ANSI/VITA 57.1-2008 - Revisions Under Consideration Change ... ... Bob Levine Mercury Mike Jadon Micro

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  • ANSI/VITA 57.1-2008 - Revisions Under Consideration The VITA 57.1 working group is considering the following changes to ANSI/VITA 57.1-2008 that would affect compliance and interoperability. NOTE: This information is provided for information only. While the working group is currently considering these changes, they may or may not be approved by the working group and may or may not become part of a revised standard. Contact VITA for more information. October 2008.

    Change of CLK*_C2M to CLK*_M2C Version 1.0 of the standard has defined clocks signals from the carrier card to the mezzanine card; CLK0_C2M_N, CLK0_C2M_P, CLK1_C2M_N, CLK1_C2M_P. It is proposed that these signals will now be redefined as additional ‘M2C’ signals.

    Original Signal Label

    (Version 1.0)

    New Signal Label

    (Version 1.1)

    CLK0_M2C_P CLK0_M2C_P

    CLK0_M2C_N CLK0_M2C_N

    CLK1_M2C_P CLK2_M2C_P

    CLK1_M2C_N CLK2_M2C_N

    CLK0_C2M_P CLK1_M2C_P

    CLK0_C2M_N CLK1_M2C_N

    CLK1_C2M_P CLK3_M2C_P

    CLK1_C2M_N CLK3_M2C_N

    A rule will also be added to state that the CLK*_M2C signals need to be populated starting at the lowest ordinal and working up

    Application Specific Signal A permission will be added to allow application specific signals to be added to the upper unused signals pins of the LA,HA and HB banks. However they will still need to meet the voltage rules for those banks.

    AC coupling to be placed on the mezzanine card All AC coupling for the DP signals will all be placed on the mezzanine card. No AC coupling will be placed on the carrier card.

    Information Only

  • ANSI/VITA 57.1-2008

    American National Standard for FPGA Mezzanine Card (FMC)

    Standard

    Secretariat VMEbus International Trade Association Approved July 2008 American National Standards Institute, Inc.

    VMEbus International Trade Association PO Box 19658, Fountain Hills, AZ 85269

    PH: 480-837-7486, FAX: Contact VITA Office E-mail: info@vita.com, URL: http://www.vita.com

    http://www.vita.com/

  • (This page left blank intentionally.)

  • ANSI/VITA 57.1-2008

    American National Standard for FPGA Mezzanine Card

    (FMC) Standard

    Secretariat VMEbus International Trade Association Approved July 2008 American National Standards Institute, Inc. Abstract This standard specifies a form factor and a pin assignment for FPGA mezzanine modules.

  • American National Standard

    Approval of an American National Standard requires verification by ANSI that the requirements for due process, consensus, and other criteria for approval have been met by the standards developer. Consensus is established when, in the judgment of the ANSI Board of Standards Review, substantial agreement has been reached by directly and materially affected interests. Substantial agreement means much more than a simple majority, but not necessarily unanimity. Consensus requires that all views and objections be considered, and that a concerted effort be made toward their resolution. The use of American National Standards is completely voluntary; their existence does not in any respect preclude anyone, whether he has approved the standards or not, from manufacturing, marketing, purchasing, or using products, processes, or procedures not conforming to the standards. The American National Standards Institute does not develop standards and will in no circumstances give an interpretation of any American National Standard. Moreover, no person shall have the right or authority to issue an interpretation of an American National Standard in the name of the American National Standard Institute. Requests for interpretations should be addressed to the secretariat or sponsor whose name appears on the title page of this standard. CAUTION NOTICE: This American National Standard may be revised or withdrawn at any time. The procedures of the American National Standards Institute require that action be taken periodically to reaffirm, revise, or withdraw this standard. Purchases of American National Standards may receive current information on all standard by calling or writing the American National Standards Institute.

    Published by VMEbus International Trade Association PO Box 19658, Fountain Hills, AZ 85269 Copyright © 2008 by VMEbus International Trade Association All rights reserved. No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without prior written permission of the publisher. Printed in the United States of America - R1.0, ISBN 1-885731-49-3

  • ANSI/VITA 57.1, FPGA Mezzanine Card (FMC) Standard

    Page 5

    TABLE OF CONTENTS

    1 Introduction ............................................................................................................... 11

    1.1. Objectives.......................................................................................................... 11 1.2. FMC Overview.................................................................................................. 12 1.3. Standard Terminology....................................................................................... 12 1.4. FMC Definitions .............................................................................................. 14 1.5. References ......................................................................................................... 15 1.6. Dimensions........................................................................................................ 15

    2 FMC Compliance ...................................................................................................... 16 2.1. FMC Mezzanine Module’s Minimum Features ................................................ 16 2.2. FMC Carrier Card’s Minimum Features........................................................... 16

    3 FMC Mezzanine Module .......................................................................................... 17 3.1. Overview ........................................................................................................... 17 3.2. Single Width Mezzanine Module...................................................................... 20 3.3. Double Width Mezzanine Module .................................................................... 21 3.4. Connectors......................................................................................................... 24

    3.4.1. Variable stacking heights .......................................................................... 25 3.4.2. Ground connections................................................................................... 27 3.4.3. Connector Pads and Labeling.................................................................... 27 3.4.4. Connector Assembly ................................................................................. 28

    3.5. Conduction Cooled Mezzanine Modules .......................................................... 29 3.5.1. Single Width Module ................................................................................ 29 3.5.2. Double Width Module............................................................................... 32 3.5.3. Conduction Cooled.................................................................................... 34 3.5.4. Thermal Interfaces..................................................................................... 34 3.5.5. Air cooled and conduction cooled compatibility ...................................... 35

    3.6. FMC Front Panel Bezel..................................................................................... 37 3.6.1. FMC Mezzanine Module to Carrier Card relationship ............................. 39

    4 FMC Carrier Card ..................................................................................................... 40 4.1. Overview ........................................................................................................... 40

    4.1.1. Carrier Card side 1 component height....................................................... 46 5 Connector Pin Assignments ...................................................................................... 48

    5.1. User Defined Pins.............................................................................................. 53 5.2. Differential Reference Clocks........................................................................... 56 5.3. Gigabit Interface................................................................................................ 58

    5.3.1. Gigabit Data Signals.................................................................................. 58 5.3.2. Gigabit reference clocks............................................................................ 60

    5.4. JTAG Signals .................................................................................................... 61 5.5. I2C Bus Signals................................................................................................. 62

    5.5.1. IPMI Support............................................................................................. 63 5.6. Geographic Addresses....................................................................................... 66 5.7. IO Mezzanine Module Present.......................................................................... 67 5.8. Power Good Signals ..........................................................