VCC
Left Right Audio (Audio)LEFT/RIGHT 4
Expansion RAS Select 3BLOBNTSC/PAL Selection 2BLOBJP3JP4
Keyboard ResetJP2JP1
BLOB 2Memory Addr. C0 vs 08BLOB 7
DESCRIPTIONREF TYPE PAGE
Mem. Exp. Main-BoardCNX RA-56H 3
Expansion Connector 7EDGE86P1
Keyboard ConnectorCN13 SIL-8 6
Internal Floppy Signal 7DIL-34Internal Floppy Power
8SIL-4CN11CN12
Video Output 5DB23PComposite Video 5RCA-JCN9CN10
Parallel Printer PortCN8CN7
SQ DIN 8Power Supply ConnectorDB25S 6
External Floppy 7DB23SRS232 Serial Port 6DB25PCN5CN6
Right Audio OutputCN4CN3
RCA-J 4Left Audio OutputRCA-J 4
Mouse/Joystick 1 2DB9PMouse/Joystick 2 2DB9PCN1CN2
DESCRIPTION PAGETYPEREF
HY1 asst 5Video Hybrid
TTL 28.63636 MHz NTSCX1OSC altTTL 28.37512 MHz PALOSC 2
DRAM 1Mx1, 150 nSU20-23U16-19
asst 9DRAM 1Mx1, 150 nSasst 3
EIA Line ReceiverU42U39
NE555 7Timer1489 4
BiMOS Op-AmpU38 1488 4EIA Line Driver
TL084 altU14 LF347 4BiMOS Op-Amp
ROM 128Kx16, 200 nSU7-8U6
8520 6Amiga VIA, 1 MHzasst 3
Denise HRU5 5719 2,4Gary
8373 alt
PaulaU4U3
8362 5Denise8364 4
Fat Agnus - PAL8372 altAgnus HR8371 alt
68000 ProcessorU2U1
8370 2Fat Agnus - NTSC68000 2
DESCRIPTIONREF CHIP PAGE
04/27/891 PCB Revision 6a/7 Production GRR
03/03/89Add E Clock Termination880283
DATEDESCRIPTIONECO NUMBER
312007312006C/A500
09/09/88GRR
A PAGE FOR SHARON AND VONNIE TO USEG. Robbins
C/A500 Main Board
C 181
APPR:ENGR:CHKD:
DATEBY:DRAWN
ONUSED ASSYNEXT
OFSHEETSCALE
SIZE
Commodore
REV
04/27/89
"Rock Lobster"
PATH: /USER/B52_LIB/ROCK_LOBSTER_REV6.X SHEET1
ECO Log
Revision History
ATTEMPT TO FORCE NODE NUMBERS VIA SEQUENCE
Key Components
Jumpers and Stuff Connectors
Signal Glossary
Schematic A500 R6a/7
A500 Rev 6a/7 PCB
+12V-12V +VID
AUDIO EXP
+5X +12X
Expansion/Tick OptionJP8JP7
BLOB 6Light Pen Port SelectBLOB 3/6
Genlock Clock Select 2BLOB7MHz Clock Option 7BLOBJP5JP6
TTL vs RS170 Comp Sync 5BLOBJP11JP10 BLOB 4RS232 Audio I/O
Cutout
see schematic 312511-01
- For older Revision 3/5 boardsREV DATEDESCRIPTION
MANAGERAPRVL
Upper / Lower Data Strobes (68000) 2,7LDS/UDSLED Power On LED /
Audio Filter Disable 4,6
Keyboard Data (Keyboard)6Keyboard Reset
(Keyboard)KBRESETKBRESETKBDATA 6
Interrupt Priority Level (68000) 2,4,7IPL[2:0]KBCLOCK Keyboard
Clock (Keyboard) 6
Interrupt Request (Chips)6,7I/O ResetIORESETINT[2,3,6]
2,4,6,7
Horizontal Sync (Video)6,7Index Pulse (Floppy)INDEXHSYNC
2,5,6
Fire Button 0/1 (Joysticks) 2,5,6FIRE0/1HLT Processor Halt
(68000) 2,7
Expansion Present / RTC Tick2,7Function Code
(68000)FC[2:0]EXTICK 2,3
Data Terminal Ready (RS232 Port) 6DTRE Peripheral Enable Clock
(68000) 2,6,7
Data Set Ready (RS232 Port) 6DSRDTACK Data Transfer Acknowledge
(68000) 2,3,7
DRAM Address Bus (DRAM)2,3,4,5DRAM Data Bus
(DRAM)DRD[15:0]DRA[8:0] 2,3
Disk Write Enable (Floppy) 4,7DKWEDMAL Chip DMA Request Line
(Chips) 2,4
Disk Read Data (Floppy)4,7Disk Write Data (Floppy)DKWDDKRD
4,7
Processor Data Bus (68000)6,7Step Direction (Floppy)DIRD[15:0]
2,3,6,7
Composite Sync (Video) 2,5CSYNCCTS Clear to Send (RS232 Port)
6
Read-Time Clock Read / Write (RTC)5Monochrome Composite Video
(Video)COMPCLKRD/WR 2,9
7.15909 MHz Quadrature Clock (Chips) 2,5,7CDACCHNG Media Change
(Floppy) 6,7
Column Address Strobe (DRAM) 2,3CASL/UCCK/CCKQ Color Clock /
Quadrature (Chips) 2,4,7
Bus Request (68000)6Device Busy (Parallel Port)BUSYBR 2,7
Blitter Slowdown (Chips) 2BLISSBLIT Chip Memory Access (Chips)
2,7
Bus Grant (68000)2,7Bus Grant Acknowledge (68000)BGACKBG 2,7
Audio Output (RS232 Jack) 4,6AUDOUTBEER Bus Error (68000)
2,7
Address Strobe (68000) 2,7ASAUDIN Audio Input (RS232 Port)
4,6
Processor Address Bus (68000) 2,3,7A[23:1]ACK Data Acknowledge
(Parallel Port) 6
28.63636 MHz Master Clock 228MHZ7MHZ 7.15909 MHz Processor Clock
2,5
DESCRIPTION (AREA) PAGESSIGNAL
External Data ReadyXRDY 2,5
External Genlock Clock (Video) 2,5XCLKXCLKEN External Clock
Enable (Video) 2,5
Write Enable (DRAM)6,7Write Protect Sense (Floppy)WPROTWE
2,3
Valid Peripheral Address (68000) 2,7VPAVSYNC Vertical Sync
(Video) 2,5,6
Transmit Data (RS232 Port) 4,6TXDVMA Valid Memory Address
(68000) 2,6,7
Step In/Out Command (Floppy)6,7Track Zero Sense (Floppy)TRK0STEP
6,7
Drive Select (Floppy) 4,6,7SEL[3:0]SIDE Side Select (Floppy)
6,7
Processor Read/Write (68000)6Select (Parallel Port)SELRW
2,6,7
Processor Reset (68000)4,6Receive Data (RS232 Port)RXDRST
2,4,7
ROM Enable (ROM) 2,3ROMENRTS Request to Send (RS232 Port) 6
Red / Green / Blue (Video)6Ring Indicate (RS232 Port)RIR/G/B
5
General Reset 6,7RESETRGA[8:1] Register Address Bus (Chips)
2,4,5
Row Address Strobe (DRAM) 2,3RAS0/1RDY Drive Ready (Floppy)
6,7
RAM Enable (Chips)2Chip Register Enable (Chips)REGENRAMEN 2
Paper Out (Parallel Port) 6POUTPPD[7:0] Parallel Port Data
(Parallel Port) 6
Pot Lines 0 X/Y (Joysticks)4,5Pot Lines 1 X/Y
(Joysticks)POT1X/1YPOT0X/0Y 4,5
Override System Decoding5Genlock Pixel Switch (Video)PIXELSWOVR
2,7
Mouse 1 Quadrature V/H (Joysticks) 5M1V/M1HOVL Overlay ROM over
RAM 2,6
Motor On - Drive 0 (Floppy)5Mouse 0 Quadrature V/H
(Joysticks)M0V/M0HMTR0 4,6,7
Light Pen Trigger (Joysticks) 2,6LPENMTR Motor On (Floppy)
4,6
DESCRIPTION (AREA)SIGNAL PAGES
rebuild for www.amigawiki.org for private use only
Rev.
1.37
(02
.09.
2012
)
