-
Design and Experiment of a Back-To-Back (BTB) System Using
Modular MultilevelCascade Converters for Power Distribution
Systems
Pracha Khamphakdi, Student Member, IEEE, Kei Sekiguchi, Makoto
Hagiwara, Member, IEEE,and Hirofumi Akagi, Fellow, IEEE
Department of Electrical and Electronic EngineeringTokyo
Institute of Technology, Tokyo, Japan
E-mail: [email protected]
Abstract This paper presents an application of the
modularmultilevel cascade converter based on double-star
chopper-cells(MMCC-DSCC) to a back-to-back (BTB) system for
installationon 6.6-kV power distribution systems. The DSCC is
characterizedby a cascade connection of multiple chopper-cells per
leg, leadingto flexible circuit design, low voltage steps, low EMI
emission,and low harmonic voltage and current. The DSCC-based
BTBsystem is equipped with neither dc capacitor nor voltage
sensoron the common dc link. The paper designs, constructs, and
tests athree-phase, 200-V, and 10-kW downscaled system to verify
andjustify its operating principles and performance.
Experimentaland simulated results agree well with each other,
showing apromising possibility of the DSCC-based BTB system.
Index Terms Back-to-back systems, grid-connected convert-ers,
modular multilevel cascade converters (MMCC)
I. INTRODUCTIONThe global warming, one of critical issues in
environment,
has resulted in calling for review in a new way of electricpower
generation. The goal of the way is to reduce CO2emission by means
of replacing a part of conventional fossil-fuel power plants with
renewable energy sources such as solarpower and wind power. This
type of generation is called oftenas distributed generators,
because most of them are installedon power distribution
systems.
Fig. 1 shows a simplified utility power distribution
systemconsisting of two 6.6-kV radial feeders in Japan, where
feeder1 has no distributed generator whereas feeder 2 has
manydistributed generators. As a result, the so-called back feedmay
occur throughout feeder 2, so that the grid voltage at theload end
of feeder 2 increases while that of feeder 1 decreases.This may
cause voltage imbalance between the two feeders,thus making it
difficult for both feeders to comply with theutility voltage code
[1].
A back-to-back (BTB) system intended for installationbetween the
ends of the two 6.6-kV distribution feeders,was designed,
constructed, and tested to mitigate the voltageimbalance. This type
of BTB system is referred to as a loopbalance controller in [2].
However, the BTB system with acommon dc-link voltage of 13.2 kV
suffered from supply (line)harmonic currents as well as EMI
emissions because it is basedon traditional two-level PWM
converters with a string of eightseries-connected 3.3-kV IGBTs per
arm.
Recently, attention has been paid to the so-called
modularmultilevel converter (MMC) for high-voltage and
high-powerapplications such as long-distance high-voltage
direct-current
BTBSystem
PrimaryDistributionTransformer
Distibuted Power Generators
Loads
Loads
Feeder 1
Feeder 2
66 kV / 6.6 kV
Fig. 1. A 6.6-kV power distribution system consisting of two
radial feeders.
(HVDC) transmission systems and BTB systems [3], [4].However,
the use of the MMC in either title or contents oftechnical papers
or articles may cause confusion about termi-nology if the reader is
not an expert of multilevel converters.To avoid this confusion, the
author of [5] classified modularmultilevel converters from circuit
topology, combining thefamily name, modular multilevel cascade
converter withdifferent given names. For example, the modular
multilevelcascade converter based on single-star bridge-cells
(MMCC-SSBC) is suitable for STATCOMs and battery energy
storagesystems, while the modular multilevel cascade converter
basedon double-star chopper-cells (MMCC-DSCC) can
achievebidirectional (ac-to-dc and dc-to-ac) power conversion.
Notethat the MMCC-DSCC (hereinafter, just called as the DSCC)is the
same in circuit configuration as the MMC in a narrowsense.
Many technical papers described the DSCC, as well asits
applications to HVDC and BTB systems, with focus oncontrol,
modeling, analysis, and/or system design [6][12].However, their
authors have confirmed the validity of their pa-pers by carrying
out computer simulation without experimentalverification. Siemens
[13] has put the DSCC-based HVDCsystems into practical use with a
trade name of HVDC-plus. All the papers published from Siemens have
madeneither description of achieving dc-capacitor-voltage
balancingof all the chopper-cells and regulating the common
dc-linkvoltage, nor disclosure of presenting experimental
waveforms.Moreover, no comparison has been made in voltage
andcurrent waveforms between experiment and simulation for
thepurpose of enhancing their reliability.
This paper has an intensive discussion on a DSCC-basedBTB system
intended for installation on the 6.6-kV distribu-tion feeders. This
BTB system is characterized by installingneither common dc-link
capacitor nor voltage sensor on the
311978-1-4799-0482-2/13/$31.00 2013 IEEE
-
DSCC-A
DSCC-B
(= )
1
8
9
16
1
8
9
16
cell
cell
cell
cell
cell
cell
cell
cell
cell
cell
cell
cell
( : 1 16)
a
c
b
(a)
(b) (c)
Fig. 2. Circuit configuration for the DSCC-based BTB system with
16cells/leg. (a) Main power circuit. (b) Chopper-cell. (c)
Center-tapped inductor(or coupled inductor).
common dc link. Modeling and analysis are done for reg-ulating
the common dc-link voltage to a preset referencevoltage. A
three-phase, 200-V, and 10-kW downscaled systemis designed,
constructed, and tested to verify the validity ofthe whole control
system in steady and transient conditions.In addition, computer
simulation using a software package ofPSCAD/EMTDC is executed under
the same conditions asthe experiment using the downscaled system.
Experimentalwaveforms agree with simulated ones well enough to
guaran-tee the reliability of both experiment and simulation.
II. CIRCUIT CONFIGURATION AND EQUATIONSA. Circuit
Configuration
Fig. 2(a) shows the circuit configuration for the DSCC-based BTB
system. Each leg consists of a cascade connectionof 16
chopper-cells depicted in Fig. 2(b), and a center-tappedinductor in
Fig. 2(c). Each chopper-cell consisting of a dccapacitor and two
IGBTs forms the so-called bidirectionalchopper. Here, is the
low-voltage-side voltage of eachchopper-cell, and is the
high-voltage-side voltage ofeach chopper-cell. Two terminals of the
center-tapped inductor,a and b are connected to the positive and
negative arms,and terminal c is connected to an ac-link inductor
sittingat the front end of the DSCC-A. The dc terminal at the
backend is directly connected to that of the DSCC-B without
anydc-link capacitor.
Let the common dc-link current and voltage be and ,
respectively. The instantaneous active power at the dc link,, is
given by
= . (1)
B. Circuit EquationsIn Fig 2(a), and are the positive and
negative
arm currents, and is the supply current. The followingequations
exist
= + , (2)
=1
2( + ), (3)
where is the circulating current along the dc loop in the-phase
leg, which is defined in [6]. Note that containsonly a dc component
under an ideal condition [6]. From (2)and (3), the arm currents and
can be expressed byusing and as follows:
= 12, (4)
= +1
2. (5)
Note that , , and are the branch currents, while is the loop
current that cannot be measured directly.
The dc-link current can be expressed from Kirchhoffscurrent law
(KCL) as follows:
=
=,,
,
=
=,,
( 12),
=
=,,
. (6)
where the relation of + + = 0 is utilized.Equation (6) means
that the supply currents produce no effecton the dc-link current
.
Each arm of the DSCC in Fig. 2(a) is represented bya voltage
source equal to the sum of the low-voltage-sidevoltages of the
chopper-cells. For example, of the DSCC-A,the -phase collective
positive-arm and negative-arm voltages, and , are expressed as
follows:
=
/2=1
, (7)
=
=1+2
, (8)
312
-
where is the number of the chopper-cells per leg. The-phase
collective leg voltage of the DSCC-A, , isobtained from (7) and (8)
as
= + =
=1
. (9)
The following equation exists in the -phase leg of the DSCC-A
as
= +
. (10)
The center-tapped inductor presents inductance only tothe
circulating current , and no inductance to the supplycurrent [6].
In other words, provides no effect onthe voltage across the
center-tapped inductor.
Finally, making reference to the Appendix can express and as
=1
6
( =,,
+
=,,
), (11)
=
1
2
( =,,
=,,
). (12)
Equation (11) means that is equal to the average valueof all the
low-voltage-side voltages of the chopper-cells usedin the BTB
system. Moreover, is independent of and. Equation (12) means that
the dc-link current can becontrolled by adjusting a voltage
difference between the sumof the low-voltage-side voltages of the
DSCC-A and that ofthe DSCC-B.
III. CONTROL METHODThe control method for the DSCC-based BTB
system can
be classified into the following four parts: control of
instantaneous active and reactive power [16] at
the ac mains, voltage control of the floating dc capacitors,
control of the dc-link voltage, and control of the dc-link
current.
The power control is achieved by using the synchronousreference
frames along with the decoupled current control.
The voltage control of the dc capacitors can be achieved
byapplying the control method proposed in [6] and [7]. Notethat the
aim of the voltage control is not to regulate theinstantaneous
voltage of each dc capacitor, but to regulatethe mean voltage with
the help of a moving-average filterof 50 Hz [8].
A. Control of the DC-Link VoltageThe following reasonable
assumption is made in (11):
=,,
+
=,,
= 6. (13)
This assumption is valid because the six legs are operatedin the
same way, especially in terms of the dc components.Substituting
(13) into (11) yields
= . (14)Equation (9) indicates that contains no
fundamental-frequency component, because those included in and
cancel out each other. Hence, contains only adc component if the
switching-ripple components are ignored.Let the dc component
included in be (). Equation(14) is changed from (9) to
= (). (15)The chopper-cell can produce an arbitrary dc voltage,
so longas it is lower than the dc-capacitor voltage [6]. This paper
sets() as follows:
() =1
2 , (16)
where is the average value of all the dc-capacitor voltagesused
for the BTB system. Substituting (16) into (15) yields
=1
2 . (17)
Equation (17) means that can be regulated by adjusting . For
example, is regulated at 400 V when = 50 Vand = 16. It is possible
to force to follow the reference by applying an appropriate
feedback control of the dc-capacitor voltages, which has already
proposed in [6] and[7]. This method is characterized by indirectly
regulating ,thus making it possible to eliminate a voltage sensor
and a dccapacitor from the common dc-link of the BTB system.
B. Control of the DC-Link CurrentEquation (6) means that the
dc-link current is expressed
by the circulating currents. This implies that can beadjusted
indirectly by controlling these circulating currents.The reference
for the dc-link current, , is given by
=
/2, (18)
where is the active power reference and /2 correspondsto the
dc-link voltage as predicted from (17). The referencesfor the
circulating currents of the DSCC-A and the DSCC-B, and , are
expressed as
= = 3. (19)
Note that each chopper-cell should produce an amount ofvoltage
for adjusting the corresponding circulating current [6].For
example, each chopper-cell in the -phase leg of theDSCC-A produces
the voltage that is given by
313
-
200 V50 Hz
200 V/200 V 200 V/200 V
=
(= 0)
PT PT
MUX MUX
Fig. 2(a)
DSCC-A DSCC-B
2 2
48
6
48
66 6
96 96
gatesignals
DSP(TMS320C6713)
FPGA-A (Altera Cyclone II)A/D Converters
FPGA-B (Altera Cyclone II)A/D Converters
MUX : Multiplexer
Fig. 3. Overview of the three-phase, 200-V, and 10-kW
experimental system.
=
( ), (20)where is the feedback gain. Considering the above
equa-tion allows the -phase collective leg voltage of the DSCC-A,,
to be changed from (14) to the following equation:
= + . (21)The similar equations exist in the other five legs.
Equations(6), (19), and (20) produce the following equation:
=,,
=
=,,
=
( ). (22)
The dc-link current can be expressed from (12), (21), and (22)as
follows:
=
1
2
[ =,,
=,,
]
=
( ). (23)
Hence, the actual dc-link current exhibits a first-orderresponse
to its reference with a time constant of / .Moreover, can be
controlled, independent of .
IV. EXPERIMENT AND SIMULATIONA. System Configuration Used for
Experiment and Simulation
Fig. 3 shows the overview of the three-phase, 200-V, and 10-kW
experimental system, that is used as a downscaled systemof the
6.6-kV BTB system. Table I summarizes the circuitparameters used in
experiment and simulation. Each DSCChas eight chopper-cells per
arm. Hence, the total number ofchopper-cells used for the BTB
system is 96 (= 862). EachDSCC is connected to the three-phase
200-V ac mains via
TABLE ICIRCUIT PARAMETERS USED IN THE EXPERIMENT AND
SIMULATION
Rated power 10 kWNominal line-to-line rms voltage 200 V
Nominal line frequency 50 HzAC-link inductor 2 mH (16%)*Coupled
inductor 3 mH (24%)*
Number of chopper-cells per leg 16DC-link voltage 400 V
DC-capacitor voltage 50 V (= 400 V/8)DC-capacitor 6.6 mF
Unit capacitance constant [15] 40 ms at 50 VPWM carrier
frequency 450 Hz
Switching-ripple frequency 16 7.2 kHz*These values are on a
200-V, 10-kW, and 50-Hz base.
ac-link inductors = 2.0 mH (16%) and a line-frequencytransformer
with unity voltage ratio for galvanic isolation. Thecenter-tapped
inductor shown in Fig. 2(c) has an inductancevalue of = 3.0 mH
(24%). Although the inductance valueof is larger than that of , the
size of the center-tappedinductor is half of the ac-link inductor
in volume because presents no inductance to the supply current. The
capacitancevalue of the dc capacitor is = 6.6 mF, which
correspondsto = 40 ms in the unit capacitance value [15].
Eachchopper-cell uses four power MOSFETs connected in parallelas a
power switch for reducing the conduction loss, thusmaking the
experimental system more reliable and effective asa downscaled
system of the 6.6-kV BTB system. The referencevalue for the
dc-capacitor voltage is set as = 50 V. Notethat neither electric
capacitor nor film capacitor is connectedto the common dc-link
terminals.
The control systems consists of a digital signal processor(DSP)
unit using the Texas Instruments TMS320C6713 andtwo
field-programmable gate array (FPGA) units using theAltera Cyclone
II. Each FPGA unit including A/D convertersdetects the 48
dc-capacitor voltages, the positive and negativearm currents, and
the ac-mains voltages. These signals are sent
314
-
20 ms [V]
400
0-400
[V]
400
0-400
[A]
50
0
-50
THD of = 0.24%[A]
50
0-50
[A]
500
-50
[V]19
755025
0
19
[V]
600400200
0
[A]
50
0-50
() = 77.8 V
24.7 A
Fig. 4. Experimental waveforms during rectification ( = 10 kW, =
0kVA).
to the A/D converters. Note that the dc-link voltage is
notdetected. Here, the multiplexer (MUX) unit is used to reducethe
number of A/D converters from 48 to six. The FPGA unitproduces
96-bit (= 2 48) gate signals in total, because eachchopper-cell
includes two power switches.
The experimental waveforms were taken by using a
personalcomputer via the Yokogawa WE7000 PC-based data acquisi-tion
system. The sampling frequency is 100 kHz in Figs. 4and 5, and 50
kHz in Figs. 6 and 7.
The PSCAD/EMTDC software package is used for sim-ulation. The
following conditions are considered:
one-sampling delay of 140 s (= 1/(16 )) resultingfrom digital
control, and a dead time of 8 s, and
each chopper-cell uses ideal power switches with noswitching
interval of time.
B. Operating Performance Under Steady-State ConditionsFig. 4
shows the experimental waveforms when the DSCC-
A acts as a rectifier ( = 10 kW and = 0 kVA). Here, and
represent the power references for the instantaneousactive and
reactive powers at the ac mains. Note that hasa positive value when
active power is transferred from theDSCC-A to the DSCC-B, and vice
versa.
The ac-terminal (front-end) line-to-line voltages ,, and get
multilevel PWM waveforms with avoltage step of 25 V (= 400 V/16).
As a consequence,
20 ms [V]
400
0-400
[V]
400
0-400
[A]
50
0
-50
THD of = 0.25%[A]
50
0-50
[A]
500
-50
[V]19
755025
0
19
[V]
600400200
0
[A]
50
0-50
() = 84.3 V
24.6 A
Fig. 5. Simulated waveforms during rectification ( = 10 kW, =
0kVA).
they contain much less harmonic voltages and much
lesscommon-mode voltage than a traditional two-level voltage-source
PWM inverter. Since the carrier frequency of eachchopper-cell is
450 Hz, the switching-ripple frequency is7.2 kHz (= 450 Hz16). As a
result, the waveforms of thesupply currents , , and look purely
sinusoidalwith a 50-Hz fundamental-frequency component. The
totalharmonic distortion (THD) value of is less than 1%.
The arm currents, and , contain dc compo-nents, 50-Hz
fundamental-frequency components, 3.6-kHz (=450 Hz8)
switching-ripple components, and 100-Hz second-order harmonic
components resulting from the control system[6]. However, no 100-Hz
component appears in becausethose included in and cancel out each
other. Thecirculating current contains a dc component of 8.3 A(=
10kW/(3 400V)), the 3.6-kHz switching-ripple com-ponent, and the
100-Hz second-order harmonic component.However, the 100-Hz
component is small enough comparedto the dc component in terms of
amplitude.
The dc-capacitor voltages 1 and 9 contain bothdc and ac
components, as shown in Fig. 4, where the voltagecontrol regulates
the dc component at 50 V. The ac componentsconsist of the most
dominant 50-Hz component and the seconddominant 100-Hz component.
Both components are propor-tional to the amplitude of , and
inversely proportionalto [18]. The mean dc-link voltage is
regulated at 400V without any steady-state error because each
dc-capacitor
315
-
100 ms [kW]
100
-10[V]
400
0
-400
[V]
400
0-400
[A]
50
0
-50
[A]
50
0
-50
[A]
50
0
-50
[V]19
755025
0
9 1
[V]
600400200
0
[A]
50
0-50
() = 101.7 V
24.6 A
24.3 A
Fig. 6. Experimental waveforms during transient state from the
ratedrectification to inversion mode
voltage is regulated at 50 V. The dc-link current has a
dccomponent of 25 A, which agrees well with the theoreticalvalue
obtained from (18).
Fig. 5 shows the simulated waveforms when the DSCC-A acts as a
rectifier ( = 10 kW and = 0 kVA).This simulation was carried out
under the same conditionsas the experiment. Comparing Fig. 4 with 5
shows that bothwaveforms agree well with each other, bringing high
reliabilityto both experiment and simulation.
C. Operating Performance under a Transient-State ConditionFigs.
6 and 7 show the experimental and simulated wave-
forms of the DSCC-A, in which the active-power referenceis
changed from 10 kW to 10 kW under a ramp changein 100 ms. Here, is
set to zero. This means that theDSCC-A changes its operation from
rectification to inver-sion. Comparing Fig. 6 with 7 reveals that
experiment andsimulation agree well with each other even under such
atransient-state condition. No overcurrent occurs in the
supplycurrents, the arm currents, the circulating current, and the
dc-link current. Moreover, the dc-capacitor voltages and the
dc-link voltage are well regulated to their references even
duringthe transient period. Carefully looking into reveals thatthe
switching-ripple component (), increases slightly
100 ms [kW]
100
-10[V]
400
0
-400
[V]
400
0-400
[A]
50
0
-50
[A]
50
0
-50
[A]
50
0
-50
[V]19
755025
0
9 1
[V]
600400200
0
[A]
50
0-50
() = 101.1 V
24.3 A
24.5 A
Fig. 7. Simulated waveforms during transient state from the
rated rectificationto inversion mode
during the transient state. However, it is about 25% in
peak-to-peak of the mean value of 400 V, which is within an
acceptablevalue.
V. CONCLUSION
This paper has described an application of a modularmultilevel
cascade converter based on double-star chopper-cells (MMCC) to a
back-to-back (BTB) system, intended forinstallation on 6.6-kV power
distribution systems. The derivedcircuit equations of the BTB
system has shown that the dc-linkvoltage and current can be
controlled independently withoutany mutual inference. Moreover, an
indirect control of the dc-link voltage developed in this paper has
eliminated neithera voltage sensor nor dc-link capacitors from the
dc link.The validity and effectiveness of the BTB system has
beenconfirmed and justified by both experiment using a three-phase,
200-V, and 10-kVA downscaled system and simulationusing the
PSCAD/EMTDC software package.
VI. ACKNOWLEDGEMENT
The authors would like to thank the Japanese ministry ofeconomy,
trade and industry for financially supporting thisresearch
project.
316
-
APPENDIXA. Derivation of equations (11) and (12)
When attention is paid to either DSCC-A or DSCC-B,making
reference to (10) allows to be expressed as follows:
=1
3
( =,,
+
=,,
), (24)
=1
3
( =,,
+
=,,
). (25)
The dc-link current is expressed from Fig. 2(a) andKirchhoffs
current law (KCL) as
=
=,,
,
=
=,,
. (26)
Substituting (26) into (24) and (25) yields
=1
3
( =,,
), (27)
=1
3
( =,,
+
). (28)
Equations (27) and (28) give (11) for and (12) for .
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/MonoImageDownsampleType /Bicubic /MonoImageResolution 600
/MonoImageDepth -1 /MonoImageDownsampleThreshold 1.00167
/EncodeMonoImages true /MonoImageFilter /CCITTFaxEncode
/MonoImageDict > /AllowPSXObjects false /CheckCompliance [ /None
] /PDFX1aCheck false /PDFX3Check false /PDFXCompliantPDFOnly false
/PDFXNoTrimBoxError true /PDFXTrimBoxToMediaBoxOffset [ 0.00000
0.00000 0.00000 0.00000 ] /PDFXSetBleedBoxToMediaBox true
/PDFXBleedBoxToTrimBoxOffset [ 0.00000 0.00000 0.00000 0.00000 ]
/PDFXOutputIntentProfile (None) /PDFXOutputConditionIdentifier ()
/PDFXOutputCondition () /PDFXRegistryName () /PDFXTrapped
/False
/CreateJDFFile false /Description > /Namespace [ (Adobe)
(Common) (1.0) ] /OtherNamespaces [ > /FormElements false
/GenerateStructure false /IncludeBookmarks false /IncludeHyperlinks
false /IncludeInteractive false /IncludeLayers false
/IncludeProfiles true /MultimediaHandling /UseObjectSettings
/Namespace [ (Adobe) (CreativeSuite) (2.0) ]
/PDFXOutputIntentProfileSelector /NA /PreserveEditing false
/UntaggedCMYKHandling /UseDocumentProfile /UntaggedRGBHandling
/UseDocumentProfile /UseDocumentBleed false >> ]>>
setdistillerparams> setpagedevice
