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1 Advanced Digital Design with the Verilog HDL Michael D. Ciletti [email protected] Copyright 2003, 2004, 2005 M.D. Ciletti Selected Solutions Updated: 10/31/2005 Solutions to the following problems are available to faculty at academic institutions using Advanced Digital Design with the Verilog HDL. This list will be updated as additional solutions are developed. Request the solutions by contacting the author directly ([email protected] ). Chapter 2: #1, 2, 3, 4, 5, 8, 9, 10, 12 Chapter 3: #1, 2, 4, 5, 6, 7, 9, 10, 11 Chapter 4: #1, 2, 4, 7, 10, 11, 12, 14, 15, 16 Chapter 5: #1, 2, 3, 4, 6, 7, 8, 9, 10, 11, 13, 16, 17, 18, 19, 20, 23, 24, 26, 27, 28, 29, 30, 32, 33 Chapter 6: #4, #7, 8, 21 Chapter 7: #12 Chapter 9: #12, #18, #19 Copyright 2004, 2005 Note to the instructor: These solutions are provided solely for classroom use in academic institutions by the instructor using the text, Advance Digital Design with the Verilog HDL by Michael Ciletti, published by Prentice Hall. This material may not be used in off-campus instruction, resold, reproduced or generally distributed in the original or modified format for any purpose without the permission of the Author. This material may not be placed on any server or network, and is protected under all copyright laws, as they currently exist. I am providing these solutions to you subject to your agreeing that you will not provide them to your students in hardcopy or electronic format or use them for off-campus instruction of any kind. Please email to me your agreement to these conditions. I will greatly appreciate your assisting me by calling to my attention any errors or any other revisions that would enhance the utility of these slides for classroom use. rev 10/10/2005

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1Advanced Digital Design with the Verilog HDL Michael D. Ciletti [email protected] Copyright 2003, 2004, 2005 M.D. Ciletti Selected Solutions Updated: 10/31/2005 Solutions to the following problems are available to faculty at academic institutions using Advanced Digital Design with the Verilog HDL. This list will be updated as additional solutions are developed. Request the solutions by contacting the author directly ([email protected]). Chapter 2: #1, 2, 3, 4, 5, 8, 9, 10, 12 Chapter 3: #1, 2, 4, 5, 6, 7, 9, 10, 11 Chapter 4: #1, 2, 4, 7, 10, 11, 12, 14, 15, 16 Chapter 5: #1, 2, 3, 4, 6, 7, 8, 9, 10, 11, 13, 16, 17, 18, 19, 20, 23, 24, 26, 27, 28, 29, 30, 32, 33 Chapter 6: #4, #7, 8, 21 Chapter 7: #12 Chapter 9: #12, #18, #19

Copyright 2004, 2005 Note to the instructor: These solutions are provided solely for classroom use in academic institutions by the instructor using the text, Advance Digital Design with the Verilog HDL by Michael Ciletti, published by Prentice Hall. This material may not be used in off-campus instruction, resold, reproduced or generally distributed in the original or modified format for any purpose without the permission of the Author. This material may not be placed on any server or network, and is protected under all copyright laws, as they currently exist. I am providing these solutions to you subject to your agreeing that you will not provide them to your students in hardcopy or electronic format or use them for off-campus instruction of any kind. Please email to me your agreement to these conditions.

I will greatly appreciate your assisting me by calling to my attention any errors or any other revisions that would enhance the utility of these slides for classroom use.

rev 10/10/2005

2Advanced Digital Design with the Verilog Hardware Description Language Michael D. Ciletti Prentice-Hall, Pearson Education, 2003 Problem 2-1 F(a, b, c) = m(1, 3, 5, 7) Canonical SOP form: F(a,b,c) = a'b'c + a'bc + ab'c + abc Also: K-map for F:

bc a 0 1 00 01 11 10 0m0

1m1

1m3

0m2

0m4

1m5

1m7

0m6

F' = m0 + m2 + m4 + m6 F' = a'b'c' + a'bc' + a'bc + abc F = (a'b'c' + a'bc' + a'bc + abc)' F = (a'b'c')' (a'bc')' (a'bc)' (abc)' Canonical POS form: F = (a + b + c)(a + b' +c) (a + b' + c') (a' + b' +c')

3Advanced Digital Design with the Verilog Hardware Description Language Michael D. Ciletti Prentice-Hall, Pearson Education, 2003 Problem 2-2 F(a, b, c, d) = M(0, 1, 2, 3, 4, 5, 12) F(a, b, c, d) = (a+ b + c + d)(a + b + c + d)(a + b + c + d)(a + b + c + d)(a + b + c + d)(a + b + c + d)(a + b + c + d)

4Advanced Digital Design with the Verilog Hardware Description Language Michael D. Ciletti Prentice-Hall, Pearson Education, 2003 Problem 2-3 F(a, b, c) = a'b + c

bc a 0 1 00 01 11 10 0m0

1m1

1m3

1m2

0m4

1m5

1m7

0m6

F(a, b, c) = m1 + m2 + m3 + m5 + m7 F(a, b, c) = a'b'c + a'bc' + a'bc + ab'c + abc

5Advanced Digital Design with the Verilog Hardware Description Language Michael D. Ciletti Prentice-Hall, Pearson Education, 2003 Problem 2-4 F(a, b, c, d) = a'bcd' + a'bcd + a'b'c'd' + a'b'c'd = m6 + m7 + m0 + m1 F(a, b, c, d) = m(0, 1, 6, 7)

6Advanced Digital Design with the Verilog Hardware Description Language Michael D. Ciletti Prentice-Hall, Pearson Education, 2003 Problem 2-5 G(a, b, c, d) = (a'bcd' + a'bcd + a'b'c'd' + a'b'c'd)' G'(a, b, c, d) = a'bcd' + a'bcd + a'b'c'd' + a'b'c'd K-map for G':

cd ab 00 01 11 10 00 01 11 10 1m0

1m1

0m3

0m2

0m4

0m5

1m7

1m6

0m12

0m13

0m15

0m14

0m8

0m9

0m11

0m10

G(a, b, c) = m(2, 3, 4, 5, 8, 9, 10 , 11, 12, 13, 14, 15)

7

Advanced Digital Design with the Verilog Hardware Description Language Michael D. Ciletti Prentice-Hall, Pearson Education, 2003

Problem 2-8 (a) (b) (c) (ab + ab) = ab + ab (b + (cd + e)a) = b(c + d) e + a ((a + b + c)(b + c)(a + c)) = abc + bc + ac

8Advanced Digital Design with the Verilog Hardware Description Language Michael D. Ciletti Prentice-Hall, Pearson Education, 2003

Problem 2-9 (a) (b) (c) F = a + ab = a + b F = a(a + b) = ab F = ac + bc + ab = ac + bc

9Advanced Digital Design with the Verilog Hardware Description Language Michael D. Ciletti Prentice-Hall, Pearson Education, 2003

Problem 2-10a F(a, b, c) = m(0, 2, 4, 5, 6)

bc a 0 1 00 01 11 10 1m0

0m1

0m3

1m2

1m4

1m5

0m7

1m6

F(a, b, c) = m(0, 2, 4, 5, 6) = ab' + c'

10Advanced Digital Design with the Verilog Hardware Description Language Michael D. Ciletti Prentice-Hall, Pearson Education, 2003

Problem 2-10b F(a, b, c) = m(2, 3, 4, 5)

bc a 0 1 00 01 11 10 0m0

0m1

1m3

1m2

1m4

1m5

0m7

0m6

F(a, b, c) = m(2, 3, 4, 5) = ab' + a'b = a b

11Advanced Digital Design with the Verilog Hardware Description Language Michael D. Ciletti Prentice-Hall, Pearson Education, 2003

Problem 2-10e (e) F = abc + bcd + abcd + abccd ab 00 01m4 m5 m7

00

01

11m3

10

1

m0

1m1

1 1

m2

m6

11m12 m13 m15 m14

10

1m8

1m9 m11

1m10

F = bc + bd + acd

12Advanced Digital Design with the Verilog Hardware Description Language Michael D. Ciletti Prentice-Hall, Pearson Education, 2003

Problem 2-12 Karnaugh Map for f = m(0, 4, 6, 8, 9, 11, 12, 14, 15)

cd ab 00c'd'

00 01 11 10 1m0

0m1

0m3

0m2

bd'

01 11 10

1m4

0m5

0m7

1m6

1m12

0m13

1m15

1m14

1m8

1m9

1m11

0m10

abc ab'c' ab'd acd

1. Prime implicants are implicants that do not imply any other implicant Answer: c'd', ab'c', ab'd, acd, abc, bd' 2. Essential prime implicants are prime implicants that cannot be covered by a set of other implicants: Answer: c'd', bd' 3. A minimal expression consists of the set of essential prime implicants together with other implicants that cover the function: Answer: f = c'd' + bd' + ab'd + abc f = c'd' + bd' + ab'd + acd f = c'd' + bd' + ab'c' +acd

13Advanced Digital Design with the Verilog Hardware Description Language Michael D. Ciletti Prentice-Hall, Pearson Education, 2003 Problem 3 1

ASM Chart - Moore Machine reset s0 / 000

AB

11

01, 10

State transition graph - Moore Machine00 s0 0 00 01, 10 11 s1 0 01, 10 11 00 11 00 s4 100 Problem 3.1, mdc 9/9/2004 00 00

s1 / 0 AB11

01, 10

s2 / 0 AB11

01, 10 00 s2 0 01, 10 s3 0 01, 10 11 11

01, 10

s3 / 000

AB

11

01, 10

s4 / 1 AB11 01, 10

14Problem 3 - 2 Advanced Digital Design with the Verilog Hardware Description Language Michael D. Ciletti Prentice-Hall, Pearson Education, 2003 9/26/ 2006clk rst

Bit_in Par_Detect

Parity

rst s0 1 0

1 s1 0

Assumption: asynchronous reset Bit_in clocked on rising edge. Interpretation: Even parity will be asserted unless an odd number of 1s have been received.

0 1

Bit_in

D

SET

Q

parityCLR

Q

clock rst

15Problem 3 - 4

Advanced Digital Design with the Verilog Hardware Description Language Michael D. Ciletti Prentice-Hall, Pearson Education, 2003 9/24/ 2003State transition graph - Mealy Machine reset0 s0 1/0 s1 1/0 s2 1/0 1/1 Note: s2 and s3 are equivalent states. s3

0/0 0/0 0/0

State transition graph - Equivalent Mealy Machine reset0 s0 1/0 s1 1/0 1/1

s2

0/0 0/0

Problem 3 5State transition graph - Moore Machine reset0 s0 0 1 s1 0 0 0 0 1 s2 0 1 1

s3 1

16Advanced Digital Design with the Verilog Hardware Description Language Michael D. Ciletti Prentice-Hall, Pearson Education, 2003 9/26/ 2005 Problem 3 - 6 No static-0 or static-1 hazards.

17Advanced Digital Design with the Verilog Hardware Description Language Michael D. Ciletti Prentice-Hall, Pearson Education, 2003 9/24/ 2003 Problem 3 - 7

B_in = 1

B_in = 0 reset

S_00 0

B_in = 0

S_10 0

B_in = 1

S_11 0

B_in = 1

S_21 0

B_in = 1

S_31 1

B_in = 0 B_in = 1 B_in = 0 B_in = 0

Advanced Digital Design with the Verilog Hardware Description Language Michael D. Ciletti Prentice-Hall, Pearson Education, 2003 9/13/ 2004

18Advanced Digital Design with the Verilog Hardware Description Language Michael D. Ciletti Prentice-Hall, Pearson Education, 2003 9/26/ 2005 Problem 3 - 8

clk

rst

clk_bar

rst

Bit_in Pattern_Detect

Detect Counter_of_6

Done

Approach: linked state machines, with the sequence detector asserting a signal that increments a counter. To avoid race conditions, the counter is clocked on the opposite edge of the clock that drives the sequence detecter. Assumption: asynchronous reset. Bit_in clocked on rising edge. LSB (1) of 0111 arrives first. Transitions for reset condition are omitted for simplicity. Bit_in 0 1 rst s0 0 1 0 0 0 Detect 0 rst s0 0 1 s1 0 0 1 s2 0 0 1 s3 0 0 1 s4 0 0 1 s5 0 0 1 s6 1 Done s1 0 1 s2 0 1 s3 0 0 s4 1 Detect 1

19Assumption: asynchronous reset. Bit_in clocked on rising edge. MSB (0) of 0111 arrives first. Transitions for reset condition are omitted for simplicity. Bit_in 1 rst s0 0 0 0 0 0 0 s1 0 1 s2 0 1 s3 0 1 s4 1 Detect 0

Detect 0 rst s0 0 1 s1 0 0 1 s2 0 0 1 s3 0 0 1 s4 0 0 1 s5 0 0 1 s6 1 Done

20Advanced Digital Design with the Verilog Hardware Description Language Michael D. Ciletti Prentice-Hall, Pearson Education, 2003 Problem 3 - 9State transition graph - NRZ - NRZI Moore Machine1 0 s0 0 1 s1 1 0

Sample at the midpoint of the bit time. module NRZ_NRZI (B_out, B_in, clk, rst); // problem 3.9 output B_out; input B_in; input clk, rst; parameter s0 = 0; parameter s1 = 1; reg state, next_state; reg B_out; always @ (negedge clk or posedge rst) if (rst == 1) state =A) && (D>=B) && (D>=C)) GTE = GTE | 4'b0001; if ((A= D); C_GT = (C >= A) && (C >= B) && (C >= D); D_GT = (D >= A) && (D >= B) && (D >= C); A_LT = (A