Panel Summaries

THE 6TH IEEE Latin American Test Workshop

(LATW 05), took place from 30 March to 2 April 2005

in Salvador, Brazil. The workshop included a panel dis-

cussion on the challenges for modern design and test

education, which attracted much attention from the

audience.

I organized the panel discussion, and Magdy Abadir

of Freescale Semiconductor served as moderator.

Participants included José Luis Huertas (Centro Nacional

de Microelectrónica, Spain), Yervant Zorian (Virage

Logic), Fernando Silveira (Universidad de la República,

Uruguay), Cesar Dueñas (BSTC-Freescale, Brazil), and

Pascal Nouet (LIRMM—Laboratory of Data Processing,

Robotics, and Microelectronics in Montpellier, France).

Cesar Dueñas commented that there is a large gap

between the research taking place in universities and the

actual needs of industry. Both sides are responsible:

Industry people tend to require short-term results, and uni-

versity people—trying to be as creative as possible—tend

to pursue ideas that are not always useful. The solution for

this dilemma would pass through professors because they

are the ones that can actually fill the gap between com-

panies and students. One possible strategy is to open up

internship positions in companies. Professors could then

work at a company for a certain period, and when they

return to their university, they would bring with them a fla-

vor of the current industry needs.

Pascal Nouet brought up the challenge that new

devices and designs pose to both professors and stu-

dents: Today’s designs demand mastery of an increas-

ing number of disciplines in addition to the traditional

disciplines such as fundamental mathematics, physics,

and circuits. Moreover, the increasing complexity of

designs requires engineers to be knowledgeable in

many different abstraction levels, ranging from basic cir-

cuit equations to software engineering. Commenting on

the gap between universities and industry, Nouet noted

the successful LIRMM experience in which companies

donated a state-of-the-art tester to the laboratory; in

exchange, LIRMM provided training for all companies

wishing to use the tester. This exchange exposed stu-

dents to highly complex equipment at reasonable costs

and brought companies inside the university.

Fernando Silveira commented that specifically in

Latin America there is a lack of industries wishing to

invest money in research. This causes a cycle in which

fewer students follow engineering careers in the design-

and-test field, resulting in less research in the field.

José Luis Huertas mentioned that the widening gap

between industry and universities in the areas of design

and test can only decrease if professors take a bold step

toward developing new technologies. Hence, joint uni-

versity-company research—even with start-up compa-

nies—is the way to go.

Yervant Zorian stressed that the way to be successful

in the design-and-test field is to develop expertise in the

field. This idea is certainly not confined to just this field.

Education should have a broader sense, and should be

strong in the fundamentals that will be necessary for the

rest of an electronic engineer’s life. Another important

aspect is that universities tend to train people to work

alone, since that is the evaluation method that universi-

ties currently use. In a company, on the other hand,

teamwork is what matters; hence, universities should

include collaborative work in their curricula.

Magdy Abadir proposed the discussion of start-ups

as a means to develop new insights and develop a path

to bring technology to developing countries.

The panel concluded that funding is fundamental

Adding value to design and test througheducation: What are the challenges?Luigi Carro

Federal University of Rio Grande do Sul

388 0740-7475/05/$20.00 © 2005 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers

continued on p. 390

390 IEEE Design & Test of Computers

Conference Reports

transient errors in memory arrays.

The workshop had 17 paper presentations in six ses-

sions with ample general discussion time after each ses-

sion. It started with an industrial perspectives session,

followed by a session on logic-soft-error modeling and

analysis techniques to understand system behaviors in

the presence of soft errors. Next, three design sessions

presented circuit-, logic-, and system-level design tech-

niques for soft-error mitigation. Organizers plan the pub-

lication of a position paper as an outcome of this

workshop.

One key outcome was the observation that logic soft

errors will be a major concern in sub-65-nm technolo-

gies. Although partially depleted silicon-on-insulator

(SOI) processes can provide a five-fold soft-error rate

reduction, SOI alone cannot eliminate the risk. Another

outcome of the workshop was that participants identi-

fied the need for automated tools to better predict sys-

tem-level derating of logic soft errors.

SELSE-1 was sponsored by the Coordinated Science

Laboratory of the University of Illinois at Urbana-

Champaign, the IEEE Computer Society’s Test

Technology Technical Council, Advanced Micro

Devices Inc., Hewlett-Packard, IBM, Intel, and iRoC

Technologies. Generous sponsorship from the five com-

panies allowed a reduced registration fee of $25 for stu-

dents. The 70 registrants came from a broad range of

industry and academic institutions, including the

California Institute of Technology; Northeastern

University; University of California, Davis; University of

Illinois at Urbana-Champaign; University of Michigan;

University of New South Wales, Australia; The University

of Texas at Austin; Advanced Micro Devices; Cypress

Semiconductor; Hewlett-Packard; iRoC Technologies;

IBM; Intel; Medtronic Inc.; and Texas Instruments.

SELSE-2 will take place in 2006, and the SELSE com-

mittee will begin accepting submissions for SELSE-2 in

the fall of 2005. For more information, access the SELSE

Web site at http://www.crhc.uiuc.edu/SELSE. Please

direct questions about SELSE-2 to the SELSE-1 cochairs,

Subhasish Mitra (subhasish.mitra@intel.com) and Pia

Sanda (sanda@us.ibm.com), program chair Wendy

Bartlett (wendy.bartlett@hp.com), TTTC contact

Yervant Zorian (yervant.zorian@viragelogic.com), or

local-arrangements chair Sanjay Patel (sjp@crhc.uiuc.

edu). The SELSE organizing committee thanks the TTTC

for encouraging and sponsoring this workshop.

CONTRIBUTIONS TO CONFERENCE REPORTS:Send conference reports to Yervant Zorian, VirageLogic, 47100 Bayside Parkway, Fremont, CA 94538;zorian@viragelogic.com.

because university laboratories must resemble the actu-

al environment in which students will work when they

begin their careers. Beside that crucial input, constant

discussion among professors and company representa-

tives in conferences and workshops is a great way to

bridge the gap between education and present-day

challenges in design and test.

The next panel discussion will take place at LATW

2006 in Buenos Aires, from 26 to 29 March 2006. For

more information, please see http://www.latw.net.

CONTRIBUTIONS TO PANEL SUMMARIES: Sendpanel summaries to Yervant Zorian, Virage Logic,47100 Bayside Parkway, Fremont, CA 94538; zorian@viragelogic.com.

continued from p. 388

Join a community that targets your discipline.

In our Technical Committees, you’re in good company.

www.computer.org/TCsignup/

Looking for a community targeted to yourarea of expertise? IEEE Computer SocietyTechnical Committees explore a variety

of computing niches and provide forums fordialogue among peers. These groups influenceour standards development and offer leadingconferences in their fields.

JOIN A THINKTANK