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Adders and Multipliers Review

Adders and Multipliers Review. ARITHMETIC CIRCUITS Is a combinational circuit that performs arithmetic operations, e.g. –Addition –Subtraction –Multiplication

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Adders and Multipliers

Review

ARITHMETIC CIRCUITS

• Is a combinational circuit that performs arithmetic operations, e.g.

– Addition– Subtraction– Multiplication– Division

with numbers in binary form.

Half Adder

• Generates the sum of 2 binary digits.

X

Y

Sum = X Y

Cy = X.Y

Truth Table of Half Adder

Logic Diagram of Half Adder

Full Adder

• Forms the arithmetic sum of 3 input bits.

X

Y

Sum = X Y Z

Cout = X.Y + Z (X Y)Cin

Truth Table of Full Adder

K-Maps for Full Adder

Full Adder

• A Full Adder can also be implemented using 2 HALF ADDERS and one OR gate.

– Cascade two half adders

(Array method)

Full Adder (Array Method)

Lab 3 : Multiplier

Overview

2-bits x 2-bits Multiplier

Terms

2

X 3

--------------

6

Mutiplicand

Multiplier

Product

Multiplication in binary form?

1. Rewrite the multiplication in binary form.

2. Sketch the black box view.

3. The multiplier multiplies two __?__ bits numbers.

2-bits x 2-bits Multiplier Design

• Two techniques:

–Using the standard K-Map

–Using Arrays (cascaded approach)

Part A: Using the K-Map Technique

• Sketch the back box.• Sketch the Truth Table for a 2-bit “multiplier” and

2-bit “multiplicand”.– Input (Multiplier) = A1 and A0– Input (Multiplicand) = B1 and B0– Output (4-bits) = S3, S2, S1 and S0 or

S[3..0]• Using K-Maps, obtain the boolean expression for

each output.• Sketch the schematic diagram.

Lab 3 Requirement

• Simulate your design– Input A1 and A0 = counting sequence. – Input B1 and B0 = a fixed value.

• Study this waveform

LAb 3

• Transfer in Max+Plus II using the Graphic Editor.

• Verify your design.

• Submit : Truth Table, K-Maps, Boolean Expressions, Printed: Schematic and Waveform results

Part B: Using the Array (Cascaded) Technique

• Create the 2x2 multiplier using Full ADDERS.

… tHE cONcEpt

A1 A0B1 B0x

A1B0 A0B0A1B1 A0B1+

S0S1S2S3

CC

A 2-Bit by 2-Bit Binary Multiplier

AND computes A0 B0

Half adder computes sum. Will need FA for larger multiplier.

In Lab 3 …

• Simulate your design

–Input A1 and A0 = counting sequence. –Input B1 and B0 = a fixed value.

… in LAb 3

• Transfer in Max+Plus II using the Graphic Editor.

• Verify your design.

• Submit : Truth Table, K-Maps, Boolean Expressions, Printed: Schematic and Waveform results

Part C: 4-bits x 4-bits Multiplier

Using Array 2x2

Basic Idea of a Larger Multiplier (4-bits by 3-bits)

Multiplier Product

• The product of m-bit x n-bit numbers is an (m+n)-bit number.

=> The product of two 4-bit numbers is an 8-bit number.

How about this one?

13

X 11

--------------

143

Mutiplicand

Multiplier

Product

1 1 0 1 (13) multiplicand

X 1 0 1 1 (11) multiplier

1 1 0 1

1 1 0 1

0 0 0 0

1 1 0 1

1 0 0 0 1 1 1 1 (143) Product

Partial products

A3 A2 A1 A0

B3 B2 B1 B0

A3B0 A2B0 A1B0 A0B0

A3B1 A2B1 A1B1 A0B1

A3B2 A2B2 A1B2 A0B2

A3B3 A2B3 A1B3 A0B3

S7 S6 S5 S4 S3 S2 S1 S0

From the previous slide:

1. The multiplier multiplies two __?__ bits numbers.

2. Sketch the black box view.

In Lab 3

• Design a 4-bits x 4-bits multiplier using the Array (cascaded) technique, by utilizing:

– The 2-bits x 2-bits Multiplier and full adder designed earlier.

• Hints : Look back at the concept of 2x2 multiplier. Take the same step.

… in LAb 3

• Transfer in Max+Plus II using the Graphic Editor.

• Verify your design.

• Submit (Printed) - Schematic, and Waveform results

4x4 Combinational Multiplier

Note use of parallel carry-outs to form higher order sums

12 Adders, if full adders, this is 6 gates each = 72 gates

16 gates form the partial products

total = 88 gates!

A 0 B 0 A 1 B 0 A 0 B 1 A 0 B 2 A 1 B 1 A 2 B 0 A 0 B 3 A 1 B 2 A 2 B 1 A 3 B 0 A 1 B 3 A 2 B 2 A 3 B 1 A 2 B 3 A 3 B 2 A 3 B 3

HA

S 0 S 1

HA

F A

F A

S 3

F A

F A

S 4

HA

F A

S 2

F A

F A

S 5

F A

S 6

HA

S 7

Array Multiplier

4 x 4 array of building blocks

1 building block

Extra Lab Activity

• Modify your design so that the output of your multiplier could be observed on two 7-segment displays on the UP2 board.

• Download your 4-bits x 4-bits multiplier design to the UP2 board.

Part C : 4 x 4 MultiplierExtra Activity

• Download your 4x4 multiplier to UP2 board using FPGA (Flex10K)

4x4 Multiplier

(your design)

Tenth & UnitSegmentDecoder

7447BCD to

7Seg

7447BCD to

7Seg a - g

a - g

A0A1A2A3

B0B1B2B3

Pin Configuration to input(use flex switch 1-8)

Pin Configuration to output(use flex digit 1 & 2 )

Max+PlusII Tips

• Bus line

A3A2A1A0

A[3..0]

~ GOOD UCK !!