ADC Thesis

DECIMATION FILTERING FOR COMPLEX SIGMA DELTA ANALOG TO DIGITAL CONVERSION IN A

LOW-IF RECEIVER

A Thesis Submitted for the Degree of

Master of Science (Engineering) In the Faculty of Engineering

By

Anjana Ghosh

Supercomputer Education and Research Centre Indian Institute of Science

Bangalore – 560012

October 2005

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To

Ma

who taught me how to live

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ACKNOWLEDGEMENTS

To my guides, Prof S K Nandy and Dr. V Srinivasan, my heartfelt gratitude. Prof Nandy,

thank you for your guidance right from the start of the MS curriculum till the end. I

would not have dreamt of the final chapters had it not been for your encouragement. To

V Srini, thank you for introducing me to the fascinating world of Receiver Systems.

Thank you for your valuable inputs and comments on the material. To both my guides,

thanks for not losing patience with me.

To my colleagues and managers at Texas Instruments, thank you for your cooperation.

You are a team I am proud of. Thanks for your support and the camaraderie. A special

thanks to Chandrashekhar B G for his commitment throughout the length of the project

where a section of this work was implemented. Hats off to you for the hard work that

resulted in an error free silicon.

Thanks to many of my close friends who helped keep my morale high throughout this

period. A special thanks to Tua, Mistuni, Rupa, Bipasha, Polly, Priya and Ravi for all

that you did for me. Thanks to my classmates, Murali, Kalpesh and Aparna for all the

fun we had during the course.

Thanks to my family for having stood behind me like a rock. To my parents-in-law,

thanks for your support and affection. To Ma and Baba, thank you for your constant

reassuring presence and for your confidence in me. To Didi, thanks for being my

saviour at times of stress. To Abhijit, thank you for being my tower of strength. Without

you folks, this thesis would not have materialised . And finally, thanks to little Diya who

came to our world halfway through my MS and transformed our home into an unending

source of joy. Thanks to her for being such a lovely child.

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Table of Contents

Acknowledgements ........................................................................................... 3

ABSTRACT ...................................................................................................11

1 INTRODUCTION........................................................................................12

1.1 Motivation...........................................................................................12

1.2 Thesis Outline and Contribution.................................................................13

2 Receiver Architectures .................................................................................15

2.1 Heterodyne Receiver: The IF Receiver ........................................................15

2.2 Homodyne Receivers: The Zero-IF Receiver .................................................18

2.3 Low IF Receivers ..................................................................................21

2.4 Summary ...........................................................................................23

3 Digital Decimation Filtering ............................................................................25

3.1 Decimation Structure for Low Pass ΣΔ A/D Converters .....................................28

3.1.1 Multistage Decimation.......................................................................32

3.1.2 Cascaded Comb Filters .....................................................................33

3.1.3 Order of the CIC Filter.......................................................................36

3.1.4 Low Power Implementation of COMB.....................................................37

3.1.5 Modified-Sinc Filters.........................................................................39

3.1.6 Later Stages of Decimation.................................................................42

3.2 Decimation structure for band pass Σ Δ modulator ..........................................44

3.3 Decimation for complex band pass ΣΔ modulator ............................................48

3.4 New Architecture : Motivation ...................................................................49

3.5 Summary ...........................................................................................50

4 Architecture For Complex NARRowband Filtering .................................................52

4.1 Frequency Spectrum Analysis of The Image Reject Receiver ..............................54

4.2 Digital Filtering .....................................................................................56

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4.2.1 Simplification of Computation ..............................................................60

4.3 Summary ...........................................................................................61

5 Decimation Filter Structure ............................................................................62

5.1 Frequency Plan ....................................................................................62

5.2 Digital Filter Partitioning ..........................................................................63

5.3 ADC NTF and STF ................................................................................64

5.4 Stage One Antialias Filter (AAF1)...............................................................65

5.4.1 Filter Specifications ..........................................................................66

5.4.2 Filter Transfer Function .....................................................................67

5.5 Stage Two Antialias Filter (AAF2)...............................................................69

5.5.1 Filter Specifications ..........................................................................69


5.6 Image Reject Filter (Complex Filter) ............................................................71

5.6.1 Filter Specification ...........................................................................74


5.7 Summary ...........................................................................................78

6 Droop Correction Filter and Implementation ........................................................79

6.1 Droop Correction Filter ...........................................................................79

6.1.1 Filter specifications ..........................................................................79


6.2 Data Quantization .................................................................................82

6.3 Hardware Considerations ........................................................................85

6.4 Silicon Results .....................................................................................86

6.5 Summary ...........................................................................................86

7 OptimiZed Architecture.................................................................................88

7.1 Complex Bandpass Antialias Filtering..........................................................88

7.2 Alternate Filter Architectures.....................................................................90

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7.3 Alternate Architecture I ...........................................................................91

7.3.1 Complex Decimation Filter Structure......................................................91

7.3.2 Image Reject Filtering .....................................................................100

7.3.3 Droop Correction Filtering ................................................................102

7.3.4 Implementation .............................................................................104

7.4 Alternate Architecture II ........................................................................106

7.4.1 Implementation .............................................................................111

7.4.2 Comparison Of The Three Architectures ...............................................112

7.5 Comparison With Prevalent Architectures ...................................................116

7.6 Summary .........................................................................................117

8 Conclusion .............................................................................................118

8.1 Scope of Future Work ..........................................................................119

References ..................................................................................................120

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Table of Figures

Figure 2-1 IF Downconverter (a) IF Receiver Topology (b) IF Down-conversion in Frequency Domain ...................................................................................................17

Figure 2-2 Dual IF Receiver ................................................................................18

Figure 2-3 Zero-IF Downconversion Scheme in Frequency Domain .................................19

Figure 2-4 Zero-IF Receiver Topology ....................................................................19

Figure 2-5 Effect of I/Q Mismatch in A Zero-IF Receiver ...............................................20

Figure 2-6 Low IF Downconversion Scheme in the Frequency Domain..............................21

Figure 2-7 Low IF Downconversion in Presence of I/Q Mismatch ....................................22

Figure 2-8 Low-IF Receiver Using Complex ΣΔ ADC ...................................................23

Figure 3-1 Transfer Function of (a) Analog Antialias Filter in Nyquist Rate ADC (b) Analog Antialias Filter(AAF) and Decimation Filter in Oversampled ADC ..........................................25

Figure 3-2 PSD of Quantization Noise in a (a) Nyquist Rate Converter (b) Oversampled Converter (c) Oversampled ΣΔ Converter .......................................................................26

Figure 3-3 (a) First Order ΣΔ Modulator (b) Second Order ΣΔ Modulator (c) z-Domain Block Diagram for a Second Order ΣΔ Modulator .........................................................30

Figure 3-4 Noise Transfer Function in First ,Second and Third order Lowpass ΣΔ Modulator ( Sampling Frequency=256MHz ) ....................................................................31

Figure 3-5 Magnitude Responses of Cascaded Comb Filters .........................................35

Figure 3-6 (a) Cascade of Two Comb Filters (b) Separation of Denominator and Numerator Sections (c) Commutation of sampling Switch and Numerator Section (d) Implementation .36

Figure 3-7 (a) Comb Filter (b) IIR-FIR implementation (c) FIR2: a cascade of FIR filters each decimating by 2 (d) POLY-FIR2: Polyphase decomposition applied to FIR2 ..................38

Figure 3-8 Efficient Polyphase Decomposition of Comb Filter.........................................39

Figure 3-9 Zero Pole Distribution of (a) M1=4 CIC (b) Angle Rotation of Zeros (c) Rotated Sinc Filter............................................................................................................40

Figure 3-10 Attenuation In a Third Order Sinc and A Modified Sinc filter(M1=4)....................41

Figure 3-11 Recursive Implementation of the Modified Sinc ...........................................42

Figure 3-12 Transfer Function of 11 Tap Halfband......................................................43

Figure 3-13 Noise Transfer Function (NTF) and Signal Transfer Function (STF) in (a) Lowpass ΣΔ Modulators(b) Bandpass ΣΔ Modulators (b) Complex Bandpass ΣΔ Modulators..............45

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Figure 3-14 Complex Downconversion (a) Signal Before Downconversion (b) Complex Sinusoidal (c) Signal After Downconversion (d) System block Diagram of Downconverter Followed by Complex LPF ............................................................................................46

Figure 3-15 (a) Downconverter and Filter Split into Real and Imaginary Parts (b) Simplified Complex Modulator and Low pass Filter ............................................................47

Figure 3-16 Complex Demodulation of the Quadrature Modulator’s Output Stream ...............49

Figure 4-1 Architecture of A Low IF Receiver Using Complex ΣΔ Analog to Digital Converter ...53

Figure 4-2 Signal Spectrum of (a) Incoming RF Signal (b) cosωct (c) sinωct (d) in-phase o/p of Mixer (e)Out-of-phase o/p of mixer (f) Out-of-phase component multiplied by j (g) Signal and Image Separated (h) Signal and Image separated .........................................................57

Figure 4-3 (a)Complex Sum of Mixer Outputs, STF and NTF of ADC (b) Complex Difference of Mixer Outputs, STF and NTF of ADC(c) Complex Sum of ADC Outputs(d) Complex Difference of ADC Outputs .........................................................................................58

Figure 4-4 (a)Complex Digital Filtering on X+jY (b)Complex Digital Filtering on X-jY (c) Real Two sided Bandpass Signal Obtained After Digital Decimation Filtering .............................59

Figure 4-5 Complex Digital Filtering on Output of Complex ΣΔ ADC .................................59

Figure 4-6 Transfer Functions of DF1 and Df2...........................................................60

Figure 4-7 Complex Digital Filter Structure ...............................................................61

Figure 5-1 Multistage Decimation Filter Structure .......................................................64

Figure 5-2 FFT Of ADC Output For A Single Tone Input ...............................................64

Figure 5-3 Transfer Function of Fourth Order Comb ....................................................67

Figure 5-4 Passband Ripple of Fourth Order Comb.....................................................68

Figure 5-5 Stopband Attenuation of Fourth Order Comb ...............................................68

Figure 5-6 Transfer Function of Halfband Filter..........................................................70

Figure 5-7 Passband Ripple of Halfband Filter ..........................................................70

Figure 5-8 Stopband Attenuation in Halfband Filter .....................................................71

Figure 5-9 Transfer Functions Of DF1 And DF2 .........................................................72

Figure 5-10 Transfer Function of Four Tap Comb and Shifted Comb ................................73

Figure 5-11 Derivation of The Image Reject Filter From A Comb .....................................74

Figure 5-12 Effect of Coefficient Quantization On The Stopband Attenuation of Image Reject Filter............................................................................................................75

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Figure 5-13 Passband Droop Of Image Reject Filter....................................................76

Figure 5-14 Phase Response of Image Reject Filter....................................................76

Figure 5-15 Transfer Function of DF1 and DF2..........................................................78

Figure 6-1 Transfer Function of Droop Correction FIR..................................................80

Figure 6-2 Droop Correction ................................................................................81

Figure 6-3 Final Transfer Function : DF2 path for filtering X-jY........................................81

Figure 6-4 Final Transfer Function : DF1 path for filtering X+jY .......................................82

Figure 6-5 Direct Form Implementation of FIR...........................................................83

Figure 6-6 PSD Of Uncorrelated White Quantization Noise ...........................................84

Figure 6-7 FFT of ADC Output ...........................................................................85

Figure 6-8 FFT of Silicon Data At The Output Of Digital Filters and ADC ......................86

Figure 7-1 Cascaded Complex Digital Filter Structure ..................................................90

Figure 7-2 Shifted Comb Structure For Downsampling by 16 .........................................93

Figure 7-3 Shifted Comb : Stage 1 ........................................................................94

Figure 7-4 Stopband Attenuation in Shifted Comb ......................................................94

Figure 7-5 Shifted Comb :Stage 2 .........................................................................95

Figure 7-6 Stopband Attenuation in Stage 2 .............................................................95

Figure 7-7 Shifted Comb Stage 3 ..........................................................................96

Figure 7-8 Stopband Attenuation in Stage 3 .............................................................96

Figure 7-9 Transfer Function of Shifted Comb ...........................................................97

Figure 7-10 Passband Ripple in Shifted Comb ..........................................................97

Figure 7-11 Phase Response of Stage 1 .................................................................99

Figure 7-12 Phase Response of Stage 2 .................................................................99

Figure 7-13 Phase Response of Stage 3 ...............................................................100

Figure 7-14 Transfer Function of Image Reject Filter .................................................101

Figure 7-15 Phase Response of Image Reject Filter..................................................101

Figure 7-16 Alternate Architecture I .....................................................................102

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Figure 7-17 Comparison of Transfer Function : Original Architecture and Architecture I ........103

Figure 7-18 Comparison of Passband Ripple : Original Architecture and Architecture I.........103

Figure 7-19 Comparison of Image Rejection : Original Architecture and Architecture I..........104

Figure 7-20 Alternate Filter Architecture II ..............................................................107

Figure 7-21 Transfer Functions of Decimation Filter Stages in Architecture II ....................108

Figure 7-22 Decimation Filter Stages in Architecture II :Signal and Image Band .................109

Figure 7-23 Anti-alias Filtering in Architecture II .......................................................109

Figure 7-24 Comparison of Transfer Function : Original Architecture and Architecture II .......110

Figure 7-25 Comparison of Passband Ripple : Original Architecture and Architecture II ........110

Figure 7-26 Comparison of Image Reject Filtering : Original Architecture and Architecture II ..111

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ABSTRACT

The low-IF receiver using complex bandpass ΣΔ modulator is one of the architectures

being explored in recent times for use in single chip implementation of wireless

receivers. This work focuses on the decimation digital filters that are needed at the

output of the such modulators.

Decimation filtering for lowpass ΣΔ modulators is a well researched subject. A typical

decimation filter stage in the lowpass case consists of a comb filter followed by one or

two stages of FIR filters. Not much literature exists in the field of decimation filtering for

bandpass and complex bandpass modulators. The accepted approach involves

translating the signal from IF to DC by performing a complex mixing operation on the

ΣΔ bit stream and performing decimation using structures similar to standard lowpass

decimation filter architectures.

This work aims at investigating an approach where decimation filtering is done at IF.

This implies that instead of lowpass filtering, complex bandpass filtering is required in

the decimation stage. As a result, standard lowpass decimation structures cannot be

directly used in this system.

Building on prevalent decimation filter theories and practices, a new architecture is

proposed for complex bandpass decimation filters. This architecture has been

successfully implemented in a single chip receiver. The architecture is further optimized

and variations to the main structure are proposed in the later sections of the thesis. A

few areas for future scope of work in the same field are proposed in the end.

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1 INTRODUCTION

1.1 Motivation

Recent years have seen considerable research effort towards the realization of

monolithic RF transceivers. The trend is implementation of small, inexpensive, low

power communication devices that are robust, testable and capable of handling

multiple communication standards. This has heralded the way for single chip solutions

with new architectures where an analog to digital converter is placed as close to the

antenna as possible. Significant amount of digital signal processing following the ADC

performs the functionalities previously achieved with analog circuitry. The low IF

receiver is one such architecture that is gaining popularity.

Published literature discuss the use of over sampled bandpass ΣΔ analog to digital

converters in low IF receivers. More recent work [6],[7],[8] discuss the use of complex

ΣΔ modulators citing advantages in terms of robustness, over the bandpass. This is

especially suited to an image reject receiver.

The ΣΔ modulator is followed by decimation digital filtering. The presence of digital

filtering following the modulator provides a scope for doing precise image rejection and

filtering. This helps in having relaxed specifications for the analog blocks preceding the

modulator.

Decimation filtering for bandpass ΣΔ modulators has been explored in literature [5].

The accepted approach is to do a complex mix on the ΣΔ bit stream, thus down

converting the signal in frequency domain from IF to DC, followed by low pass filtering .

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In real valued band pass ΣΔ modulators, the output is a single bit stream. Complex ΣΔ

modulators, on the other hand, produce two bit streams: real and imaginary. In this

case, complex mixing is performed on the complex output of the ΣΔ modulator and low

pass decimation filtering is done after that [8].

In the above approaches, the decimation filtering is performed after frequency

translating the ΣΔ output from low IF to dc. A good choice of the sampling frequency

accommodates an optimized implementation of the down conversion mixer. However,

a fixed choice of down conversion frequency with respect to the sampling rate poses

certain restrictions on the overall system design.

This work investigates an approach where decimation filtering is done at IF.

Downconversion to baseband should be performed on the decimated signal. Here,

instead of low pass filtering, complex band pass filtering is performed. The complex

filters perform decimation and image rejection and transforms the complex signal to a

real signal. The output of the decimation filter chain is a real signal free of the

quantization noise and out of band signal components.

1.2 Thesis Outline and Contribution

The first three chapters discuss the prevalent art on the subject of receiver

architectures, ∑∆ modulators and decimation digital filtering. Chapters 4, 5 and 7

discuss the proposed architectures for complex narrowband digital filtering for complex

∑∆ converters and as such constitute the contribution by this author. Chapter 6

discusses mostly the implementation details, the actual work for which was shared

between the author and a colleague of hers.

This thesis has been organized as follows:

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1 gives an introduction to the subject.

2 gives an overview of different receiver architectures available in literature.

In 3, decimation digital filtering for ΣΔ converters is discussed. Published literature on

digital filter structures for lowpass, bandpass and complex bandpass ΣΔ converters is

explained.

In 4, a new architecture for performing complex narrowband digital filtering is proposed.

First, the frequency spectrum of the image reject receiver is analyzed. Next, the

proposed complex image reject filter architecture is discussed.

In 5 , the decimation filter and image reject filter designs are discussed in detail.

In 6, the droop correction filter is explained and implementation details for the whole

filter block are explained. A large part of the work described in this chapter has been

contributed by my colleague, Chandrashekar B G, at Texas Instruments. This chapter

has been included for the purpose of completion of the description and analysis of the

filters.

In 7, the architecture is analyzed for scope of optimization. Two new architectures are

proposed. A comparative analysis of the three architectures is given at the end of this

chapter

The list of publications that were used as reference for this work is given at the end of

the thesis.

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2 RECEIVER ARCHITECTURES

A telecommunication receiver typically consists of two sections – a front end for

downconversion and a backend for demodulation. The front end receives the signal

from the antenna, filters it from interfering signals and translates it from the high

frequency to low frequency. The front end needs very high performance circuits and

has been traditionally built with analog circuit design techniques. The backend

processes the frequency down converted signal applying demodulation algorithms and

extracts the transmitted information. In most applications of Today, the demodulation

section involves the use of a digital signal processor (DSP). In this thesis, the design of

a section of the front end of the receiver is addressed.

2.1 Heterodyne Receiver: The IF Receiver

The heterodyne receiver, also known as the IF receiver, has been in use for a long time.

In this receiver, the incoming RF signal is multiplied by a sinusoid, generated by a local

oscillator, of a frequency close to but not equal to the frequency band of the RF signal.

This results in the RF signal being translated to an IF (intermediate frequency). The

main disadvantage of this scheme is that during the process of multiplication, along

with the wanted signal, some unwanted signals, called the image signals, get

downconverted to the same IF.

Figure 2-1(b) shows the IF downconversion scheme in the frequency domain. Let the

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desired RF signal be assumed to be present in a band ωc+ωif. Let the sinusoid used in

the mixer for downconversion have a frequency ωc. After multiplication of the incoming

signal with the sinusoid (ωc), the RF signal gets translated to the intermediate

frequency ωif. Now, during the process of multiplication, any signal present in the band

ωc - ωif, also gets translated to the IF. This signal is called the image signal. The image

signal is an interfering signal and is unrelated to the signal of interest. Hence, to

prevent corruption of the RF signal, a prefiltering of the signal needs to be performed

before the mixing operation. This filter is a pre-select filter. The amount of filtering

achieved determines how much of the image signal gets into the IF band. This can be

seen in Figure 2-1(b), where a small part of the image band is seen to be present even

after filtering.

Figure 2-1(a) shows the block diagram of such a receiver. Here the incoming RF signal

received by the antenna is sent through an LNA (low noise amplifier) which amplifies

the received signal. A pre-select filter (HF) present after the LNA, removes signals

present in RF bands adjacent to the signal band of interest. The output of the pre-select

filter is sent to the mixer. The mixer multiplies the incoming signal with the sinusoid

provided by a local oscillator. The mixer output contains signals at two frequency

bands: one at the IF (ωif) and another at a high frequency (2ωc+ωif). A lowpass filter,

present after the mixer, filters the high frequency component. An analog to digital

converter transforms the resulting signal from the analog to the digital domain and

sends it to the demodulation section of the receiver.

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ωc -ωc 0 ω -ω

desired signalimage

signal

Pre-select Filter

ωc + ωif

ωc - ωif

-ωc -ωif

-ωc +

ωif

0 -ωif ωif

Pre-select

Filter

cosωct

LNA Low Pass Filter

A/D to Demodulator

(a)

LO Signal

(b)

Figure 2-1 IF Downconverter (a) IF Receiver Topology (b) IF

Down-conversion in Frequency Domain

The high frequency (HF) filter poses a challenge in terms of integration. The HF can be

realized only if the IF is high enough so that the wanted signal is relatively far away

from the image frequency. Even when the ratio (ωc+ωif)/ωif is as small as 10, the

specifications of the HF are very severe. The HF must have a very high Q (up to 50 and

more) and it must have an order which is high enough; and in some cases, the center

frequency must be tunable. A filter with such specifications cannot be integrated on a

single die of silicon. These filters are realized with discrete components consisting of

capacitors and inductors. These HF filters are expensive and vulnerable [10].

Once the signal is downconverted to IF, the signal needs to be further filtered so as to

separate the desired signal from its neighbors. These filters, too, must have a high Q

and are difficult to integrate on silicon. While, a high IF implies relaxed specifications

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for the HF prefilter, it makes the specifications for the IF filters tight because the

corner frequency of the IF filter increases with increasing IF. On the other hand, a low

IF implies relaxed spec for the IF filters but imposes strict conditions on the design of

the HF prefilter. A high IF also implies that the ADC needs to work at a higher

frequency.

In order to strike a balance in the choice of the IF, some receivers use the dual-IF

scheme. Such a receiver contains two sections, each section consisting of an image

reject filter, mixer and low pass filter. The dual IF receiver trades off the design of the

filters in exchange for increased circuit complexity.

image reject filter

cosωLO1t

LNA Channel Select Filter1

Band select filter

cosωLO2t

Channel Select Filter2

IFamp

Figure 2-2 Dual IF Receiver

2.2 Homodyne Receivers: The Zero-IF

Receiver

The homodyne receiver does not use an IF. Such a receiver is also called the zero-IF

receiver or the direct conversion receiver. Here the signal is directly down converted to

dc. Figure 2-3 shows the zero-IF downconversion scheme in frequency domain. Here,

the incoming RF signal is multiplied with a one sided LO signal of a frequency equal to

the centre frequency of the desired signal band. This translates the desired signal to DC.

This technique does not have any problem of interference from image signals.

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-ωc 0 ω -ω

desired signal

0 ω -ω

ωc

LO Signal

Figure 2-3 Zero-IF Downconversion Scheme in Frequency Domain

The topology for such a receiver is shown in Figure 2-4. The downconversion with a one

sided LO signal is achieved by sending the incoming signal through a quadrature mixer;

i.e. the incoming signal is multiplied with two LO signals (a sine and a cosine) having a

phase difference of 90 degrees between themselves. The outputs from the two mixers

are sent through two branches – the in-phase or the I component and the quadrature

phase or the Q component. These two components are lowpass filtered and sent to two

Analog to Digital Converters. The I and the Q outputs from the ADCs are sent to the

demodulation block. A complex summation of the I and Q components yields the

desired signal. This is done inside the demodulator.

cosωct

sinωct

LNA

ADC Lowpass Filter

ADC Lowpass Filter

I DSP Q

Demodulation

Figure 2-4 Zero-IF Receiver Topology

The zero-IF receiver is one of the architectures that is being considered suitable for

single chip realization of receivers. High Q tunable bandpass filters are not required in

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this scheme. The low pass filters can be implemented as analog integrated filters.

The zero-IF receiver poses design challenge in three areas. First, any mismatch in the

I and the Q paths manifests itself in leakage of signal from the mirror frequency; i.e. if

the desired signal is present at ωc and the one-sided LO signal used for downconversion

is present at –ωc, then a mismatch in the I and Q paths will lead to signal present at –ωc

(mirror frequency) being downconverted to DC. This is shown in Figure 2-5. The

appearance of a small impulse at ωc in addition to the actual impulse at –ωc is the result

of I/Q mismatch. This results in a section of the signal at –ωc to superimpose on the

desired signal at DC.

-ωc 0 ω -ω

desired signal

0 ω -ω

ωc

LO Signal due to I/Q Mismatch mirror signal

Figure 2-5 Effect of I/Q Mismatch in A Zero-IF Receiver

The second challenge faced by the zero-IF receiver is that resulting from coupling

between the RF and LO inputs to the mixer. The coupling results in the LO signal getting

multiplied with itself and gives a DC signal. This DC-offset gets superimposed on the

desired signal in the baseband. The coupling at the mixer inputs also results in the RF

signal getting multiplied with it.

A third problem in the zero IF receiver is flicker noise. This is a noise generated in

analog circuits which is present in the low frequency band. This low frequency noise,

also called the 1/f noise due to its PSD being inversely proportional to frequency, gets

superimposed with the desired signal.

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2.3 Low IF Receivers

The low-IF receiver combines the advantage of both the heterodyne and homodyne

receivers. Here, the RF signal is passed through a quadrature mixer, similar to the

zero-IF receiver. However, the signal is not downconverted to DC but to a frequency

band close to DC. This is called the low-IF band. The quadrature mixing makes the high

Q HF filters redundant. At the same time, the problems of DC offset and flicker noise of

the zero-IF receiver does not arise in the low-IF case. This makes the low-IF receiver

another good candidate for monolithic implementation of receivers.

Figure 2-6 shows the downconversion in a Low-IF receiver. Here, the incoming signal

(present at ωc+ ωif) is multiplied with a one-sided LO signal (at -ωc). This results in the

desired signal getting translated to ωif and the image signal being translated to -ωif. A

complex filter having passband at ωif and stopband at -ωif can now be used to extract the

desired signal.

LO Signal

ωc -ωc DCω-ω

desired signal

image signal

ωc + ωif ωc - ωif-ωc -ωif

-ωc + ωif

ωif-ωif DC

ω-ω

Figure 2-6 Low IF Downconversion Scheme in the Frequency Domain

The low-IF receiver suffers in presence of non-ideality in the quadrature oscillator in a

similar manner as the zero-IF receiver. If the two output paths of the oscillator have

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mismatch, then the signal leaks to positive frequencies, thereby mixing some of the

image input into the signal band. Figure 2-7 shows the receiver spectrum in presence

of mismatch in the two phases of the local oscillator. Here, the complex sum of the

quadrature LO mixer outputs have impulse functions at both ωc and -ωc; the one at ωc

being due to non-ideality in the phase relationships between the sine and the cosine

outputs of the local oscillator. The convolution of the two impulse functions with the

input spectrum yields a superimposition of the image signal component with the

desired signal at ωif. The avoidance, estimation and correction of I/Q mismatch is an

active area of research. Several methods used to minimize the image interference

include digital signal processing algorithms for estimation and correction of the errors

due to mismatch and strategic choice of IF so as to place the interfering signals outside

the image frequency range.

LO Signal

ωc -ωc DCω-ω

desired signal

image signal


-ωc + ωif

ωif-ωif DC

ω-ω

Due to I/Q mismatch

Figure 2-7 Low IF Downconversion in Presence of I/Q Mismatch

The topology of the low-IF receiver is similar to that of the zero-IF receiver. A

quadrature mixer performs the job of mixing the incoming signal with a one-sided local

oscillator signal. The mixer outputs are filtered and sent to the analog to digital

converter. The ADC is designed such that its signal transfer function exhibits bandpass

23

properties. A bandpass ΣΔ converter is used in [5] while a complex bandpass ΣΔ

converter is used in [6] [7].

cosωct

sinωct

LNA

Lowpass Filter

Complex Bandpass

ΣΔ Converter

Lowpass Filter

Deci-

mation Filter

I

Q

To Demodulator

Figure 2-8 Low-IF Receiver Using Complex ΣΔ ADC

Figure 2-8 shows the block diagram of a low-IF receiver using complex ΣΔ converter.

The output of the ADC is sent to a decimation filter section. The latter performs antialias

filtering and reduces the sample rate. Since, the local oscillator signal needs to be

one-sided, the system performs complex computations. The decimation filter,

therefore, is complex. The design of the decimation filter for complex ΣΔ converters is

an active area of research [21]. This thesis focuses on the design of these filters.

2.4 Summary

This chapter gives an overview of different receiver architectures. The principles of

operation of the IF receiver, zero-IF receiver and the low-IF receiver are explained in

brief. The advantages and disadvantages of each in terms of integration are discussed.

The zero-IF and the low-IF receiver are the architectures under discussion for single

chip implementation of a receiver. The low-IF receiver using complex bandpass

24

ΣΔ converter is the architecture used in the receiver discussed in the thesis. The focus

area is the decimation digital filter section following the complex ΣΔ converter. This is

discussed in detail in the rest of the thesis.

25

3 DIGITAL DECIMATION FILTERING

An oversampled ADC works at a sample rate higher than the Nyquist sample rate. If the

signal of interest lies in the bandwidth, DC to ±fib (pass band edge), then the Nyquist

sample rate fN is very close to fib (fN > 2* fib). The sampling rate, fos, of an oversampled

ADC is much higher than fib ( fos>> fN). The analog antialias filter preceding an

oversampled ADC need only provide attenuation till (fN-fib) close to the sampling

frequency of the ADC. Consequently the analog filter can have a much gentler cutoff

characteristic than the filter preceding a Nyquist rate converter. However, in the

oversampled case, a digital decimation filter is required after the ADC to attenuate the

signal and noise components falling outside the signal band before reducing the sample

rate to the Nyquist rate. Figure 3-1 shows the transfer function of the analog antialias

filter (AAF) in the two cases. The transfer function of the decimation filter for the second

case is also shown.

fN/2 -fN/2

fN/2 -fN/2 fOS/2 -fOS/2

(a)

(b)

Decimation Filter

Analog AAF

Figure 3-1 Transfer Function of (a) Analog Antialias Filter in Nyquist Rate

ADC (b) Analog Antialias Filter(AAF) and Decimation Filter in Oversampled

ADC

26

Effectively in oversampled converters, the steep analog filter preceding a Nyquist rate

converter is replaced by a much simpler analog filter and a digital decimation filter. As

a result, most of the antialias filtering operation is transferred from the analog to the

digital domain, where it may be performed accurately with a steep cutoff characteristic

and without phase distortion or deterioration resulting from component variation. An

added benefit provided by the decimation filter is the attenuation of out-of-band circuit

noise generated in the ADC. This noise may be generated by electronic devices within

the modulator, or may enter the modulator through the power supplies or substrate

coupling from digital circuits [3].

fN/2 -fN/2

fos/2 -fos/2

fos/2 -fos/2

(a)

(b)

(c)

0

0

0

Figure 3-2 PSD of Quantization Noise in a (a) Nyquist Rate Converter (b)

Oversampled Converter (c) Oversampled ΣΔ Converter

Assuming that the quantization noise is white and uniformly distributed across the

quantization interval Δ, the total noise in an ADC is Δ2/12. This noise is uniformly

27

distributed from -fN/2 to fN/2, where fN is the Nyquist frequency. This is shown in Figure

3-2(a). In an oversampled ADC which works at a frequency fos, the total noise gets

uniformly distributed over the frequency range, -fos/2 to fos/2. This is shown in Figure

3-2(b). The total noise (Δ2/12) is the same in both the ADCs, the noise being a function

of the number of quantization intervals in the ADC. But the PSD of the noise at

individual frequencies is less in the oversampled case, compared to the Nyquist rate

converter. Thus, in an oversampled converter, the high sample rate yields low

quantization noise at the cost of increased circuit complexity. Figure 3-2(c) shows the

noise characteristics for a lowpass oversampled ΣΔ modulator. In this modulator, the

distribution of the noise is not uniform over the entire frequency range. Here, the noise

is low in the low frequency band, but increases in higher frequencies. Thus the signal to

noise ratio is very high in the low frequency signal range. This allows the use of a low

resolution quantizer; significantly lower than that which would be required for an ADC

with flat quantization noise for the same signal to noise ratio requirement. Hence, in

spite of it being an oversampled system, the use of a low resolution quantizer reduces

the circuit complexity. Usually a single bit or dual bit quantizer is sufficient for providing

high resolution ADCs employing ΣΔ modulation. It is this fact that allows the use of the

ΣΔ modulator in high speed applications.

The output of the ΣΔ modulator represents the input signal together with its

out-of-band components, quantization noise, analog circuit noise and interference

components. The modulator is followed by a decimation filter stage. The two principal

functions of a decimation filter are the attenuation of quantization noise outside the

signal band and band limiting the modulator input.

28

3.1 Decimation Structure for Low Pass ΣΔ A/D

Converters

This section describes lowpass ΣΔ modulator [3]. This is explained in this section.

Figure 3-3(a) shows a first order lowpass ΣΔ modulator. The integrator accumulates the

difference between the modulator input and the quantizer output. When the

accumulated difference is greater than or equal to zero, the quantizer feeds back a

positive pulse that is subtracted from the input to move the integrator output in the

negative direction. When the accumulated difference is less than zero, the quantizer

feeds back a negative pulse to move the integrator output in the positive direction.

Thus, the modulator attempts to keep the integrator output near zero and minimizes

the accumulated difference between the modulator input and the quantizer output. The

quantization error is defined as the difference between the output and input of the

quantizer,

e(kT) = q(kT) – u(kT);

where e(kT) is the quantizer error, u(kT) is the integrator output and q(kT) is the

quantizer output at time kT and T is the sample time interval.

The output of the quantizer is given by,

q(kT) = u(kT ) + e(kT) ;

i.e. q(kT) = x(kT –T) -q(KT-T) + u(KT-T) + e(kT) ;

i.e. q(kT) = x(kT –T) + e(kT) –e(kT-T);

where x(kT-T) is the analog input signal at time (kT-T).

29

Thus, the quantizer output consists of the modulator input, delayed by one sample

period, plus the first order difference of the quantizer error.

Figure 3-3(b) shows a second order modulator. The output of this modulator is given by

the equation,

Y(kT)=x(kT-T) + e(kT) –2e(kT-T)+e(kT-2T)

The noise generated by a scalar quantizer with quantization levels equally spaced by Δ

is uncorrelated and is uniformly distributed between -Δ/2 and Δ/2 with power Sq=Δ2/12,

provided that the number of levels is large and the quantized signal is active.

This uniformly distributed white noise approximation of the quantizer error is not

correct in ΣΔ modulators because of their extremely coarse quantization, the

correlation between the modulator input and the quantization noise and the presence

of discrete components in the probability density function of the quantizer input. The

model is particularly poor for first order ΣΔ modulators though it is useful for the design

of higher order modulators.

30

Integrator

Quantizer

Integrator

Quantizer

Integrator

DELAY 1 BIT

ADC

1 BIT DAC

-

+x(kT) y(kT)

111

−− z

1 BIT DAC

-

+X(z) Y(z)

E(z)

(a)

(c)

q(kT)

u(kT)

DELAY 1 BIT ADC

1 BIT DAC

-

+x(kT)

(b)

q(kT)

u(kT) DELAY

-

+

-

+1

1

1 −

−

− zz

y(kT)

Figure 3-3 (a) First Order ΣΔ Modulator (b) Second Order ΣΔ Modulator (c)

z-Domain Block Diagram for a Second Order ΣΔ Modulator

Under the limitations of the white noise model, the second order ΣΔ modulator of Figure

3-3(b) can be approximated by a linear system shown in Figure 3-3(c). The quantizer

is modeled as an additive error source, E(z), while the integrators are represented by

their transfer functions in the z-domain. The one bit DAC is assumed not to introduce

any error so that Q(z)=Y(z). The z-transform of the modulator output is

Y(z)= z-1X(z) +(1- z-1)2E(z) , where X(z) is the z-transform of the modulator

input.

The factor (1-z-1)2 has a high pass characteristic and is known as the noise transfer

function of the modulator.

31

Figure 3-4 Noise Transfer Function in First ,Second and Third order Lowpass

ΣΔ Modulator ( Sampling Frequency=256MHz )

In general, L-th order noise shaping can be achieved by means of L integrators in the

forward path of a ΣΔ modulator. In this case , the noise shaping becomes

HE(z)= (1- z-1)L

In the frequency domain, the magnitude of the noise shaping function is

( )( )[ ]( )( )L

L

LftjftjfTj

zEE

fT

fT

eeezHfH

π

π

πππ

sin2

2cos22

11)()(

2

22222

=

−=

−−== −

=

32

The magnitude of the noise transfer function vs frequency for first, second and third

order modulator is shown in Figure 3-4. The quantization noise in the low frequency

band is attenuated by the high pass characteristics of the noise transfer function.

Higher the order of the modulator, higher is the attenuation of the noise in the

baseband. This allows greater resolution to be achieved at the same oversampling ratio.

The quantization noise outside the baseband needs to be removed by a digital lowpass

filter so that the output of the filter can be resampled at the Nyquist rate, fN=2fB,

without aliasing. This is what comprises the decimation filter block.

3.1.1 Multistage Decimation

A popular approach in the design of the digital decimation filter stage for low pass ΣΔ

A/D converters is based on multistage structure [1]. In a typical application using

oversampled A/D converters, the signal band is only 1/128 to 1/512 of the modulator

sampling frequency. For example, in our receiver, the desired signal is present between

3MHz and 5 MHz while the ADC works at about 256Mhz; thus the signal band is only

1/128 of the modulator sample rate. For a specified passband ripple and stopband

attenuation, the number of coefficients in a filter is proportional to the filter’s input rate

divided by the width of the transition band, fs/ft [23]. This ratio may be quite large in a

narrowband filter such as the decimation filter for an oversampled A/D converter. As a

result the filter may require too many computations. By implementing a cascade of

several stages, the ratio fs/ft may be reduced for each of the individual stages, resulting

in a significant reduction in overall hardware complexity. A typical decimation filter

chain for a lowpass ΣΔ modulator will consist of a COMB, a Halfband and an FIR [3].

33

3.1.2 Cascaded Comb Filters

An efficient first stage anti aliasing decimation filter is a cascade of comb filter [2]. A

comb filter computes a running average of its last M1 input samples.

∑ −=−

=

11

011 )()(

M

iM inxny

...( 3.1.2.1)

The corresponding z transform is

))1()1(1()(1 1

1

1−

−

−−

=z

zM

zHM

…( 3.1.2.2)

Evaluating H1(z) on the unit circle in the z-plane gives the frequency response,

)1(.sin

sin)(1 11

11

11 −−= MfTjetTMTfM

fH ππ

π

… (3.1.2.3)

where T1=1/fs1 is the input sampling period. Note that the phase response of a comb

filter is linear.

The magnitude response has zeroes at integer multiples of the resampling frequency,

fs1/M1 . It is the noise present at the frequencies centered on these zeroes that get

aliased to the baseband when the comb filter output is resampled at fs1/M1 . The noise

in other frequency bands is aliased outside the baseband and is expected to be

removed by subsequent stages of the decimation filter.

Comb filters are efficient as they provide attenuation only in frequencies where it is

needed. Several comb filters can be cascaded to form higher order combs, in order to

34

provide better attenuation over wider frequency range around the zeroes. The

magnitude response for cascaded combs is given by equation 3.1.2.4, where k is the

number of filters in cascade.

k

fTMTfMfH ⎟

⎠⎞

⎜⎝⎛=

11

11

sinsin)(1 π

π

… (3.1.2.4)

Figure 3-5 shows the frequency response of a first, second and third order comb for

M=4, and a sampling rate of 256MHz. The zeros are located at multiples of

256MHz/4 ;i.e. at 64MHz, 128MHz and 192MHz. As is seen in the figure, the stopband

width, centered on the zeros, increases with increasing order, k, of the filter. The

passband droop also increases as k increases.

35

Figure 3-5 Magnitude Responses of Cascaded Comb Filters

Cascaded comb filters can be implemented efficiently without multipliers or coefficient

storage [2]. The comb transfer function is first separated into its numerator and

denominator terms. The denominator section forms an integrator i.e. an accumulator.

The numerator forms a differentiator; it calculates the difference between the current

sample and the sample obtained M sample points ago. A resampling switch is placed

between the integrator and the differentiator. Thus the term, z-M , gets replaced by z-1.

Hence, the differentiator can work at a lower sample rate. This structure can be

implemented using registers, adders and sub tractors. Figure 3-6 shows the structure

for a second order comb.

36

REG REG

REG-

REG -

fs1/M1i/p o/p

1 1-z-1

1 1-z-1

1-z-M1 1-z-M

1 1 M1

2

fs1/M1

1 1-z-1

1 1-z-1

1-z-1 1-z-1 1 M1

2

fs1/M1

(b)

(c)

(d)

1-z-M1

M1 (1-z-1) 1-z-M

1 M1 (1-z-1)

fs1/M1

(a)

1 M1

2

Figure 3-6 (a) Cascade of Two Comb Filters (b) Separation of Denominator

and Numerator Sections (c) Commutation of sampling Switch and Numerator

Section (d) Implementation

In many cases, the CIC response does not satisfy the design specifications. Modified

Sinc Filters have been proposed for such applications [4].

3.1.3 Order of the CIC Filter

The cascades of integrate and dump functions, described in section 3.1.2, match the

structure of the noise from sigma delta modulation so well that these filters are ideal for

providing the initial decimation with negligible loss of signal to noise ratio. The

determination of the order of the CIC filter to be used for decimation after sigma delta

modulation is an important design criterion. As explained in [22], there is an optimum

number that determines the order of the comb to be used. The order of the CIC can be

37

determined based on the following two facts:

• For a ΣΔ modulator of order l, a CIC of order l+1 is suitable for antialias filtering

in the first stage of decimation

• This CIC can be used to reduce the sample rate to as low as 4 times the Nyquist

sampling rate with negligible SNR degradation (<0.25dB). Further reduction in

the sample rate using the CIC will degrade the SNR significantly.

3.1.4 Low Power Implementation of COMB

Power consumption in decimation filters in Σ Δ Α/D converters has become a significant

contributor to the total power consumption of a chip in today’s low power world. The

majority of the power consumed by the CIC is attributed to the integrator as it has to

work at the highest sample rate. Alternate structures of the comb have been

investigated and found to be more optimum in terms of area and power efficiency

[11][12][13][14][15] [17]. This is explained below.

Figure 3-7 shows different implementations of a comb filter. The transfer function of a

comb can be written in the recursive and nonrecursive forms as follows :

( )kz

zM

M

zH)1()1(1

1 11

1)( −

−

−

−= Recursive structure

kM

i

izM

zH ⎟⎠⎞

⎜⎝⎛

∑=−

=

−11

011

1)( Nonrecursive structure

In case the decimation factor is power of 2, the nonrecursive CIC form can be rewritten

as follows:

38

( )kN

i

i

k

i

ikM

i

i zzzzHN

∏∑∑−

=

−

=

−−

=

− +=⎟⎟⎠

⎞⎜⎜⎝

⎛=⎟⎟

⎠

⎞⎜⎜⎝

⎛=

1

0

212

0

1

01 1)(

1

In the above expression, the system function has been factored. Hence, structures can

be implemented in cascaded form. The location of downsamplers can be exchanged

with factors of the system function. This leads to a simplified structure shown in Figure

3-7(c). Each of the individual blocks in the cascade of filters can be implemented using

polyphase decomposition, as shown in Figure 3-7(d). This structure gives reduction in

power consumption as the frequency of operation of the individual elements is less

compared to the standard structure of integrator followed by differentiator.

kM

zz

⎟⎟⎠

⎞⎜⎜⎝

⎛−−

−

−

111 M y(n)x(n)

k

z⎟⎠⎞

⎜⎝⎛

− −111 M y(n)x(n) ( )kz 11 −−

( )kz 11 −+ 2 ( )kz 11 −+ 2 ( )kz 11 −+ 2 y(n)x(n)

E0(z)

E1(z)

2

2

E0(z)

E1(z)

2

2z-1 z-1

E0(z)

E1(z)

2

2z-1

y(n)

(a)

(b)

(c)

(d)

x(n)

Figure 3-7 (a) Comb Filter (b) IIR-FIR implementation (c) FIR2: a cascade of

FIR filters each decimating by 2 (d) POLY-FIR2: Polyphase decomposition

applied to FIR2

39

The power can be further reduced by altering the decimation ratio in the individual

blocks. Several implementations indicate that a proper choice of the first stage

decimation ratio gives significant reduction in power. This structure is shown in Figure

3-8. Here, the Comb has been decomposed into a first stage FIR filter with decimation

ratio P, followed by a cascade of FIR (1+z-1)k filters each with decimation ratio of 2.The

reason behind such a decomposition is that it is best to decimate in the first stage by as

much as possible . The following stages are kept at the minimum decimation ratio of 2

because when the word length is high, reduction in the sampling frequency does not

compensate for the added complexity of the polyphase decomposition.

E0(z)

E1(z)

P

P

E0(z)

E1(z)

2

2z-1 z-1

E0(z)

E1(z)

2

2z-1

y(n)x(n)

EP-1(z) P

z-1

Figure 3-8 Efficient Polyphase Decomposition of Comb Filter

3.1.5 Modified-Sinc Filters

In this section a new filter, which is designed based on the Comb, is discussed. In a CIC,

the stopband attenuation is constrained by the fixed location of the zeros. The main

idea behind modified sinc filters [4] is to make the zero distribution flexible in order to

40

attain the desired stopband, while preserving most of the low complexity

implementation of the CIC. From the transfer function of the CIC , the zeros are seen

to be located at regular intervals in the z plane given by the following equation

11...,1;

2

1 −== Mii

Mj

eiz

π

Now, if a clockwise rotation by an angle α is applied to each of the zeros of the CIC, then

the transfer function becomes

))1(

)1(1()( 1

11

1α

α

j

MjM

ezez

MzHu −

−

−−

=

Similarly, if an anticlockwise rotation by the same angle α is applied, the transfer

function becomes

))1(

)1(1()( 1

11

1α

α

j

MjM

ezez

MzHd

−−−−

= −

−

Figure 3-9 shows how the zeros get rotated in the zplane with such transformations.

-α α

(a) (b) (c)

Figure 3-9 Zero Pole Distribution of (a) M1=4 CIC (b) Angle Rotation of Zeros

(c) Rotated Sinc Filter

41

These two filters, Hu(z) and Hd(z), have complex coefficients, but they can be cascaded

to obtain a filter with real coefficients, as seen in the complete transfer function :

)cos21

)cos(211)()()( 21

1211

21

−−

−−

+−+−

==zz

zzMM

zdHzuHzrHMM

αα

Figure 3-10 Attenuation In a Third Order Sinc and A Modified Sinc

filter(M1=4)

This filter has zero at (i/M1 ± α/2π); I = 1,…M1 . If α is chosen in such a way as to put

all zeros in the required intervals, this filter, cascaded with a classical comb filter can be

used to greatly increase the stopband attenuation in the null intervals. Figure 3-10

shows the first null for a third order Sinc (M1=4) and a modified sinc. As can be seen,

the stopband attenuation has improved from –137dB to –150dB for a stopband of

1.564 to 1.578 radians. The passband droop is same for both the filters.

42

The modified sinc filter can be implemented as a polyphase FIR. Alternatively, it can be

implemented as a recursive structure as shown in Figure 3-11.This structure needs two

multipliers, one at a high rate, and one at a low rate.

z-1 z-1 z-1

M1 z-1 z-1 z-1

+ -2cosα

1+2cos(M1α)

-

Figure 3-11 Recursive Implementation of the Modified Sinc

3.1.6 Later Stages of Decimation

The Comb is generally used for performing decimation up to 4*fs. Normally, a couple of

filter stages are placed after the Comb. An efficient second stage filter can be selected

from a class of filters called the halfband. These are even order linear phase FIR filters

having a special property that every odd sample of their impulse response is zero,

except for the sample at the centre of the impulse response which has a value of 0.5.

Thus, the number of computations required to implement these filters is reduced by

approximately half. These filters have a special symmetry in the frequency response,

viz. H(ejω) = 1 – H(ej(π-ω))

This symmetry implies that the transition band of the halfband filter is centered at

ω=π/2 where the magnitude of the transfer function is 0.5. This means that this filter

43

cannot be used to decimate to more than 2fs so that the –6dB point lies at fs. Another

implication of the symmetry in the transfer function is that the ripple in the passband

equals the ripple in the stopband. This property prevents the halfband filter from

compensating the baseband droop introduced by the comb filter. Figure 3-2 shows the

transfer function of an 11 tap halfband filter.

Figure 3-12 Transfer Function of 11 Tap Halfband

The last stage filter is usually an FIR with sharp transition band. This filter will be the

most complex filter of the three stages. The sharp filtering is done at the last stage by

design, as it can work at the lowest sample rate and so the hardware complexity can be

reduced.

44

3.2 Decimation structure for band pass Σ Δ

modulator

Bandpass Σ Δ modulation is a variant of the lowpass Σ Δ modulator. Both convert an

analog signal to a high speed digital output. The lowpass Σ Δ modulator is used in

applications where the signal of interest lies in the low frequency band while the

bandpass Σ Δ modulator is used for bandpass signals. The difference between the two

is in the shape of the noise transfer functions. In the lowpass case, the NTF has nulls

around DC so that maximum signal to noise ratio can be guaranteed for lowpass signals.

In the band pass case, on the other hand, the NTF null lies in a frequency band away

from the DC. Figure 3-13 shows the nature of the NTF in the different cases. Both

modulation schemes require filtering and decimation of the digital output to yield a low

noise Nyquist rate sequence. In the lowpass Σ Δ modulator, the decimation filter is

lowpass while in the bandpass ΣΔ modulator, the decimation filter needs have a narrow

bandpass frequency characteristic.

45

fos/2 -fos/2 (b)0

NTFSTF

fos/2 -fos/2 (c)0

NTFSTF

fos/2 -fos/2 (a)0

NTFSTF

Figure 3-13 Noise Transfer Function (NTF) and Signal Transfer Function

(STF) in (a) Lowpass ΣΔ Modulators(b) Bandpass ΣΔ Modulators (b) Complex

Bandpass ΣΔ Modulators

Not much literature exists in the field of decimation for bandpass ΣΔ modulators . This

is an active area of research [21]. An optimized hardware for the decimation scheme

has been explored in [5]. Here, it is required to do narrow band filtering on a high speed

bit stream. The importance of the Comb filter in the decimation structure for the

lowpass ΣΔ modulator lies in the fact that it lends itself to a very efficient hardware

implementation. However, since the Comb is a lowpass filter, it seems inappropriate for

use in a bandpass system. This hurdle is overcome by combining some of the signal

processing required by the receiver along with the decimation filter section.

The demodulation and decoding algorithm of the receiver needs the signal to be

downconverted to baseband; i.e. the signal should be frequency translated from IF to

DC. This downconversion block is pulled in ahead of the decimation filter section. Here,

46

the signal obtained at the output of the ΣΔ ADC is first frequency down converted so as

to shift the signal from IF to DC. As a result, the signal is no more bandpass in nature

but has a lowpass frequency characteristic . Hence, the lowpass decimation structures

described earlier in this chapter can be applied to this signal. The resulting decimation

filters have architecture similar to the standard multistage decimation filter chain for

lowpass signals, with Comb as the first stage.

e-jωot

I/P Complex low pass filter

Complex O/P

fos/2 -fos/2 (a)0

fos/2 -fos/2 (c)0

fos/2 -fos/2 -fIF

fIF -fIF

0(b)

(d)

signal quantization noise

e-jω0

t

-2fIF

Figure 3-14 Complex Downconversion (a) Signal Before Downconversion (b)

Complex Sinusoidal (c) Signal After Downconversion (d) System block

Diagram of Downconverter Followed by Complex LPF

The ADC output is modulated down to DC by using a complex modulator as shown in

Figure 3-14. A straightforward implementation of this scheme will require two full

fledged multipliers; one for the real term and one for the complex term of the complex

47

exponential (e-jω0t = cos(ω0t) – j sin(ω0t))

A careful choice of the sampling frequency yields a simplified implementation. If ω =

π/4, the sine and cosine sequences have a simple structure: each term is either 0, ±1

or ±1/√2, as shown in Figure 3-15(a). Thus, the sequence can be separated into

integers and integer times 1/√2:

...1,0,1,0,1,0,1,02

1...0,1,0,0,0,1,0,0....2

1,1,2

1,0,2

1,1,2

1,04

sin −−×+−=−−−=⎟⎠⎞

⎜⎝⎛ tπ

Low pass filter

Low pass filter

Low pass filter

Low pass filter

1,0,0,0,-1,0,0,0

0,1,0,-1,0,-1,0,1

0,-1,0,-1,0,1,0,1

0,0,-1,0,0,0,1,0

1/√2

1/√2

Complex decimation Filtering

Complex O/p

cosω0T = 1,1/√2,0,- 1/√2,-1,…..

I/P Low pass filter Real O/P

-sinω0T = 0,-1/√2,-1,- 1/√2,0,…..

Low pass filter

ωo=π/4

Complex O/P

(a)

(b)

Figure 3-15 (a) Downconverter and Filter Split into Real and Imaginary Parts

(b) Simplified Complex Modulator and Low pass Filter

48

The linearity of multiplication and filtering operations can be used to separate the

streams into rational and irrational parts as illustrated in Figure 3-15(b). The

multiplicands are 0 and ±1, and hence can be implemented by Boolean operations. The

implementation can be optimized so as to multiplex a single low pass filter [5]. The

decimation filters can be implemented with the standard multistage decimation

structure meant for lowpass signals using the Comb as the first stage LPF followed by

more sophisticated digital filter in the final stage.

3.3 Decimation for complex band pass ΣΔ

modulator

Decimation for complex ΣΔ modulators has been explored in [6], [ 7]. The structure is

similar to that for bandpass ΣΔ modulators explained in the previous section. Here, the

output stream from the ΣΔ modulator is complex, so demodulation entails multiplying

two complex sequences:

[ ] [ ] ...2,1,0];sin[cos)()()()( 000 =−+=+ − nnjnnjQnIenjQnI nj θθθ

Thus, the baseband I and Q sequences, I0(n) and Q0(n), are

nnQnnInI 000 sin)(cos)()( θθ += and,

nnInnQnQ 000 sin)(cos)()( θθ −=

49

cosω0T

Re Low pass filter

sinω0T

Low pass filter

-sinω0T

cosω0T

Im

Figure 3-16 Complex Demodulation of the Quadrature Modulator’s Output Stream

The downconversion scheme is as shown in Figure 3-16. The lowpass filter can be

implemented as standard low pass digital decimation filters.

3.4 New Architecture : Motivation

The digital decimation filter architecture described above imposes certain restrictions

on the design of a receiver system. Firstly, the architecture depends on a good choice

of the sample rate such that ω= π/2 ,π/4 etc. A different choice of ω will not allow the

optimization achieved in the implementation of the down conversion mixer. Secondly,

the hardware is tied to the choice of ω. In order to comply with different wireless

standards, a fixed ω imposes constraints on design of other parts in the system like

crystal clock, PLL circuitry etc. For example, in our GPS receiver system, the reference

clock can come from the cellular engine. The frequency of this clock varies across

different wireless standards. Now, if the downconversion frequency ω is made constant

50

(e.g. pi/4 or pi/2), the PLL would be required to synthesize all the frequencies

corresponding to the different standards. This would have made the PLL design more

complicated. Instead, in our design, the LO frequency was made to be integer multiple

of the reference frequency and ADC frequency was derived by dividing the LO

frequency. Thus the IF was not constant across different standards. This made the PLL

design simple as it was required to generate clocks that are only integer multiples of

the reference clock. The baseband section, however, works at a fixed sample rate

equal to 16 times the Nyquist rate. Hence, the ratio of the IF to the baseband sample

rate varied across different standards. Thus, a constant value of ω= π/2 ,π/4 at the

downconversion mixer can not be ensured. If, on the other hand, ω was made constant

(ω= π/2 ,π/4 etc.), the PLL would need to generate clocks whose frequencies would not

be integer multiples of the reference frequency. Thus, the design complexity was

shifted from the analog to the digital domain: the complexity of the PLL design was

replaced by complexity in the design of the downconversion mixer and associated

circuitry in the baseband. Thirdly, in order to be compatible with the existing baseband

engine of the GPS receiver system, the decimation digital filtering section was required

to be placed before the baseband downconversion stage in the signal chain.

The need, therefore, was for an architecture for performing narrowband complex

filtering at IF. A new architecture for complex decimation digital filtering of the output

of a complex ΣΔ modulator is proposed in the following chapter.

3.5 Summary

Digital decimation filtering architectures have been discussed in this chapter. Standard

architectures for lowpass ΣΔ modulators are explained. The comb filter is a popular first

stage decimation filter. Several implementations of the comb are explained. Also

51

explained in this chapter is the modified sinc, which is a filter derived from the comb

transfer function. Architectures for decimation digital filtering for bandpass and

complex bandpass ΣΔ modulators, discussed in prevalent literature are explained and

the motivation for a new architecture for performing decimation digital filtering for

complex bandpass ΣΔ modulators is explained.

52

4 ARCHITECTURE FOR COMPLEX

NARROWBAND FILTERING

Figure 4-1 shows the block diagram of a low IF receiver using complex ΣΔ analog to

digital conversion. The receiver front-end starts with an RF stage. The latter has a low

noise amplifier and filter. The output of the RF stage is sent to a quadrature mixer. A

local oscillator produces a sine and a cosine of a frequency, which is slightly offset from

that of the incoming RF signal. The output of the RF stage is multiplied with these two

sinusoids in two mixers. Multiplication with the cosine yields the in-phase component

and multiplication with the sine produces the quadrature phase component. These two

components are sent to the ADC. An antialias filter is required to attenuate all signal

components present at more than half the sampling frequency of the ADC so that there

is minimum aliasing of unwanted signals after the signal is converted from the analog

to the discrete frequency domain. This filter can be placed before the ADC or can be

integrated along with the ADC as shown in the block diagram in Figure 4-1.

53

cosωct

sinωct

Antialias Filter and Complex

Bandpass ΣΔ Modulator

Digital Baseband

X

Y

Digital Decimation

Filters

A

B

RF Stage

Figure 4-1 Architecture of A Low IF Receiver Using Complex ΣΔ Analog to

Digital Converter

The ADC is an oversampled complex ΣΔ analog to digital converter. It has three salient

features: It is an oversampled system; so the quantization noise is less than that for a

Nyquist rate ADC. Secondly, it is a ΣΔ converter. Hence the quantization noise is

frequency shaped. Thirdly, the noise transfer function is complex i.e. it has an

asymmetric frequency response with respect to the zero frequency axis. Hence, this

ADC can be used to recover only those signals that are complex in nature.

The ADC converts the signal from the analog to the digital domain. The output of the

ADC consists of two streams of single bit data. This data represents the mixer outputs

in addition to quantization noise generated by the operation of analog to digital

conversion. The digital decimation filtering block attenuates the quantization noise and

reduces the sample rate.

The digital baseband section performs downconversion of the digital filter output from

IF to DC and further reduction in sample rate to Nyquist rate, followed by demodulation

and decoding to extract the transmitted data from the signal.

54

4.1 Frequency Spectrum Analysis of The

Image Reject Receiver

Let us look at the frequency components of the signal at different stages of the chain.

Let us assume that the incoming RF signal is present in a frequency band centered on

(ωc+ ωif) and the local oscillator produces sinusoids of frequency ωc. Mixing is essentially

a multiplication operation. Hence, the output of the mixer will be as given by the

following equation:

;2/))cos()2(cos()cos()cos( tttt ififccifc ωωωωωω ++=×+

Thus, each mixer output contains two sets of signals, one at ±ωif and the other at ±2ωc

+ ωif. The latter is filtered while the components at ωif are passed through the system.

Thus, essentially, the mixing process translates the signal in the frequency domain

from RF to IF. In the process, all signals equidistant from the oscillator frequency in the

frequency axis, get translated to the same IF. So, along with the desired RF signal at

(ωc+ ωif) , any interfering signal present at (ωc- ωif) also get translated to the same IF.

This is apparent from the following equation:

;2/))cos()2(cos()cos()cos( tttt ififccifc ωωωωωω +−=×−

Thus, the mixer output contains a superposition of the desired RF signal, originally

present at (ωc+ ωif) and the interfering signal, originally present at (ωc- ωif). The latter

is called the image signal. It has no relationship with the desired signal but appears as

a noise at the mixer output.

This can also be seen by doing a frequency domain analysis of the signals. Figure 4-2

55

shows the frequency spectrum. The desired signal and image signal spectrum are as

shown in Figure 4-2a): these are signals present at ωif and -ωif distance from the

oscillator frequency. The local oscillator outputs, the sine and cosine of ωc, are impulses

at ωc, as shown in Figure 4-2(b) & (c). Now, multiplication in time domain is equivalent

to convolution in the frequency domain. A convolution of the impulse in Figure 4-2 (b)

and the signal in Figure 4-2 (a) gives the superposition of the signal and image at ±ωif

as seen in Figure 4-2 (d). Similarly, a convolution of the impulse in Figure 4-2 (c) and

the signal in Figure 4-2 (a) gives the superposition of the signal and image at ±ωif as

seen in Figure 4-2 (e).

The job, now, is to remove the image signal and extricate the desired signal from the

signal obtained at ±ωif. This can be achieved by doing a complex summation of the

mixer outputs. This is shown in Figure 4-2 (f),(g) and(h). The difference in the phase

of the signal and image components in the quadrature phase component of the mixer

(Figure 4-2 (e)) , is utilized to recover the signal. This scheme is called the image reject

receive scheme.

The mixer outputs are fed to the ΣΔ analog to digital converter. The ADC has a complex

noise transfer function (NTF) and a complex signal transfer function(STF). The output

of the ADC consists of two single bit data streams. A complex sum or difference of these

two bit streams has the following frequency components:

i. the desired signal at ±ωif

ii. the image signal attenuated by the STF

iii. the quantization noise shaped according to the NTF

These components are shown in Figure 4-3. The complex STF, shown in Figure 4-3(a)

56

and (b) , pass the desired signal and attenuate the image signal partially from the

complex sum and difference of the mixer outputs. The complex NTF, shown in Figure

4-3 (a) and (b) , shapes the quantization noise. Figure 4-3 (c) and (d) show the signal

present at the ADC outputs. It is to be noted that, the individual data bits do not have

any significant interpretation and it is only the complex sum or difference of these bits

that can be meaningfully interpreted.

4.2 Digital Filtering

The job of the digital filters, placed after the ADC, is apparent from the signal spectrum

shown in Figure 4-3. The digital filters need to attenuate the image signal and the

quantization noise present outside the signal band. A complex digital filter with

passband centered around -ωif can extricate the desired signal from the complex sum of

the ADC output bits. Similarly, a complex digital filter with passband centered on ωif will

filter the desired signal from the complex difference of the ADC output bits. This is

shown in Figure 4-4.

57

ωc -ωc 0 ω-ω

desired signal

image signal band

ωc -ωc 0 ω-ω

1/2

ωc -ωc 0 ω-ω

j/2

-j/2

(a)

(b)

(c)

ωif-ωif 0 ω-ω

1/2 (d)

ωif-ωif 0ω-ω

j/2 (e)

-j/2

ωif-ωif 0 ω-ω

1/2 (f)


-ωc + ωif

A= IP*cosωct

B= IP*sinωct

cosωct

sinωct

IP

j*B

ωif-ωif 0 ω-ω

1(g) A+j*B

ωif-ωif 0 ω-ω

1(h) A-j*B

Figure 4-2 Signal Spectrum of (a) Incoming RF Signal (b) cosωct (c) sinωct (d)

in-phase o/p of Mixer (e)Out-of-phase o/p of mixer (f) Out-of-phase

component multiplied by j (g) Signal and Image Separated (h) Signal and

Image separated

58

Noise Transfer Function

Signal Transfer Function

ωif-ωif 0 ω-ω

(a)

ωif-ωif 0 ω-ω

(b)

A+j*B

A-j*B

ωif-ωif 0 ω-ω

(c) X+j*Y

ωif-ωif 0 ω-ω

(d)

X-j*Y

Quantization noise Desired Signal Residual Image Signal

Figure 4-3 (a)Complex Sum of Mixer Outputs, STF and NTF of ADC (b)

Complex Difference of Mixer Outputs, STF and NTF of ADC(c) Complex Sum of

ADC Outputs(d) Complex Difference of ADC Outputs

Two filters DF1 and DF2 having complex transfer functions are used to extricate the

desired signal as shown in Figure 4-4 (a) and (b). The outputs of these two filters are

combined in Figure 4-4 (c) to obtain a real two sided bandpass signal. This is the

desired signal. Figure 4-5 shows the block diagram of the corresponding filter operation.

It is to be noted, here, that the use of the term “j” in Figure 4-5 is only conceptual and

has got no physical entity in the actual implementation, explained later in the chapter.

59

A close look at the block diagram in Figure 4-5 reveals that a direct implementation of

the complex filters working on the complex sum and difference of the ADC outputs

would require 4 convolutions to be performed inside each filter; two for the real term

and two for the imaginary term. The computational complexity can be drastically

reduced by doing a simple mathematical manipulation, as explained in the next

section.

ωif-ωif 0 ω -ω

(a) DF1

ωif-ωif 0 ω -ω

(b)

DF2

ωif-ωif 0ω -ω

(c)

Quantization noise Desired Signal Residual Image Signal

Figure 4-4 (a)Complex Digital Filtering on X+jY (b)Complex Digital Filtering

on X-jY (c) Real Two sided Bandpass Signal Obtained After Digital Decimation

Filtering

Complex Sigma Delta Analog to Digital Converter

OP j

-j

DF1 (Complex Digital Filter)

X

Y

P

QDF2 (Complex Digital Filter)

Figure 4-5 Complex Digital Filtering on Output of Complex ΣΔ ADC

60

4.2.1 Simplification of Computation

Let the two complex digital filters have transfer functions HDF1(z) & HDF2(z), as shown

in Figure 4-6.

Let, );()()(1 zjHzHzH IMREDF −=

Then, as DF1 and DF2 are a complex conjugate pair ,

);()()(2 zjHzHzH IMREDF += where HRE(z) and HIM(z) are real transfer

functions

Now, );().()().( 21 zHzQzHzPOP DFDF +=

=> )]()()][(()([)]()()][(()([ zjHzHzYjzXzjHzHzYjzXOP IMREIMRE +−+−+=

=> )()()()([2 zHzYzHzXOP IMRE += ---(i)

ωif-ωif 0 ω-ω

ωif-ωif 0 ω-ω

DF1 Transfer Function


Figure 4-6 Transfer Functions of DF1 and Df2

From (i) it is apparent that complex digital filtering can be accomplished by using two

real filters corresponding to the real and imaginary parts of the transfer function of the

61

individual complex filter.

This structure is shown in Figure 4-7. This optimization reduces the computational

complexity to one fourth, as a single convolution has replaced 4 convolutions in each

branch.

RF Amp and Filter

90

Antialias Filter and Complex

ΣΔ Modulator

cosωct

sinωct

IP

A

B

OP

HRE(z)

X

Y

HIM(z)

Figure 4-7 Complex Digital Filter Structure

4.3 Summary

The frequency domain analysis of an Image Reject Receiver is explained in this chapter.

The frequency domain analysis of an image reject receiver utilizing complex ΣΔ Analog

to Digital Converter is discussed next. The role of the digital decimation filter is

analyzed. The chapter concludes with the derivation of an optimized structure for

complex narrowband filtering for such a receiver. The implementation details are

explained in the following chapters.

62

5 DECIMATION FILTER STRUCTURE

The decimation digital filters in this system perform the following functions:

i. antialias filtering and reduction of the data rate

ii. attenuation of remaining out of band components in the signal

iii. generation of a real two sided signal centered around ±ωif

The above classification forms the basis of the partitioning of the filter section. This is

explained in section 5.2. The design of the actual filters is explained in subsequent

sections. Before going into the filter details, it is necessary to describe the frequency

plan, first . This is explained in the next section.

5.1 Frequency Plan

The GPS receiver is designed for use in mobile phone systems catering to different standards

(GSM, WCDMA etc.) As explained in section 3.4, here the IF is made to vary within a small range

around 4Mhz so that integer ratios can be used to derive the required clocks from the PLL. The

ADC works at sample rates ranging from 261.88MHz to 263.25MHz. The sample rate at the digital

filter output varies from 16.368MHz to 16.453125MHz. The signal band exists within 750KHz on

either side of the IF. The passband of the digital filter is chosen in such a manner that all the

different standards can be accommodated. This results in a signal passband that extends from

0.37π to 0.59π on either the positive or negative frequency axis, depending on where the signal lies.

63

In the remaining part of this thesis, the sample rate at the digital filter output is indicated as fs. The

data at the ADC output has a sample rate of 16fs. Decimation by 16 is performed inside the digital

filter section. fs take values close to 16MHz. Since, the discrete frequency domain scales with the

sample rate, it is sufficient to analyze the system using a single frequency. For the ease of

explanation, the thesis is written assuming a constant value of 4MHz for the IF, 256MHz for the

ADC sample rate(16fs) and 16MHz for the sample rate at the digital filter output (fs).Translating the

extreme passband edge numbers for a sample rate of 16MHz, the signal band becomes 2.96MHz

to 4.72MHz

The task of frequency downconversion to DC and further decimation to the Nyquist rate is

performed in the digital baseband section. The latter is outside the scope of this thesis and will not

be discussed.

5.2 Digital Filter Partitioning

As explained in section 3.1.1, multistage decimation is the architecture of choice for

most applications. In our receiver, decimation is achieved in stages of 4,2 and 2. The

first two stages are real filters. These are implemented in duplicate, one each for the

two streams of data coming from the ADC. The complex filtering is achieved in the last

of these three stages, which also performs the final decimation by 2. This filter is

implemented by splitting the real and imaginary parts of the filter transfer function and

adding the two outputs, as explained in section 4.2.1. A droop correction filter is placed

at the end of the filter chain to correct the in band droop produced by the preceding

filter stages and also to provide sharp filtering of the residual quantization noise. This

structure is shown in Figure 5-1.

64

COMPLEX FILTER

AAF1 4

AAF2 2

REAL PART

2 4fs 2fs16fs

16fs

fs

fs

DROOP CORRECTION

FILTER

COMPLEX ΣΔ ADC MIXER

O/P AAF1

4 AAF2

2 IMAGINARY

PART 2

4fs 2fs

I Q

OP

Figure 5-1 Multistage Decimation Filter Structure

5.3 ADC NTF and STF

The signal and noise components present in the ADC output data is now analyzed.

Figure 5-2 shows the FFT of the complex sum of the ADC output bit streams (X+jY) for

a single tone. Here, fs=256MHz, ωif=4MHz.

Figure 5-2 FFT Of ADC Output For A Single Tone Input

65

The noise floor in the 3MHz to 5Mhz range is -98 dB. The decimation filters are

expected to attenuate the out of band noise. The attenuation should be sufficient so

that after downsampling, the aliased noise does not raise the in band noise floor

significantly i.e. there should be negligible degradation in the signal to noise ratio in the

band of interest.

5.4 Stage One Antialias Filter (AAF1)

As explained in section 3.1.2, a popular first stage anti aliasing filter is the comb.

However, the comb has a low pass transfer function while in this application the signal

is bandpass in nature. If the IF band is included inside the passband, then the comb

can be used. This imposes two stringent restrictions on the design:

i) The passband of the filter is more than the actual bandwidth of the signal. The

signal of interest is present in a 2MHz band around ±ωif. But the comb has a

passband from (-ωif-1Mhz) to (ωif+1Mhz). This implies that the desired signal is

present at the edge of the passband. In the lowpass decimation structure for ΣΔ

modulators, the comb can be used for reducing the sampling rate to as low as

4*fn (fn = Nyquist sampling rate) [22], i.e. 8 times the signal band. However, in

this application the same rule cannot be used. Here, the signal extends in a

2MHz band around IF(4MHz). The Nyquist rate is 4MHz and ideally, the comb

should have been used to downsample to 16MHz; i.e. the decimation factor

would be 16.However, since the signal is bandpass in nature, the comb can be

used to down sample till 8 times the edge of the passband i.e. till 40 MHz

(=8*5MHz). Choosing a factor of 2 decimation ratio, the comb is used here to

66

decimate by 4 (down sample to 64MHz).

ii) The desired stopband lies in a 2MHz band situated at ωif distance on either side

of the nulls, as it is these frequency components that will alias on to the desired

signal present at ±ωif . This implies that the frequency components that will alias

after downsampling lie at the extreme edge of the stopband. This results in a

wider stopband around each null than for a lowpass signal. For example, for a

sample rate of 256MHz, an IF of 4 MHz, the passband is from –5 MHz to 5Mhz

while the stopband width is 10 MHz centered on each null. Had the signal been

low pass in nature, the passband would have been –1Mhz to 1Mhz and the

stopband width would have been 2Mhz around each null.

As noted in section 3.1.3 [22], for an lth order modulator, the optimum comb order is

(l+1) [22]. This analysis is limited to modulators of order =<2. Although , in this

system, the modulator has order 3, we apply the same rule for choosing the order of

the comb. Hence, the comb order is chosen to be 4. A frequency domain analysis of the

fft of the output shows that this is sufficient.

The transfer function of the filter is :

4

11

41

41)( ⎟

⎟⎠

⎞⎜⎜⎝

⎛=

⎟⎠⎞⎜

⎝⎛ −−

⎟⎠⎞⎜

⎝⎛ −−

z

zzH

5.4.1 Filter Specifications

The noise floor in the 3MHz to 5Mhz range is -98 dB. Now, since AAF1 performs

downsampling by 4, the aliasing bands for this filter are: 59MHz to 69MHz, 123MHz to

133MHz, 187MHz to 197MHz.

67

The maximum noise at these bands is seen to be -35dB. Now, the noise in the aliasing

bands needs to be attenuated to a level low enough, so that after aliasing, the in band

noise does not degrade much. i.e. after the aliasing the net noise floor should not rise

much compared to the in band noise floor of –98dB. Hence, required attenuation should

be greater than ( -35 - (-98) =) 63dB .

5.4.2 Filter Transfer Function

Figure 5-3 shows the transfer function of the filter for a sample rate of 256MHz. It has

4 zeros at each of ±π/4 and ±π/2; i.e. at 4fs and 8fs. The stopband attenuation, as

shown in Figure 5-5, is around 83.1dB . The passband droop , as can be seen in Figure

5-4, is 0.33dB.

Figure 5-3 Transfer Function of Fourth Order Comb

68

Figure 5-4 Passband Ripple of Fourth Order Comb

Figure 5-5 Stopband Attenuation of Fourth Order Comb

69

5.5 Stage Two Antialias Filter (AAF2)

The second stage filter performs a further reduction in sample rate by 2. An 11 tap

halfband is used for this purpose. The coefficients are quantized to 15 bits. Its transfer

function is as follows:

H(z)= h0 + h2z-2 + h4z-4 + h5z-5 + h6z-6 + h8z-8 + h10z-10

The halfband filter is a low pass filter. As for the comb, the passband for this filter has

been defined so as to include the band around ± ωif.

5.5.1 Filter Specifications

AAF2 performs downsampling by2. Assuming the ADC sample rate to be 256MHz,the

aliasing bands for this filter are: 27MHz to 37MHz on both the positive and negative

frequency axes. The maximum noise in these bands is seen to be -35dB. Hence,

required attenuation should be greater than ( -35 - (-98) =) 63dB .


The transfer function is shown in Figure 5-6, for a sample rate of 64MHz(4fs). The

stopband attenuation, shown in Figure 5-8, is about 64 dB. The passband ripple, shown

in Figure 5-7, is negligible (0.0027dB/-0.0054dB). Attenuation provided by the cascade

of comb and halfband is 75.8dB.

70

Figure 5-6 Transfer Function of Halfband Filter

Figure 5-7 Passband Ripple of Halfband Filter

71

Figure 5-8 Stopband Attenuation in Halfband Filter

5.6 Image Reject Filter (Complex Filter)

This filter attenuates signal and noise components present in the image band. Hence, it

is called the image reject filter. This is a complex filter. It is implemented using a

structure explained in Section 4.2.1.

72

ωif-ωif 0 ω-ω

ωif-ωif 0 ω-ω



Figure 5-9 Transfer Functions Of DF1 And DF2

As explained in 4, a pair of complex conjugate filters, DF1 and DF2, are required for

performing image rejection and obtaining a real signal. As is apparent, it is sufficient to

derive the coefficients for either of DF1 or DF2. Here, we will discuss the design of DF2.

This filter has been designed using techniques described in [4] and explained in section

3.1.5. The chief purpose of this filter is to attenuate signal components present at the

image frequency. As the comb filter provides sharp narrowband attenuation around its

zeros, it is chosen as the base filter from which the complex image reject filter is to be

derived. The comb filter is first frequency translated so that the passband shifts to

low-IF. The filter transfer function , then becomes:

α

α

jez

DjeDzD

zIRH−−−

−−−=

11

11)( where α is the shift in frequency.

73

Figure 5-10 Transfer Function of Four Tap Comb and Shifted Comb

This filter works at a sample rate of 2fs. The filter passband needs to be centered at ωif,

which is at fs/4 i.e. one eighth of the sample rate of the image reject filter. Hence, α

should be π/4. The number of coefficients (D) of the comb is chosen in such a manner

that, after frequency translation, its passband aligns with the signal band centered on

ωif and the zero aligns with the image frequency centered around -ωif. A 4 tap comb is

required so that after frequency translation by π/4 to the positive frequency side, the

pass band is at π/4, and the zeros are at –π/4, -3π/4, 3π/4. As can be observed from the

transfer function of the filter, the zero placements is such that decimation by two can

be performed at the output of this filter. The aliasing bands are at ±3π/4, where zeros

have been placed. The transfer function of the shifted 4 tap comb is shown in Figure

5-10. The filter works at 2fs(32MHz).The shifted comb has zeros at –4Mhz(image band)

and ±12Mhz (aliasing bands).

74

Figure 5-11 Derivation of The Image Reject Filter From A Comb

In the actual design, taking α= 1.01*π/4 gives better image rejection with quantized

coefficients.

The shifted comb is modified further by spreading the zeros to increase the width of the

stopband. The zeros are spread on either side twice; so each zero gets replaced by 4

zeros located close to each other. The resulting filter is a cascade of the 4 filters.

5.6.1 Filter Specification

The aliasing bands are 2MHz bands centered around is -4MHz,±12MHz. The maximum

noise at these frequencies is seen to be -56dB. Hence, the required attenuation should

be greater than ( -56-(-98)= ) 42 dB.

75


The transfer function is shown in Figure 5-11. The filter has 13 complex coefficients,

quantized to 15 bits. The effect of coefficient quantization is shown in Figure 5-12. It

gives more than 76dB of attenuation in the image band(-5Mhz to –3MHz). The

passband droop, as can be seen from Figure 5-13 , is 0.94dB at 3MHz.

Figure 5-12 Effect of Coefficient Quantization On The Stopband Attenuation

of Image Reject Filter

76

Figure 5-13 Passband Droop Of Image Reject Filter

Figure 5-14 Phase Response of Image Reject Filter

77

Although the comb is a linear phase filter, the modified and shifted comb needs to be

analyzed for its phase response. This is shown in Figure 5-14. As is evident, the phase

is linear in the passband (3.1125MHz to 5.1125Mhz). The nonlinearity in the phase in

the stopband (-5.1125Mhz to –3.1125MHz) is of no consequence to the performance of

the GPS receiver system.

As explained in Section 4.2.1, the real and imaginary parts of the transfer function of

DF2 are split up to operate on the two output bit streams of the ADC. The outputs of the

two filters are summed. This produces the real two sided bandpass signal at +/–ωif.

Figure 5-15 shows the transfer functions of DF1 and DF2. As is evident from the figure,

DF2 has a null at –ωif (i.e. at –π/4 or –4.1125MHz ) ; at the same place as the passband

of DF1. This makes sure that the noise present on the complex sum of the ADC outputs

(X+jY) at –ωif is sufficiently attenuated by DF2, so that after summing the two outputs

from the real and imaginary sections of the complex filter, there is negligible

degradation in the signal to noise ratio at –ωif. Similarly, DF1 null is at ωif to ensure

negligible SNR loss at ωif.

78

Figure 5-15 Transfer Function of DF1 and DF2

5.7 Summary

A detailed description of the filter architecture is given in this chapter. The first section

gives some details of the frequencies used in the chip. Next, an fft of the ADC output is

analyzed to understand antialiasing requirements for the digital decimation filters. The

partitioning of the filter chain is discussed, next. The design of the two decimation

filters and the image reject complex filter are described in the later sections of this

chapter.

79

6 DROOP CORRECTION FILTER AND

IMPLEMENTATION

The last filter in the chain is a real filter called the droop correction filter. This filter

processes the real signal coming from the complex image reject filter and passes it on

to the baseband processing block.

6.1 Droop Correction Filter

The purpose of this filter is twofold:

I) to correct the passband droop introduced by the three preceding filter

stages

II) to perform sharp bandpass filtering and attenuate remaining out of band

quantization noise

A 49 tap FIR is used for this purpose. This filter is synthesized by designing a low pass

inverse SINC and transforming it to a bandpass filter by weighting the coefficient

sequence with samples of (sin πn/2);n=1,2,..49.

6.1.1 Filter specifications

The maximum out of band noise at the filter input is 78dB. Hence, the required

80

attenuation should be greater than ( -78-(-98)=) 20dB. Actual attenuation provided by

the filter is more than 30dB.


The transfer function of this filter is shown in Figure 6-1. The passband ripple is shown

in Figure 6-2. As can be seen, the combined droop due to the three preceding stages of

filters result in a net droop of –1.07dB at the edge of the passband (-5MHz). After droop

correction, the passband ripple is limited within 0.02dB and -0.28dB.

Figure 6-1 Transfer Function of Droop Correction FIR

81

Figure 6-2 Droop Correction

Figure 6-3 Final Transfer Function : DF2 path for filtering X-jY

82

Figure 6-4 Final Transfer Function : DF1 path for filtering X+jY

The net channel transfer functions are shown in Figure 6-3 and Figure 6-4. The complex

sum of the ADC output bit streams, (X + jY), is filtered by the transfer function shown

in Figure 6-4. The complex difference of the ADC output bit streams, (X - jY), is filtered

by the transfer function shown in Figure 6-3. The sum of these two filtered signals is

what constitutes the output of the digital decimation filter block. It is to be noted that

the complex transfer functions shown in Figure 6-3 and Figure 6-4 are relevant only for

the purpose of analysis. The generation of complex sum (X + jY) and difference (X - jY)

is not performed explicitly in the actual implementation, which is shown in Figure 5-1.

6.2 Data Quantization

All the filters are implemented as direct form structures, using two’s complement

arithmetic. Full precision arithmetic is performed inside each filter and the final result is

83

quantized. Thus the quantization error can be modeled as an additive noise source.

This is shown in Figure 6-5.

z-1 z-1 z-1

h1 h2 h0 hn Quantization Noise

I/P Data

O/P Data

Figure 6-5 Direct Form Implementation of FIR

The noise generated by a quantizer with quantization levels equally spaced by Δ is

uncorrelated and is distributed uniformly between -Δ/2 and Δ/2 with power, SQ=Δ2/12.

The noise is spread uniformly across the frequency spectrum and so the power spectral

density of the noise is equal to SQ/fs. Figure 6-6 shows the PSD of the quantization

noise. The quantization level spacing Δ , for data quantized to (B+1) bits, is:

Δ= 1/2B … (2)

Thus, the PSD,

SQS = 2-2B/12fs … (3)

84

-fs/2 fs/2 DC

Δ2/12fs

frequency

Figure 6-6 PSD Of Uncorrelated White Quantization Noise

Now, the data quantization at the filter outputs should be such that there is negligible

degradation in the noise floor compared to the noise at the ADC output. The noise floor

in the band of interest (3MHz to 5MHz) is shown in

Figure 6-7. The noise has a null at 4MHz and increases on either side. The number of

data quantization bits, B is chosen is such a manner that the noise due to quantization

falls below that at the ADC output FFT.

85

Figure 6-7 FFT of ADC Output

The data quantization was also analyzed using an empirical method. The SNR was

computed at each stage of the filter chain with number of bits for data quantization

being varied. Analysis of the results suggests an optimum bit allocation as follows:

• halfband : 13

• image reject filter : 14

6.3 Hardware Considerations

The filters were coded in Verilog and synthesized using Synopsys tools. Various

architectures were evaluated for optimization of area and power. The first architecture

experimented with was as follows.

Cascaded Integrator Comb implementation for Comb (AAF1), multiplier based

architectures for halfband(AAF2) , Image Reject Filter and droop correction FIR. This

scheme was found to consume a lot of power.

86

Hence, the implementation was changed as follows.

The COMB(AAF1) was implemented as a cascade of FIRs as explained in Section3.1.4.

The coefficients of the halfband and the image reject filter were coded with canonical

signed digits (CSD) and the filters implemented with shift and add stages. The droop

correction FIR was implemented as a multiplier based structure.

6.4 Silicon Results

Figure 6-8 shows a plot of the FFT of the digital filter output for a sinusoidal input. The

FFT of the ADC output is shown along with the FFT of the output from the digital filter.

It can be seen from the figure that the quantization noise floor in the passband at the

digital filter output overlaps that at the ADC output. In the transition band (~1MHz on

either side of the passband), the noise begins to decrease and at the stopband region

the noise is down by about 40dB with respect to inband noise floor.

ADC O/P

Digital Filter O/P

Figure 6-8 FFT of Silicon Data At The Output Of Digital Filters and ADC

6.5 Summary

This chapter started with a discussion of the design of the droop correction filter. The

net transfer function of the entire decimation filter system was analyzed next. The

87

implementation details covering the choice of hardware and data quantization effects

were also discussed. The chapter concluded with a brief description of the silicon

results.

88

7 OPTIMIZED ARCHITECTURE

The decimation filter architecture described in the previous three chapters, is examined

for possible improvements in this chapter. A cursory look at the filter structure hints at

a scope for optimization in the choice of the first two stages of filtering. The use of

lowpass filter transfer functions for a system meant for complex bandpass signals,

indicates a suboptimal choice of the filter. This was also made apparent in Section 5.4

where it was mentioned that the use of lowpass filters for AAF1 severely restricted the

amount of decimation achievable by the comb filter .In a lowpass ΣΔ converter (of

order <=2), a decimation by 16 is possible for a signal of similar bandwidth. In this

system, the modulator has order 3 and the comb is used for bandpass filtering. This

results in a decimation ratio of 4. If, however, the comb can be replaced by a complex

bandpass filter, higher amount of decimation can be achieved. This is explored in the

rest of this chapter.

7.1 Complex Bandpass Antialias Filtering

The architecture suggested in Figure 4-7 and implemented in Figure 5-1, gives a

simplified method of implementing a complex image reject filter. However, if the

antialias filter stage preceding the image reject filter is made complex, the decimation

filter architecture will change to a cascade of complex filters. This will mean additional

computations compared to a cascade of real filters. The structure for such a system is

discussed in this section.

89

Here, the first two stages(AAF1 and AAF2) are combined into one single complex filter

(AAF). The cascade of the complex filter, AAF, and the complex image reject filter is

discussed below. The simplification in computation described in Section 4.2.1, will be

used in deriving the structure of the cascade of the two complex filters.

Let the new antialias filter have a transfer function as follows:

);()()( zjHzHzH AAFMAAFREAAF += …7.1

The second complex filter, the image reject filter DF1, has a transfer function as

follows:

);()()(1 zjHzHzH IMREDF −= …7.2

Then, if the two output bit streams from the ADC are X(z) and Y(z), the output of the

cascade of the two complex filters is as follows:

)](*)(*)]()(Re[[2 1 zHzHzjYzXOP DFFAA+= …7.3

i.e. the output, OP, will be equal to twice the real part of the signal resulting from

filtering the complex sum of the ADC outputs by a cascade of the two complex filters:

antialias filter AAF and image reject filter DF1.

Now,

)(*)](*)()(*)([)(*)](*)()(*)([)](*)(*)]()(Re[[

)]()([*)]](*)()(*)([)](*)()(*)([[)]()([*)]()([*)](()([

)(*)(*)]()([

1

1

zHzHzXzHzYzHzHzYzHzXzHzHzjYzX

zjHzHzHzXzHzYjzHzYzHzXzjHzHzjHzHzYjzX

zHzHzjYzX

IMAAFIMAAFREREAAFIMAAFRE

DFAAF

IMREAAFIMAAFREAAFIMAAFRE

IMREAAFMAAFRE

DFAAF

++−=+=>

−++−=−++=

+

….7.4

90

The above equation yields a structure shown in Figure 7-1. Here, the real and

imaginary parts of the AAF are split up and four sets of convolutions are performed with

the dual bit stream output of the ADC. The four convolution sums are added in pairs to

yield two outputs. These are then sent to the image reject filter which, again, is

implemented in two branches, one for the real and one for the complex. The two

outputs from the image reject filter are added to form the output OP. This output is a

real signal and its sample rate is Fs. This needs to be further filtered by a droop

correction FIR, similar to the one used in the previous architecture.

-

OP

HRE(z)

HIM(z)

HAAFRE

HAAFIM

HAAFIM

HAAFRE

Complex Sigma Delta ADC

X

Y

Figure 7-1 Cascaded Complex Digital Filter Structure

7.2 Alternate Filter Architectures

A couple of alternate filter architectures for decimation digital filtering in complex ΣΔ

converters are explored in the remaining part of this chapter. These structures employ

a mix of real filters and cascade of complex filters. The motivation behind this analysis

is to investigate if the decimation filter structure can be optimized if complex filtering is

allowed. The different architectures are evaluated for area and a comparative analysis

is performed at the end.

91

7.3 Alternate Architecture I

The first structure to be explored is a decimation stage employing complex filters,

followed by the image reject filter and droop correction filter. The last filter in the chain

is a real filter and all the other filters have complex transfer functions.

7.3.1 Complex Decimation Filter Structure

As described in section 3.1.3, for low pass ΣΔ modulators, the comb can be used as a

first stage decimation filter for reducing the sample rate down to 4*fn; where fn is the

Nyquist sampling rate. This rule holds for modulators of order less than or equal to 2.

We however, try using the same formula for this system, where a third order complex

band pass ΣΔ modulator has been used. If the zeros of the comb filter are frequency

translated such that the resulting passband aligns with the passband of the complex

signal, then it can be used for decimation up to 4*fs. The order of the comb remains the

same as above.

In this receiver, the signal band is 2MHz wide. Hence the Nyquist sampling rate is

4MHz(fs) and the frequency translated comb can perform a decimation till 16MHz (=

4fs). The order of the ΣΔ modulator is 3 (i.e. = 3). Hence, the order of the frequency

translated comb should be 4 (i.e. = l+1). The ADC sampling rate is 256MHz. The

frequency translated comb will down sample the signal to 16MHz;hence its decimation

ratio is 16.

We start with a 16 tap comb of order 4. Its transfer function is as follows:

4

1

16

)1()1(

161)( ⎟⎟

⎠

⎞⎜⎜⎝

⎛−−

= −

−

zzzH …7.5

92

As explained in section 3.1.4 , H(z) can be expressed as a cascade of FIR filters as

follows:

( ) 484442414

)1()1()1(1161)( −−−− ++++⎟

⎠⎞

⎜⎝⎛= zzzzzH …7.6

For low power, a POLY-FIR structure yields an optimum implementation [13]. Hence,

we rewrite H(Z) as follows:

( ) 484443214

)1()1(1161)( −−−−− +++++⎟

⎠⎞

⎜⎝⎛= zzzzzzH …7.7

Now, for complex bandpass filtering, we need to translate the zeros of this filter in the

frequency domain. The signal band is 3 MHz to 5 MHz. Since the ADC sampling rate is

256MHz, the comb zeros need to be translated by pi/32 (=2*π*4e6/256e6). Applying

this translation , H(z) becomes as follows:

4)4/81(4)8/41(432/3316/232/11

4

161)( jpiezjpiezpijezjpiezjpiezzH −+−+⎟

⎠⎞

⎜⎝⎛ −+−+−+⎟

⎠⎞

⎜⎝⎛=

…7.8

93

STAGE 1

STAGE 2

STAGE 3

Hc1R

(13 taps)

Hc1I (13 taps)

Hc1I (13 taps)

Hc1R (13 taps)

X

Y

Hc2R (5 taps)

Hc2I (5 taps)

Hc2I (5 taps)

Hc2R (5 taps)

4

4 Hc3R (5 taps)

Hc3I (5 taps)

Hc3I (5 taps)

Hc3R (5 taps)

2

2

2

2

OP_Q

OP_I- - -

Figure 7-2 Shifted Comb Structure For Downsampling by 16

Thus, the resulting filter is a cascade of three FIR filters, performing decimation in

stages of 4,2 & 2.

The first filter is a 13 tap filter while the last two are each 5 tap linear phase filters. Each

of these three filters is a complex filter and hence can be implemented as shown in the

structure of Figure 7-1. The resulting structure is a cascade of 3 stages, each stage

having 4 real filters. This structure is shown in Figure 7-2. The transfer functions of the

three stages are shown in the figures below.

94

Figure 7-3 Shifted Comb : Stage 1

Figure 7-4 Stopband Attenuation in Shifted Comb

95

Figure 7-5 Shifted Comb :Stage 2

Figure 7-6 Stopband Attenuation in Stage 2

96

Figure 7-7 Shifted Comb Stage 3

Figure 7-8 Stopband Attenuation in Stage 3

97

Figure 7-9 Transfer Function of Shifted Comb

Figure 7-10 Passband Ripple in Shifted Comb

98

Figure 7-3 shows the transfer function of the first stage filter. The stopband attenuation

is shown in detail in Figure 7-4. The GPS signal passband is 3MHz to 5MHz.The Stage 1

filter operates at 256MHz and performs decimation by 4.Hence the stopbands are

located at 67MHz to 69MHz, -59MHz to -61MHz, -123MHz to -125MHz. The attenuation

provided by the filter after data quantization is more than 80dB.

Figure 7-5 shows the transfer function of the second stage filter. The stopband

attenuation is shown in detail in Figure 7-6. This filter operates at 64MHz and performs

decimation by two. Hence, the stopband is located at -27MHz to -29MHz. The filter with

quantized coefficients provides more than 70dB attenuation in this frequency range.

Figure 7-7 shows the transfer function of the third stage filter. The stopband

attenuation is shown in detail in Figure 7-8. This filter operates at 32MHz and performs

decimation by two. Hence, the stopband is located at -11MHz to -13MHz. This filter

provides more than 70dB attenuation in this frequency range. The net transfer function

is shown in Figure 7-9. The passband ripple is shown in Figure 7-10. The ripple is

0.223dB. The phase responses of the three filters are shown in Figure 7-11, Figure 7-12,

Figure 7-13. In the band of interest (3MHz-5MHz) the phase is linear in all three.

99

Figure 7-11 Phase Response of Stage 1


100


7.3.2 Image Reject Filtering

The image reject filter is a single rate filter, operating at 16MHz. A two tap comb is

taken as the starting point for the design . The low if frequency is at 4MHz. This implies

that the passband of the image reject filter will be at pi/2 radian away from dc(i.e. at

4MHz)and the zeros in the image reject filter should be at –pi/2 radian away from

dc(i.e. at –4MHz). Hence, the zeros of the two tap comb are shifted in the frequency

domain so as to have the passband and stopband aligned appropriately. The zeros are

further rotated on either side by 1.7*pi/16 to form a modified comb with 4 zeros . The

resulting image reject filter becomes a 5 tap linear phase filter. The resulting transfer

function is showed in Figure 7-14. The phase response of this filter is shown in Figure

7-15. The phase is linear in the band of interest (3MHz-5MHz).

101

Figure 7-14 Transfer Function of Image Reject Filter

Figure 7-15 Phase Response of Image Reject Filter

102

7.3.3 Droop Correction Filtering

This filter is the same as that used in the original architecture. The whole filter structure

is shown in Figure 7-16.The transfer function of the new architecture is compared with

that of the original architecture in Figure 7-17 . The stopband attenuation is sufficient

in all bands. The passband ripple is compared in Figure 7-18. While the original

architecture has a ripple of 0.3dB, the new one provides 0.24dB. The image rejection is

compared in Figure 7-19. The new architecture is shown to provide higher or equivalent

attenuation.

AAF & Decimation

ImageReject

Complex AAF

Stage1 4

X

Y

Droop correction (48 taps)

IRR (5 taps)

IRIM (5 taps)

OP

Complex AAF

Stage22

Complex AAF

Stage32

Complex Sigma Delta ADC

Figure 7-16 Alternate Architecture I

103

Figure 7-17 Comparison of Transfer Function : Original Architecture and

Architecture I

Figure 7-18 Comparison of Passband Ripple : Original Architecture and

Architecture I

104

Figure 7-19 Comparison of Image Rejection : Original Architecture and

Architecture I

7.3.4 Implementation

Although the cascade of three complex filters results in 4 real filter computations per

stage, there are several scopes for optimizing the area. The filter block that has the

highest area is the first filter stage since it is a 13 tap filter operating at the highest

clock frequency. However, the ADC output is a pair of single bit outputs. Hence, no

multiplier is required to implement this filter.A series of adders is sufficient to perform

the necessary computations. The filter is implemented in polyphase fashion, thus

reducing the speed of operation of the individual components and hence the total area.

The second and third filter in the chain are each 5 tap filters. The coefficients are CSD

coded. This results in a multiplier less structure. A polyphase implementation is

105

employed and so the operating speed of the filter reduces. This reduces the area

further. The details of the implementation are shown in Table 1. The unit of area used

in the table is the area of one lowest drive two input NAND gate available in the

standard cells library of the relevant technology.

106

Filter

Stage

Filter

Type

Decimation

Factor

Frequency of

Operation

Coefficient

Quantization

Output Data

Quantization

Area (NAND

Gate

equivalent)

stage 1

AAF

shifted

sinc

4 64 MHz 15 16 3409

stage 2

AAF

shifted

sinc

2 32 MHz 11 16 4460

stage 3

AAF

shifted

sinc

2 16 MHz 11 15 4657

image

reject

shifted

sinc

1 16 MHz 15 14 2208

Total 16 14736.5

Table 1 Implementation Details of Optimized Architecture I

7.4 Alternate Architecture II

The chief motivation behind exploring the shifted comb was to enable one to use the

comb for decimating till 4*fs. The block with the highest area in Architecture I

described in Section 7.3 above, is the first stage decimation where four 13 tap real filter

computations need to be performed. It is now attempted to replace the first stage

decimation with a lowpass comb, similar to the original structure. As explained in

Section 5.4, employing lowpass decimation , the passband needs to be 5 times that of

107

the actual Nyquist frequency. The signal band is 3-5MHz. If lowpass decimation is

performed, the antialias frequency band needs to cover the frequency range –5MHz to

5MHz. This implies, that the passband increases from 2MHz (3-5MHz) to 10 MHz(-5 to

5MHz). Hence, the lowpass comb can be used to decimate till no lower than 40MHz.

Using a factor of two decimation, here, the comb is used to decimate by 4. The sample

rate reduces to 64MHz. The remaining two stages of decimation remain the same as

those described in Section 7.3. The resulting structure is shown in Figure 7-20 . It

contains 4 stages as follows:

1. a 4th order comb performing decimation by 4

2. a two stage complex filter chain comprising of a 4th order shifted

comb ,performing decimation by 4 in two stages

3. image reject filtering

4. droop correction filtering

STAGE 1

STAGE 2

STAGE 3

4th

order Comb

(13 taps)

4rth order Comb

(13 taps)

X

Y

Hc2R (5 taps)

Hc2I (5 taps)

Hc2I (5 taps)

Hc2R (5 taps)

4

4 Hc3R (5 taps)

Hc3I (5 taps)

Hc3I (5 taps)

Hc3R (5 taps)

2

2

2

2

OP_Q

OP_I- -

Figure 7-20 Alternate Filter Architecture II

108

Figure 7-21 shows the transfer functions of the three antialias filters. The signal and

image band are shown in detail in Figure 7-22. The combined antialias filtering obtained

from the three filter stages is shown in Figure 7-23. The transfer function of

architecture II is compared with that of the original architecture in Figure 7-24. The

passband ripple of the two is compared in Figure 7-25. The original architecture has a

ripple of 0.3dB while the new architecture has a ripple of 0.37dB. The image rejection

of the two is compared in Figure 7-26. As in the case of architecture I, architecture II is

shown to provide higher or equivalent attenuation.

Figure 7-21 Transfer Functions of Decimation Filter Stages in Architecture II

109

Figure 7-22 Decimation Filter Stages in Architecture II :Signal and Image

Band

Figure 7-23 Anti-alias Filtering in Architecture II

110

Figure 7-24 Comparison of Transfer Function : Original Architecture and

Architecture II

Figure 7-25 Comparison of Passband Ripple : Original Architecture and

Architecture II

111

Figure 7-26 Comparison of Image Reject Filtering : Original Architecture and

Architecture II

7.4.1 Implementation

This structure was synthesized and the area obtained is shown in Table 2. The chief

area savings in this architecture as compared to architecture I described in Section7.3,

above, is in the first stage filter. The use of lowpass comb results in much simpler

computation as compared to the shifted comb. The reduction in the area of the second

stage is due to the reduction in data quantization bits at the first stage output.

112

Filter

Stage

Filter Type Decimation

Factor

Frequency of

Operation

Coefficient

Quantization

Output Data

Quantization

Area (NAND

Gate

equivalent)

stage

1 AAF

4rth

order

comb

4 64 MHz Ideal

Coefficients

10 971.75

stage

2 AAF

shifted

sinc

2 32 MHz 11 15 3147.75

stage

3 AAF

shifted

sinc

2 16 MHz 11 15 4437.25

image

reject

shifted

sinc

1 16 MHz 15 14 2209.25

Total 16 10766

Table 2 Implementation Details of Architecture II

7.4.2 Comparison Of The Three Architectures

For the purpose of a comparative study, the original filter was synthesized once again,

removing all functionalities unrelated to the function of decimation of the complex SDM

output. The details of this implementation are given in Table 3.

113

Filter

Stage

Filter Type Decimation

Factor

Frequency of

Operation

Coefficient

Quantization

Output Data

Quantization

Area (NAND

Gate

equivalent)

stage

1 AAF

4rth

order

comb

4 64 MHz Ideal

coefficients

10 1160

stage

2 AAF

11 tap

Halfband

2 32 MHz 15 13 3154.5

image

reject

shifted

sinc

2 16 MHz 15 14 11702

Total 16 16037.25

Table 3 Implementation Details of Original Architecture

A comparison of the three filters is summarized in Table 4. As is apparent from the

comparison data, the most optimum filter architecture is the alternate architecture II.

This architecture retains the lowpass comb in the first stage decimation (decimation by

4) and employs complex filtering in the subsequent stages of decimation. This allows

the use of the shifted comb for performing decimation by 16 resulting in a very small

image reject filter. Thus, the advantage of the use of the comb transfer function for

decimation up to 4*fn is retained. This helps in having the image reject filter operate at

the lowest frequency , resulting in a small filter. The same idea is used in the optimized

architecture I as well. However, in optimized architecture I, the use of the shifted comb

in the first stage decimation increases the area. The chief reason behind this is that in

114

the shifted comb , the coefficients need to be quantized. This increases the number of

data quantization bits required, which, in turn, increases the area.

Design Parameter Original

Architecture

Alternate

Architecture I

Alternate

Architecture II

Stage 1 AAF

Filter Type

Number of taps

Coefficient

Quantization

Data Quantization

Area

Real Filter

4th order comb

13

Ideal

10

1160

Complex Filter

4th order shifted

comb

13

15 bits

16 bits

3409.5

Real Filter

4th order comb

13

Ideal

10 bits

971.75

Stage2 AAF

Filter Type

Number of Taps

Coefficient

Quantization

Data Quantization

Area

Real Filter

Halfband

11

15 bits

13 bits

3154.5

Complex Filter

4th order shifted

comb

5

11 bits

16 bits

4460.75

Complex Filter

4th order shifted

comb

5

11 bits

15 bits

3147.75

115

Stage 3 AAF

Filter Type

Number of Taps

Coefficient

Quantization

Data Quantization

Area

None Complex Filter

4th order shifted

comb

5

11bits

15 bits

4657.75

Complex Filter

4th order shifted

comb

5

11 bits

15 bits

4437.25

Image Reject

Filter Type

Number of Taps

Coefficient

Quantization

Data Quantization

Area

Complex Filter

Shifted Modified

Comb

13

15 bits

14 bits

11702

Complex Filter

Shifted Modified

Comb

5

15 bits

14 bits

2208.5

Complex Filter

Shifted Modified

Comb

5

15 bits

14 bits

2209.25

Total area 16037.25 14736.5 10766

Table 4 Comparison of the Three Architectures

116

7.5 Comparison With Prevalent Architectures

In Sections 3.2 and 3.3, the decimation digital filter architecture given in previous

literature [5][6][7] were explained. The chief feature of that architecture is that the

ADC output is first down-converted to DC and then sent to the decimation filters. This

allows the use of standard low pass structures for decimation. The rate of operation of

the filters are the same as that in the structures proposed in this work. However, since

the I & the Q channels exist throughout the signal chain, two sets of filters are needed,

one each for the I and Q channel. This is not the case in the structures discussed in this

work. Here, the complex signal is transformed into a real signal in the middle of the

signal chain. As a result a single filter suffices in the last stage. This may yield some

amount of optimization in terms of area. On the other hand, the first few stages in this

architecture are complex filters. This indicates the possibility of larger area in the first

few stages, compared to the low pass filters used in the prevalent architecture. The

prevalent architecture has the additional advantage in the fact that it uses standard

lowpass decimation structures. The huge amount of research existing in the field of

lowpass decimation filtering can be directly used for an optimized implementation of

the filters. The use of complex bandpass filters in decimation filtering, on the other

hand, is an emerging field.

However, since area numbers have not been reported in the existing literature, it is

difficult to make an exact comparison of the two structures. The points discussed above

are, therefore, only indicative of areas of optimization.

117

7.6 Summary

In this chapter, two new filter architectures are proposed. These structures use a

combination of real and complex filters derived from the lowpass comb to perform

antialias filtering and sample rate reduction. The two structures are compared along

with the original architecture. It is seen that the most area efficient filter architecture is

one that employs the comb transfer function in the most optimum manner so as to

perform true complex bandpass filtering and downsampling to 4*fs. While, in the case

of the lowpass ΣΔ modulator, the comb can be used directly, in the case of the complex

bandpass ΣΔ modulator, the comb needs to be frequency translated so as to align its

passband with that of the signal present at IF. This results in a complex filter and hence

double the number of computations need to be performed, in comparison with real filter

implementations. However, since a polyphase architecture and a multiplier less

implementation using CSD coded coefficients is employed, the resulting area has been

sufficiently optimized.

A brief comparison of the proposed architecture with that discussed in prevalent

literature is made identifying the main distinguishing features, along with their merits

and demerits.

118

8 CONCLUSION

A decimation digital filter architecture for low IF Receiver using complex ΣΔ ADC is

discussed in this thesis. The digital filter performs complex narrowband filtering at IF

and converts the ADC output from complex signal to a real signal, sampled at a rate

equal to one-sixteenth of the sample rate of the ADC.

The key results of this work can be summarised as follows:

1. An architecture for conversion of the signal from complex to real domain is

proposed.

2. Design details of the actual filters that perform the above operation are

discussed.

3. Design of the decimation filters is discussed.

4. Two additional structures for decimation, aimed at optimizing the digital filter

chain are explored.

5. A comparative analysis of the proposed digital filter structures is made.

6. An analysis of the proposed structures with prevalent art is made to highlight

the distinguishing features of the two.

119

8.1 Scope of Future Work

The decimation digital filter architecture proposed in this thesis involves complex

bandpass filters. This preempts the use of the classical comb structure. The

optimization of the implementation of the filters depends largely upon the exact

coefficients of the particular filters used. A possible scope of future work lies in evolving

a generalized structure for complex bandpass filtering, similar to the CIC in the lowpass

case.

An area comparison of the actual implementation of the proposed structure with that of

the already prevalent scheme is another scope of future work. An exercise involving an

accurate calculation in such a comparison may throw some light on whether there

exists a clear method of choosing the optimum one for a particular application.

A third scope for future work lies in the accurate determination of the optimum order of

the comb to be used in such an application. In this work, the guideline used is same as

that proposed for ΣΔ modulators of order less than or equal to two [22]. This may or

may not be an optimum number for a third order modulator. Determination of the

optimum order for the CIC for modulators of order greater than two will be very useful

for the design of decimation filters.

120

REFERENCES

1. James C Candy and Gabor C Temes, ”Oversampling Methods for A/D and D/A

Conversion”,

2. Eugene B Hogenauer, “An Economical Class of Digital Filters for Decimation and

Interpolation”, IEEE Transactions on Acoustics,Speech And Signal Processing,

Vol ASSP 29,No 2, April 1981

3. Brian Paul Brandt, “Oversampled Analog to Digital Conversion”, Doctoral Thesis,

Stanford University, Electrical Engineering Department, Stanford, California,

October 1991

4. Letizia Lo Presti,” Efficient Modified-Sinc Filters For Sigma Delta A/D

Converters”,IEEE Transaction on Circuits and Systems-II:Analog and Digital

Signal Processing,Vol 47,No 11,November 2000

5. Richard Schreier and W Martin Snelgrove,”Decimation For Bandpass Sigma

Delta Analog to Digital Conversion”, IEEE International Symposium on Circuits

and Systems,1990, 1-3 May, Pages 1801-1804 Vol 3

6. Stephen Andrew Jantzi, “Quadrature Bandpass Delta Sigma Modulation for

Digital Radio”, PhD Thesis, Dept of Electrical and Computer

Engineering,University of Toronto

7. Ashok Swaminathan,”A Single-IF Receiver Architecture Using a Complex

Sigma-Delta Modulator”, ME thesis, Dept of Electronics, Ottawa-Carleton

121

Institute for Electrical Engineering, Carleton University,Ottawa,Canada

8. Stephen A Jantzi, Kenneth W Martin, Adel S Sedra, “Quadrature Bandpass ΔΣ

Modulation For Digital Radio”, IEEE Journal Of Solid State Circuits, Vol 32,No 12,

December 1997

9. Asad A Abidi, “Direct Conversion Radio Transceivers For Digital

Communications”, IEEE Journal Of Solid State Circuits, Vol 30,No12,December

1995

10. Jan Crols, Michiel S J Steyaert, ”Low-IF Topologies For High Performance Analog

Front Ends of Fully Integrated Receivers”, IEEE Transactions on Circuits And

Systems-II: Analog And Digital Signal Processing, Vol 45,No3,March1998

11. Hong-Kui Yang, W Martin Snelgrove, “High Speed Polyphase CIC Decimation

Filters”, IEEE International Symposium on Circuits and Systems, 1996

12. Yonghong Gao, Lihong Jia, Hannu Tenhunen, “A Partial-Polyphase VLSI

Architecture For Very High Speed CIC Decimation Filters”, Twelfth Annual IEEE

International ASIC/SOC Conference, 1999

13. Hassan Aboushady,Yannick Dumonteix, Marie Minverte Louėrat, Habib Mehrez,

“Efficient Polyphase Decomposition of Comb Decimation Filters in ΣΔ Analog to

Digital Converters “,IEEE Transactions on Circuits And Systems-II: Analog And

Digital Signal Processing, Vol 48,No10,October 2001

14. Youngbeom Jang, Sejung Yang, ”NonRecursive Cascaded Integrator Comb

Decimation Filters With Integer Multiple Factors”, 44th IEEE Midwest

Symposium on Circuits and Systems, Volume: 1 , 14-17 Aug. 2001

122

15. Yonghong Gao, Lihong Jia, Hannu Tenhunen, ”A Fifth Order Comb Decimation

Filter For Multi-standard Transceiver Applications”, IEEE International

Symposium on Circuits and Systems, May 28-31,2000,Geneva , Switzerland

16. Brian A White, Mohamed I Elmasry, “Low Power Design of Decimation Filters For

A Digital IF Receiver”, IEEE Transactions On Very Large Scale Integration (VLSI)

Systems, Vol 8,No3, June 2000

17. Yonghong Gao, Lihong Jia, Hannu Tenhunen, ”An Improved Architecture and

Implementation of Cascaded Integrator Comb Decimation Filters”,IEEE Pacific

Rim Conference on Communications, Computers and Signal Processing, 1999

18. Farbod Behbahani,Yoji Kishigami, John Leete, Asad A Abidi,”CMOS Mixers And

Polyphase Filters For Large Image Rejection”, IEEE Journal of Solid State

Circuits, Vol 36. No 6, June 2001

19. James F Kaiser, Richard W Hamming, “Sharpening the Response of A

Symmetric Nonrecursive Filter by Multiple Use of the Same Filter”, IEEE

Transactions on Acoustics, Speech, And Signal Processing, Vol ASSP 25, No 5,

October 1977

20. Matthias Henker, Tim Hentschel, Gerhard Fettweis, “Time Variant CIC Filters For

Sample Rate Conversion With Arbitrary Rational Factors”, The 6th IEEE

International Conference on Electronics, Circuits and Systems, Volume: 1 , 5-8

Sept. 1999

21. Ken Martin, “ Complex Signal Processing is Not Complex”, Conference on

European Solid-State Circuits, 2003, 16-18 Sept

22. James C Candy, “Decimation for Sigma Delta Modulation”, IEEE Transactions

123

On Communications, Volume COM 34,No1,January 1986

23. Alan V Oppenheim , Ronald W Schafer, ”Discrete Time Signal Processing”,

Prentice Hall Signal Processing Series

24. Ghosh Anjana, BG Chandrashekar , Venkatraman Srinivasan and Nandy S K,

“Decimation For Complex Sigma Delta Analog to Digital Conversion In A Low-IF

GPS Receiver”,10th International Symposium On Integrated Circuits, Devices &

Systems”, September 2004

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