Dual VGA with Ultralow Noise Preamplifier and Programmable RIN

AD8332FEATURES Ultralow noise preamplifier

Voltage noise = 0.74 nV/√Hz Current noise = 2.5 pA/√Hz

3 dB bandwidth: 120 MHz Low power: 125 mW/channel Wide gain range with programmable postamp

–4.5 dB to +43.5 dB +7.5 dB to +55.5 dB

Low output-referred noise: 48 nV/√Hz typical Active input impedance matching Optimized for 10-/12-bit ADCs Selectable output clamping level Single 5 V supply operation Available in space-saving chip scale package

APPLICATIONS Ultrasound and sonar time-gain control High performance AGC systems I/Q signal processing High speed dual ADC driver

GENERAL DESCRIPTION

The AD8332 is an ultralow noise, dual channel, linear-in-dB, variable gain amplifier (VGA). Although optimized for ultra-sound systems, it may be used for a low noise variable gain control in any application of frequencies up to 120 MHz.

Each channel of the AD8332 consists of an ultralow noise preamplifier (LNA), an X-AMP® VGA with 48 dB of gain range, and a selectable gain postamplifier with adjustable output limit-ing. The LNA gain is 19 dB with a single-ended input and differential outputs capable of accurate, programmable active input impedance matching by selecting an external feedback resistor. Active impedance control optimizes noise performance for applications that benefit from input matching.

The 48 dB gain range of the VGA makes the AD8332 suitable for a variety of applications. Excellent bandwidth uniformity is maintained across the entire range. The gain control interface provides precise linear-in-dB scaling of 50 dB/V for control voltages between 40 mV and 1 V. Factory trim ensures excellent part-to-part and channel-to-channel gain matching. Differential signal paths lead to superb second and third order distortion performance and low crosstalk.

FUNCTIONAL BLOCK DIAGRAM

LNA 127

28

+19dB23

26

LMD1

INH1

COM1

VPS1

LNA 21

2

3

6

LMD2

INH2

VSP2

COM2

BIAS(VMID)

VGA 1

BIAS ANDINTERPOLATOR

VGA 2

5 74

25 24 22 21

8 14 18

VMID

POSTAMP2

POSTAMP1

11

CLAMP

GAININT

20 9 19

17

16

10

13

12

[(–48 to 0) + 21] dB3.5dB/15.5dB

LON2 LOP2 VIP2 VIN2 COMM ENB RCLMP

VOH1

VOL1

GAIN

VOL2

VOH2

LON1 LOP1 VIP1 VIN1 VPSV VCM115

HILOVCM2

Figure 1. 28-Lead TSSOP

GA

IN–

dB

FREQUENCY – Hz

–10

0

10

20

40

30

50

100k–20

1M 1G100M10M

VGAIN = 1V

0.8V

0.6V

0.4V

0.2V

0V

Figure 2. Frequency Response vs. Gain

The VGA’s low output-referred noise is advantageous in driving high speed differential ADCs. The gain of the postamplifier may be pin selected to 3.5 dB or 15.5 dB to optimize gain range and output noise for 12-bit or 10-bit converter applications. The output may be limited to a user-selected clamping level, preventing input overload to a subsequent ADC. An external resistor adjusts the clamping level.

The AD8332 is available in 28-lead TSSOP and 32-lead LFCSP packages and operates from a single 5 V supply. The total quies-cent power consumption is 250 mW and a power-down pin is provided. The operating temperature range is –40°C to +85°C.

Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.

http://www.analog.com/

AD8332

TABLE OF CONTENTS AD8332—Specifications.................................................................. 3

Absolute Maximum Ratings............................................................ 6

AD8332—Typical Performance Characteristics........................... 7

Test Circuits..................................................................................... 15

Theory of Operation ...................................................................... 16

Overview...................................................................................... 16

Low Noise Amplifier (LNA)...................................................... 16

Variable Gain Amplifier............................................................. 18

Postamplifier ............................................................................... 20

Applications..................................................................................... 21

LNA .............................................................................................. 21

VGA ............................................................................................. 22

Driving ADCs ............................................................................. 23

Overload ...................................................................................... 23

Layout, Grounding, And Bypassing ......................................... 24

Multiple Input Matching ........................................................... 24

Measurement Considerations................................................... 25

Ultrasound TGC Application ................................................... 25

Pin Function Descriptions ............................................................ 29

Pin Configurations ......................................................................... 30

Outline Dimensions ....................................................................... 31

Ordering Guide .......................................................................... 32

REVISION HISTORY

Revision B

5/03—Data Sheet Changed from REV. A to REV. B

Edits to Ordering Guide …………………………………………32

Edits to Ultrasound TGC Application section ……………… … 25

Added Figure 71, Figure 72, and Figure 73………………………26

Updated Outline Dimensions ……………………………………31

2/03—Data Sheet Changed from REV. 0 to REV. A

Edits to Ordering Guide .....................................................................32

Rev. B | Page 2 of 32

AD8332

Rev. B | Page 3 of 32

AD8332—SPECIFICATIONS Table 1. TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RFB = 280 Ω, CSH = 22 pF, f = 10 MHz, RCLMP = ∞, CL = 1 pF, VCM = 2.5 V, –4.5 dB to +43.5 dB gain (HILO = LO), and differential output voltage, unless otherwise specified.

Parameter Conditions Min Typ Max Unit LNA CHARACTERISTICS

Single-Ended Input to Differential Output

19 dB Gain

Input to Output (Single-Ended) 13 dB Input Voltage Range AC-Coupled ±275 mV

RFB = 280 Ω 50 Ω RFB = 412 Ω 75 Ω RFB = 562 Ω 100 Ω RFB = 1.13 kΩ 200 Ω

Input Resistance

RFB = ∞ 6 kΩ Input Capacitance 13 pF Output Impedance Single-Ended, Either Output 5 Ω –3 dB Small Signal Bandwidth VOUT = 0.2 V p-p 130 MHz Slew Rate 650 V/µs Input Voltage Noise RS = 0 Ω, HI or LO Gain,

RFB = ∞, f = 5 MHz 0.74 nV/√Hz

Input Current Noise RFB = ∞, HI or LO Gain, f = 5 MHz 2.5 pA/√Hz Noise Figure f = 10 MHz, LOP Output

Active Termination Match RS = RIN = 50 Ω 3.7 dB Unterminated RS = 50 Ω, RFB = ∞ 2.5 dB

Harmonic Distortion @ LOP1 or LOP2 HD2 –56 dBc HD3

VOUT = 0.5 V p-p, Single-Ended, f = 10 MHz

–70 dBc Output Short-Circuit Current Pins LON, LOP 165 mA

LNA + VGA CHARACTERISTICS –3 dB Small Signal Bandwidth VOUT = 0.2 V p-p 120 MHz –3 dB Large Signal Bandwidth VOUT = 2 V p-p 110 MHz

LO Gain 300 V/µs Slew Rate HI Gain 1200 V/µs

Input Voltage Noise RS = 0 Ω, HI or LO Gain, RFB = ∞, f = 5 MHz

0.82 nV/√Hz

Noise Figure VGAIN = 1.0 V RS = RIN = 50 Ω, f = 10 MHz, Measured

4.15 dB Active Termination Match

RS = RIN = 200 Ω, f = 5 MHz, Simulated

2.0 dB

RS = 50 Ω, RFB = ∞, f = 10 MHz, Measured

2.5 dB Unterminated

RS = 200 Ω, RFB = ∞, f = 5 MHz, Simulated

1.0 dB

VGAIN = 0.5 V, LO Gain 48 nV/√Hz Output-Referred Noise VGAIN = 0.5 V, HI Gain 178 nV/√Hz

Output Impedance, Postamplifier DC to 1 MHz 1 Ω Output Signal Range, Postamplifier RL ≥ 500 Ω,

Unclamped, Either Pin VCM ± 1.125 V

Differential 4.5 V p-p Output Offset Voltage

Differential –50 ±5 +50 mV Common-Mode

VCM = 2.5 V, VGAIN = 0.5 V –125 –25 +75 mV

Output Short-Circuit Current 45 mA

AD8332

Parameter Conditions Min Typ Max Unit Harmonic Distortion VGAIN = 0.5 V, VOUT = 1 V p-p

HD2 –88 dBc HD3

f = 1 MHz –85 dBc

HD2 –68 dBc HD3

f = 10 MHz –65 dBc

Input 1 dB Compression Point VGAIN = 0.25 V, VOUT = 1 V p-p, f = 1 MHz–10 MHz

7 dBm1

VGAIN = 0.72 V, VOUT = 1 V p-p, f = 1 MHz

–80 dBc Two-Tone Intermodulation Distortion (IMD3)

VGAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz

–72 dBc

VGAIN = 0.5 V, VOUT = 1 V p-p, f = 1 MHz

38 dBm Output Third Order Intercept

VGAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz

33 dBm

Channel-to-Channel Crosstalk VGAIN = 0.5 V, VOUT = 1 V p-p, f = 1 MHz

–84 dB

Overload Recovery VGAIN = 1.0 V, VIN = 50 mV p-p/1 V p-p, f = 10 MHz

5 ns

Group Delay Variation 5 MHz < f < 50 MHz, Full Gain Range

±2 ns

ACCURACY 0.05 V < VGAIN < 0.10 V –10 0.5 +2 dB 0.10 V < VGAIN < 0.95 V –1 ±0.3 +1 dB

Absolute Gain Error2

0.95 V < VGAIN < 1.0 V –2 –1 +1 dB Gain Law Conformance3 0.1 V < VGAIN < 0.95 V ±0.2 dB Channel-to-Channel Gain Matching 0.1 V < VGAIN < 0.95 V ±0.1 dB

GAIN CONTROL INTERFACE (Pin GAIN)

Gain Scaling Factor 0.10 V < VGAIN < 0.95 V 50 dB/V LO Gain –4.5 to +43.5 dB Gain Range HI Gain +7.5 to +55.5 dB

Input Voltage (VGAIN) Range 0 to 1.0 V Input Impedance 10 MΩ Response Time 48 dB Gain Change to

90% Full Scale 750 ns

COMMON-MODE INTERFACE (Pin VCM1, VCM2)

Input Resistance Current Limited to ±1 mA 30 Ω Output CM Offset Voltage VCM = 2.5 V –125 –25 +75 mV Voltage Range

VOUT = 2.0 V p–p 1.5 to 3.5 V

1 All dBm values are referred to 50 Ω, unless otherwise noted. 2 Conformance to theoretical gain expression (see Equation 1). 3 Conformance to best fit dB linear curve.

Rev. B | Page 4 of 32

AD8332

Parameter Conditions Min Typ Max Unit ENABLE INTERFACE (AR Package: Pin ENB; AC Package: Pins ENBL, ENBV)

Logic Level to Enable Power 2.25 5 V Logic Level to Disable Power 0 1.0 V

Pin ENB 25 kΩ Pin ENBL 40 kΩ

Input Resistance

Pin ENBV 70 kΩ VINH = 30 mV p–p 300 µs Power-Up Response Time VINH = 150 mV p–p 4 ms

HILO GAIN RANGE INTERFACE (Pin HILO)

Logic Level to Select HI Gain Range 2.25 5 V Logic Level to Select LO Gain Range 0 1.0 V Input Resistance 50 kΩ

OUTPUT CLAMP INTERFACE (Pin RCLMP; HI or LO Gain)

Accuracy HILO = LO RCLMP = 2.74 kΩ, VOUT = 1 V p–p (Clamped) ±50 mV HILO = HI RCLMP = 2.21 kΩ, VOUT = 1 V p–p (Clamped) ±75 mV

MODE INTERFACE (Pin MODE, AC Package Only)

Logic Level for Positive Gain Slope 2.25 5 V Logic Level for Negative Gain Slope 0 1.0 V Input Resistance 200 kΩ

POWER SUPPLY (Pins VPS1, VPS2, VPSV)

Supply Voltage 4.5 5.0 5.5 V Quiescent Current per Channel 25 mA Power Dissipation Both Channels Active, No Signal 250 mW Disable Current 300 600 µA PSRR VGAIN = 0, f = 100 kHz –68 dB

Rev. B | Page 5 of 32

AD8332

Rev. B | Page 6 of 32

ABSOLUTE MAXIMUM RATINGS Table 2. Absolute Maximum Ratings for the AD8332

Parameter Rating Voltage

Supply Voltage (VPS1, VPS2, VPSV) 5.5 V Input Voltage (INH1, INH2) VS + 200 mV ENB, ENBL, ENBV, HILO Voltage VS + 200 mV GAIN Voltage 2.5 V

Power Dissipation AR Package1 0.96 W AC Package 1.97 W

Temperature Operating Temperature –40°C to +85°C Storage Temperature –65°C to +150°C Lead Temperature (Soldering 60 sec) 300°C

θJA AR Package1 68°C/W AC Package2 33°C/W

1 Four-Layer JEDEC Board (2S2P). 2 Exposed pad soldered to board, nine thermal vias in pad — JEDEC4-Layer Board J-STD-51-9.

Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

AD8332

AD8332—TYPICAL PERFORMANCE CHARACTERISTICS Table 3. TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RFB = 280 Ω, CSH = 22 pF, f = 10 MHz, RCLMP = ∞, CL = 1 pF, VCM = 2.5 V, –4.5 dB to +43.5 dB gain (HILO = LO), and differential signal voltage, unless otherwise specified.

0 0.2VGAIN – V

0.60.4 1.00.8 1.1

GA

IN–

dB

40

50

30

10

0

20

–10

60

HILO = HI

MODE = HI(AC PACKAGEONLY)

MODE = LO

HILO = LO

Figure 3. Gain vs. VGAIN and MODE (MODE Available on AC Package)

GA

IN E

RR

OR

– dB 0.5

1.0

2.0

1.5

0 0.2VGAIN – V

0.60.4

0

–1.0

–1.5

–0.5

–2.01.00.8 1.1

–40°C

+85°C

+25°C

Figure 4. Absolute Gain Error vs. VGAIN at Three Temperatures

GA

IN E

RR

OR

– dB 0.5

1.0

2.0

1.5

0 0.2VGAIN – V

0.60.4

0

–1.0

–1.5

–0.5

–2.01.00.8 1.1

1MHz10MHz

70MHz30MHz

Figure 5. Absolute Gain Error vs. VGAIN at Various Frequencies

0

% O

F U

NIT

S

10

20

30

40

50

–0.1GAIN ERROR – dB

0.40–0.3 –0.2 0.1–0.4–0.5 0.30.2 0.5

SAMPLE SIZE = 80 UNITSVGAIN = 0.5V

Figure 6. Gain Error Histogram

% O

F U

NIT

S

0.01

CHANNEL-TO-CHANNEL GAIN MATCH – dB

0

0.15

0.13

0.11

0.09

0.07

0.05

0.03

–0.0

1

0.21

0.19

0.17

–0.1

7–0

.15

–0.1

3–0

.11

–0.0

9–0

.07

–0.0

5–0

.03

5

25

20

15

10

0

5

25

20

15

10

VGAIN = 0.7V

SAMPLE SIZE = 50 UNITSVGAIN = 0.2V

Figure 7. Gain Match Histogram for VGAIN = 0.2 V and 0.7 V

GA

IN–

dB

–10

0

10

20

40

30

50

100k–20

FREQUENCY – Hz1M 1G100M10M

VGAIN = 1V

0.8V

0.6V

0.4V

0.2V

0V

Figure 8. Frequency Response for Various Values of VGAIN

Rev. B | Page 7 of 32

AD8332

FREQUENCY – Hz

GA

IN–

dB

0

10

–10

20

40

30

50

60

100k 1G100M10M

VGAIN = 1V

0.9V0.7V

0.1V

0.5V

0.3V

0V

Figure 9. Frequency Response for Various Values of VGAIN, HILO = HI

FREQUENCY – Hz

GA

IN–

dB

–10

0

10

20

30

–40

–30

–20

1M 1G100k 100M10M

RIN = RS = 1kΩ

RIN = RS = 500Ω

RIN = RS = 200Ω

VGAIN = 0.5V RIN = RS = 50Ω

Figure 10. Frequency Response for Various Matched Source Impedances

FREQUENCY – Hz

GA

IN–

dB

–10

0

10

20

–40

30

–30

–20

1M 1G100k 100M10M

VGAIN = 0.5VRFB = ∞

Figure 11. Frequency Response, Unterminated, RS = 50 Ω

FREQUENCY – Hz

CR

OSS

TALK

– dB

–70

0

–60

–50

–30

–40

–20

1M100k 100M10M

–10

–90

–800.7V 0.4V

0.9V

VGAIN = 1V

0.5V

VOUT = 1 V p-p

Figure 12. Channel-to-Channel Crosstalk vs. Frequency for Various Values of VGAIN

FREQUENCY – Hz

GR

OU

P D

ELA

Y–

ns

1M100k 100M10M0

50

45

40

35

30

25

20

15

10

5

Figure 13. Group Delay vs. Frequency

VGAIN – V

OFF

SET

VOLT

AG

E–

mV

–20

–15

–10

–5

0

25

–25

10

20

5

15

1.10.40.20 0.30.1 0.90.70.5 0.80.6 1.0

T = +25°C

T = –40°C

T = –40°C

T = +85°C

Figure 14. Differential Output Offset Voltage vs. VGAIN at Three Temperatures

Rev. B | Page 8 of 32

AD8332

% T

OTA

L

50.5GAIN SCALING FACTOR

050.449.6 49.7 49.8 49.9 50.0 50.1 50.2 50.3

5

25

20

15

10

35SAMPLE SIZE = 1000.2V < VGAIN < 0.7V

30

Figure 15. Gain Scaling Factor Histogram

100

100k 1M

10

1

0.110M 100M

FREQUENCY – Hz

OU

TPU

T IM

PED

AN

CE

–Ω

SINGLE ENDED, PIN VOH OR VOLRL = ∞

Figure 16. Output Impedance vs. Frequency

FREQUENCY – Hz

INPU

T IM

PED

AN

CE

–Ω

100

1k

10

10k

1M100k 100M10M

RFB = ∞, CSH = 0pF

RFB = 270Ω, CSH = 22pFRFB = 412Ω, CSH = 12pF

RFB = 549Ω, CSH = 8.2pF

RFB = 3.01kΩ, CSH = 0pF

RFB = 6.65kΩ, CSH = 0pF

RFB = 1.1kΩ, CSH = 1.2pF

Figure 17. LNA Input Impedance vs. Frequency for Various Values of RFB and CSH

0Ω 17Ω

25j

–25j

50j

–50j

100j

–100j

f = 100kHz

RIN = 50ΩRFB = 270Ω

RIN = 75Ω,RFB = 412Ω

RIN = 100Ω,RFB = 549Ω

,

RIN = 200Ω,RFB = 1.1kΩ

RIN = 6kΩ,RFB = ∞

Figure 18. Smith Chart, S11 vs. Frequency, 0.1 MHz to 200 MHz for Various Values of RFB

1GFREQUENCY – Hz

10M

GA

IN–

dB

100k

–10

–5

0

5

20

10

15

100M1M–20

–15

RIN = 50Ω, 75ΩAND 100Ω

RIN = 200Ω

RIN = 200ΩRIN = 500Ω

RIN = 1kΩ

Figure 19. LNA Frequency Response, Single-Ended, for Various Values of RIN

1GFREQUENCY – Hz

10M

GA

IN–

dB

100k

–10

–5

0

5

20

10

15

100M1M–20

–15

RFB = ∞

Figure 20. LNA Frequency Response, Unterminated, Single-Ended

Rev. B | Page 9 of 32

AD8332

500

0 0.4VGAIN – V

1.00.6

300

0

100

400

200

0.2 0.8

OU

TPU

T R

EFER

RED

NO

ISE

– nV

/ H

z

HILO = HI

f = 10MHz

HILO = LO

Figure 21. Output-Referred Noise vs. VGAIN

1M 10M0

100M100kFREQUENCY – Hz

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

INPU

T N

OIS

E–

nV/

Hz

RS = 0, RFB = ∞,VGAIN = 1VHILO = LO OR HI

Figure 22. Short-Circuit Input-Referred Noise vs. Frequency

1

0 0.4VGAIN – V

1.00.60.1

100

10

0.2 0.8

INPU

T N

OIS

E–

nV/

Hz

RS = 0, RFB = ∞,HILO = LO OR HI, f = 10MHz

Figure 23. Short-Circuit Input-Referred Noise vs. VGAIN

90TEMPERATURE – °C

10–30–50 –10 7050300.50

1.00

0.95

0.90

0.85

0.80

0.75

0.70

0.65

0.60

0.55

INPU

T N

OIS

E–

n V/

Hz

RS = 0, RFB = ∞,VGAIN = 1V, f = 10MHz

Figure 24. Short-Circuit Input-Referred Noise vs. Temperature

1 10

1.0

0.1100 1k

SOURCE RESISTANCE – Ω

10

INPU

T N

OIS

E–

nV/

Hz

RS = THERMAL NOISE ALONE

f = 5MHz, RFB = ∞, VGAIN = 1V

Figure 25. Input-Referred Noise vs. RS

NO

ISE

F IG

UR

E–

dB

5

6

7

4

2

1

3

010050 1k

75Ω

200Ω

SOURCE RESISTANCE – Ω

RIN = 50Ω

RFB = ∞

INCLUDES NOISE OF VGA

SIMULATION

100Ω

Figure 26. Noise Figure vs. RS for Various Values of RIN

Rev. B | Page 10 of 32

AD8332

NO

ISE

FIG

UR

E–

dB

40

50

0 0.2VGAIN – V

0.60.4

30

10

0

20

5

1.00.8 1.1

35

45

25

15

0.1 0.50.3 0.90.7

HILO = LO, RIN = 50Ω

HILO = LO, RFB = ∞

HILO = HI, RFB = ∞

HILO = HI, RIN = 50Ω

f = 10MHz, RS = 50Ω

Figure 27. Noise Figure vs. VGAIN

NO

ISE

FIG

UR

E–

dB

30

10 20GAIN – dB

3525

20

0

5

5545 60

25

15

10

15 30 5040

HILO = HI, RIN = 50Ω

HILO = HI, RFB = ∞

HILO = LO, RIN = 50Ω

HILO = LO, RFB = ∞

f = 10MHz, RS = 50Ω

Figure 28. Noise Figure vs. Gain

FREQUENCY – Hz

HA

RM

ON

IC D

ISTO

RTI

ON

– dB

c

–70

–60

–50

–40

–100

–90

–80

100M1M 10M

–30

–20

–10

0

HILO = LO,HD2

HILO = HI,HD2

HILO = HI,HD3

HILO = LO,HD3

G = 30dBVOUT = 1V p-p

Figure 29. Harmonic Distortion vs. Frequency

HA

RM

ON

IC D

ISTO

RTI

ON

– dB

c

–70

–60

–50

–40

–100

–90

–80

200 8000 600400 1.0k 2.0k1.8k1.6k1.4k1.2k

–30

RLOAD – Ω

HILO = LO,HD3

HILO = LO,HD2

f = 10MHzVOUT = 1V p-p

HILO = HI,HD2

HILO = HI,HD3

Figure 30. Harmonic Distortion vs. RLOAD

HA

RM

ON

IC D

ISTO

RTI

ON

– dB

c–70

–60

–50

–40

–100

–90

–80

10 40 500 3020CLOAD – pF

HILO = HI,HD2

HILO = HI,HD3 HILO = LO,

HD2

HILO = LO,HD3

f = 10MHzVOUT = 1V p-p

Figure 31. Harmonic Distortion vs. CLOAD

HA

RM

ON

IC D

ISTO

RTI

ON

– dB

c

–70

–60

–50

–40

–100

–90

–80

1 40 32

HILO = HI,HD2

f = 10MHzGAIN = 30 dB

VOUT – V p-p

HILO = LO,HD3

HILO = HI,HD3

HILO = LO,HD2

Figure 32. Harmonic Distortion vs. Differential Output Voltage

Rev. B | Page 11 of 32

AD8332

0.4VGAIN – V

0.2

DIS

TOR

TIO

N–

dBc

0

–100

–80

–60

–40

–20

0

0.30.1–120

0.90.70.5 0.80.6 1.0

HILO = HI,HD2

f = 1MHzVOUT = 1V p-p

HILO = LO,HD3

INPUT RANGELIMITED WHENHILO = LO

HILO = LO,HD2

HILO = HI,HD3

Figure 33. Harmonic Distortion vs. VGAIN, f = 1 MHz

DIS

TOR

TIO

N–

dBc

VGAIN – V0.40.20

–100

–80

–60

–40

–20

0

0.30.1–120

0.90.70.5 0.80.6 1.0

HILO = HI,HD3

HILO = HI,HD2

f = 10MHzVOUT = 1V p-p

HILO = LO,HD3

INPUT RANGELIMITED WHENHILO = LO

HILO = LO,HD2

Figure 34. Harmonic Distortion vs. VGAIN, f = 10 MHz

0.40.2

INPU

T PO

WER

– dB

m

0 0.30.1–30

0.90.70.5 0.80.6 1.0

5

0

–5

–10

–15

–20

–25

10

VGAIN – V

f = 10MHz

HILO = HI HILO = LO

Figure 35. Input 1 dB Compression vs. VGAIN

100MFREQUENCY – Hz

1M

IMD

3–

dBc

10M

–10

–90

–80

–70

–60

–30

–50

–40

–20

0VOUT = 1V p-p COMPOSITE (f1 + f2)G = 30dB

Figure 36. IMD3 vs. Frequency

OU

TPU

T IP

3–

dBm

VGAIN – V

15

20

25

30

0

5

10

0.1 0.40 0.30.2 1.00.90.80.70.60.5

40

35

HILO = HI,1MHz

HILO = HI,10MHz

HILO = LO,10MHz

HILO = LO,1MHz

VOUT = 1V p-p COMPOSITE (f1 + f2)

Figure 37. Output Third Order Intercept vs. VGAIN

100

90

10

0

2mV

50mV 10ns

Figure 38. Small Signal Pulse Response, G = 30 dB, Top: Input, Bottom: Output Voltage, HILO = HI or LO

Rev. B | Page 12 of 32

AD8332

100

90

10

0

20mV

500mV 10ns

Figure 39. Large Signal Pulse Response, G = 30 dB, HILO = HI or LO, Top: Input, Bottom: Output Voltage

10TIME – ns

–10–30 0–20–2

604020 5030–40

1

0

–1

2

8070

V OU

T–

V

INPUT IS NOT TO SCALE

INPUT

CL = 0pF

G = 30dB CL = 50pF

Figure 40. Large Signal Pulse Response for Various Capacitive Loads, CL = 0 pF, 10 pF, 20 pF, 50 pF

400ns200mV

500mV

Figure 41. Pin GAIN Transient Response, Top: VGAIN, Bottom: Output Voltage

V OU

T–

V p-

p

0 10 3020 5040

1

4

3

2

0

5

RCLMP – kΩ

HILO = LO

HILO = HI

Figure 42. Clamp Level vs. RCLMP

30TIME – ns

10

V OU

T–

V

–10 200–4

6040 50

1

0

–1

2

4

3

–2

–3

G = 40dB

RCLMP = 48.1kΩ RCLMP = 16.5kΩ

RCLMP = 7.15kΩ RCLMP = 2.67kΩ

Figure 43. Clamp Level Pulse Response

100

90

10

0

100ns

200mV

Figure 44. LNA Overdrive Recovery, VINH 0.05 V p-p to 1 V p-p Burst, VGAIN = 0.27 V, VGA Output Shown

Rev. B | Page 13 of 32

AD8332

Rev. B | Page 14 of 32

100

90

10

0

100ns

50mV

Figure 45. VGA Overdrive Recovery, VINH 4 mV p-p to 70 mV p-p Burst, VGAIN = 1 V, VGA Output Shown Attenuated 24 dB

100

90

10

0

100ns

50mV

Figure 46. VGA Overdrive Recovery, VINH 4 mV p-p to 275 mV p-p Burst, VGAIN = 1 V, VGA Output Shown Attenuated 24 dB

1ms200mV

2V

Figure 47. Enable Response, Top: VENB, Bottom: VOUT, VINH = 30 mV p-p

1V

2V

1ms

Figure 48. Enable Response, Large Signal, Top: VENB, Bottom: VOUT, VINH = 150 mV p-p

FREQUENCY – Hz

PSR

R–

dB

1M100k 100M10M–80

0

–10

–20

–30

–40

–50

–60

–70

VPS1, VGAIN = 0.5V

VPS1, VGAIN = 0V

VPSV, VGAIN = 0.5V

Figure 49. PSRR vs. Frequency (No Bypass Capacitor)

40TEMPERATURE – °C

0

QU

IESC

ENT

SUPP

LY C

UR

REN

T–

mA

–40

40

45

50

55

60

20–2030

35

1008060

VGAIN = 0.5V

Figure 50. Quiescent Supply Current vs. Temperature

AD8332

Rev. B | Page 15 of 32

TEST CIRCUITS

1:1

NETWORK ANALYZER

LMD

INH

DUT

1.8nF

22pF

FB*75Ω @

100MHz

50Ω

0.1µF

0.1µF

0.1µF0.1µF

50Ω

28Ω

28Ω

237Ω

237Ω270Ω

OUT IN

*FERRITE BEAD Figure 51. Used for Gain and Bandwidth Measurements

1:1LMD

INH

DUT

1.8nF

22pF

OSCILLOSCOPE

*FERRITE BEAD

FB*75Ω @

100MHz0.1µF

0.1µF28Ω

50Ω

50Ω

IN28Ω

237Ω

237Ω0.1µF

0.1µF270Ω

Figure 52. Used for Transient Measurements

1:1LMD

INH

DUT

SPECTRUMANALYZER

22pF

A BG

*FERRITE BEAD

FB*75Ω @

100MHz0.1µF

0.1µF

0.1µF

0.1µF

50Ω

IN49Ω

1Ω50Ω

Figure 53. Used for Noise Measurements

AD8332

THEORY OF OPERATION Overview

The AD8332 is a dual-channel VGA. Each channel contains an LNA that provides user-adjustable input impedance termina-tion, a differential X-AMP VGA, and a programmable gain postamplifier with adjustable output voltage limiting. Figure 54 shows a simplified block diagram.

When MODE is set high, (AC package only):

( ) ( ) ( )3=,545+×50–=)( LOHILOdB.VVdBdBGAIN GAIN or

( ) ( ) ( )4=,557+×50–=)( HIHILOdB.VVdBdBGAIN GAIN

VOL

VOHLNA

CLAMP*

–

+INH

LMD

LOP

LON

HILOVCM

PREAMPLIFIER19dB

X-AMP VGA POSTAMP

[(–48 to 0) + 21] dB 3.5dB/15.5dB

GAININTERFACE*

GAIN

BIAS ANDINTERPOLATOR*

VIN

VIP

*SHARED BETWEEN CHANNELS

RCLMPBIAS(VMID)

VMID

The LNA converts a single-ended input to a differential output with a voltage gain of 19 dB. When only one output is used, the gain is 13 dB. The inverting output is used for active input impedance termination. Each of the LNA outputs is capacitively coupled to a VGA input. The VGA consists of an attenuator with a range of 48 dB followed by an amplifier with 21 dB of gain, for a net gain range of –27 dB to +21 dB. The X-AMP gain-interpolation technique results in low gain error and uniform bandwidth, and differential signal paths minimize distortion.

The final stage is a logic programmable amplifier with gains of 3.5 dB or 15.5 dB. The LO and HI gain modes are optimized for 12-bit and 10-bit A/D converter applications, in terms of output-referred noise and absolute gain range. Output voltage limiting may be programmed by the user.

Figure 54. Simplified Block Diagram

The linear-in-dB gain control interface is trimmed for slope and absolute accuracy. The overall gain range of the AD8332 is 48 dB, extending from –4.5 dB to +43.5 dB or +7.5 dB to +55.5 dB, depending on the setting of the HILO pin. The slope of the gain control interface is 50 dB/V, and the gain control range is 40 mV to 1 V, leading to the following expressions for gain.

Low Noise Amplifier (LNA)

AD8332 performance relies on a proprietary ultralow noise preamplifier at the beginning of the signal chain, which mini-mizes the noise contribution in the following VGA. Active impedance control optimizes noise performance for applica-tions that benefit from input matching.

( ) ( ) ( )1=,56×50=)( LOHILOdB.–VVdB dBGAIN GAIN or

( ) ( ) (2=,55+50=)( HOHILOdB.V×VdB dBGAIN GAIN ) The gain characteristics are shown in Figure 55.

A simplified schematic of the LNA is shown in Figure 56. INH is capacitively coupled to the source. An on-chip bias generator centers the output dc levels at 2.5 V and the input voltages at 3.25 V. A capacitor CLMD of the same value as the input coupling capacitor CINH is connected from the LMD pin to ground.

GA

IN–

dB

40

50

0 0.2VGAIN – V

0.60.4

30

10

0

20

–101.00.8 1.1

60

HILO = LO

HILO = HI

MODE = HI(AC PACKAGE ONLY)

MODE = LO

VPOS

INH

LOP

LMD

LON

Q1 Q2

I0

I0

I0

I0

CLMD

CFB RFB

CINH

RS

CSH

Figure 55. Gain Control Characteristics

Figure 56. Simplified LNA Schematic

Rev. B | Page 16 of 32

AD8332 The LNA supports differential output voltages as high as 5 V p-p with positive and negative excursions of ±1.25 V, about a com-mon-mode voltage of 2.5 V. Since the differential gain magnitude is 9, the maximum input signal before saturation is ± 275 mV or 550 mV p-p. Overload protection ensures quick recovery time from large input voltages. Since the inputs are capacitively cou-pled to a bias voltage near midsupply, very large inputs can be handled without interacting with the ESD protection.

Low value feedback resistors and the current-driving capability of the output stage allow the LNA to achieve a low input-referred voltage noise of 0.74 nV/√Hz. This is achieved with a modest current consumption of 10 mA per channel (50 mW). On-chip resistor matching results in precise gains of 4.5 per side (9 differ-ential), critical for accurate impedance control. The use of a fully differential topology and negative feedback minimizes distortion. Low HD2 is particularly important in second harmonic ultra-sound imaging applications. Differential signaling enables smaller swings at each output, further reducing third order distortion.

ACTIVE IMPEDANCE MATCHING

The AD8332 LNA supports active impedance matching through an external shunt feedback resistor from Pin LON to Pin INH. The input resistance RIN is given by Equation 5, where A is the single-ended gain of 4.5, and 6 kΩ is the unterminated input impedance.

( )5+Ω33

×Ω6=Ω6

+1=

FB

FBFBIN Rk

Rkk

AR

R

CFB is needed in series with RFB, since the dc levels at Pins LON and INH are unequal. Expressions for choosing RFB in terms of RIN and for choosing CFB are found in the Applications section. CSH and the ferrite bead enhance stability at higher frequencies where the loop gain declines and prevents peaking. Frequency response plots of the LNA are shown in Figure 19 and Figure 20. The bandwidth is approximately 130 MHz for matched input impedances of 50 Ω to 200 Ω and declines at higher source impedances. The unterminated bandwidth (RFB = ∞) is approximately 80 MHz.

Each output can drive external loads as low as 100 Ω in addition to the 100 Ω input impedance of the VGA (200 Ω differential). Capacitive loading up to 10 pF is permissible. All loads should be ac-coupled. Typically, Pin LOP output is used as a single-ended driver for auxiliary circuits, such as those used for Doppler mode ultrasound imaging, and Pin LON drives RFB. Alternatively, a differential external circuit can be driven from the two outputs, in addition to the active feedback termination. In both cases, important stability considerations discussed in the Applications section should be carefully observed.

The impedance at each LNA output is 5 Ω. A slight reduction in open-circuit gain from 13.1 dB to 12.7 dB results when driving

the VGA, and to 12.3 dB with an additional 100 Ω load at the output. The differential gain of the LNA is 6 dB higher. If the load is less than 200 Ω on one side, an equal load should be used on the opposite output.

LNA NOISE

The input-referred voltage noise of the AD8332 sets an impor-tant limit on system performance. The short-circuit input volt-age noise of the LNA is 0.74 nV/√Hz or 0.82 nV/√Hz (at maxi-mum gain), including the VGA noise. The open-circuit current noise is 2.5 pA/√Hz. These measurements, taken without a feedback resistor, provide the basis for simulating the input noise and noise figure performance of the configurations in Figure 57, which is shown in Figure 58 and Figure 59. Untermi-nated (RFB = ∞) operation exhibits the lowest equivalent input noise and noise figure. Noise figure versus source resistance plots are shown in Figure 58, rising at low RS, where the LNA voltage noise is large compared to the source noise, and again at high RS due to current noise. The VGA’s input-referred voltage noise of 2.7 nv/√Hz is included in all of the curves.

VOUT

UNTERMINATED

+

–VIN

RINRS

VOUT

RESISTIVE TERMINATION

+

–VIN

RINRS

RS

VOUT

ACTIVE IMPEDANCE MATCH

+

–VIN

RIN RFB

RFB1 + 4.5

RS

RIN =

Figure 57. Input Configurations

Rev. B | Page 17 of 32

AD8332

NO

ISE

F IG

UR

E–

dB

5

6

7

4

2

1

3

010050 1k

RS – Ω

ACTIVE IMPEDANCE MATCH

RESISTIVE TERMINATION(RS = RIN)

UNTERMINATED

SIMULATION

INCLUDES NOISE OF VGA

Figure 58. Noise Figure vs. RS for Resistive, Active Matched and Unterminated Inputs

NO

ISE

FIG

UR

E–

dB

5

6

7

4

2

1

3

010050 1k

RIN = 50Ω

70Ω

RFB = ∞

RS – Ω

200Ω

INCLUDES NOISE OF VGA

100Ω

SIMULATION

Figure 59. Noise Figure vs. RS for Various Fixed Values of RIN, Actively Matched

The primary purpose of input impedance matching is to improve the system transient response. With resistive termina-tion, the input noise increases due to the thermal noise of the matching resistor and the increased contribution of the LNA’s input voltage noise generator. With active impedance matching, however, the contributions of both are smaller than they would be for resistive termination by a factor of 1/(1 + LNA Gain). Figure 58 shows their relative noise figure (NF) performance. In this graph, the input impedance has been swept with RS to pre-serve the match at each point. The noise figures for a source impedance of 50 Ω are 7.1 dB, 4.1 dB, and 2.5 dB, respectively, for the resistive, active, and unterminated configurations. The noise figures for 200 Ω are 4.6 dB, 2.0 dB, and 1.0 dB, respectively.

Figure 59 is a plot of the NF versus RS for various values of RIN, which is helpful for design purposes. The plateau in the NF for actively matched inputs mitigates source impedance variations. For comparison purposes, a preamp with a gain of 19 dB and noise spectral density of a 1.0 nV/√Hz, combined with a VGA with 3.75 nV/√Hz, would yield a noise figure degradation of

approximately 1.5 dB (for most input impedances), significantly worse than the AD8332 performance.

The equivalent input noise of the LNA is the same for single-ended and differential output applications. The LNA noise figure improves to 3.5 dB at 50 Ω without VGA noise, but this is exclusive of noise contributions from other external circuits connected to LOP. A series output resistor is usually recom-mended for stability purposes, when driving external circuits on a separate board (see the Applications section). In low noise applications, a ferrite bead is even more desirable.

Variable Gain Amplifier

The differential X-AMP VGA provides precise input attenua-tion and interpolation. It has a low input-referred noise of 2.7 nV/√Hz and excellent gain linearity. A simplified block diagram is shown in Figure 60.

GAIN INTERPOLATOR(BOTH CHANNELS)

POSTAMP+

–

VIP

GAIN

R

6dB

2R48dB

POSTAMP

VIN

gm

Figure 60. Simplified VGA Schematic

X-AMP VGA

The input of the VGA is a differential R-2R ladder attenuator network, with 6 dB steps per stage and a net input impedance of 200 Ω differential. The ladder is driven by a fully differential input signal from the LNA and is not intended for single-ended operation. LNA outputs are ac-coupled to reduce offset and isolate their common-mode voltage. The VGA inputs are biased through the ladder’s center tap connection to VCM, which is typically set to 2.5 V and is bypassed externally to provide a clean ac ground.

The signal level at successive stages in the input attenuator falls from 0 dB to –48 dB, in 6 dB steps. The input stages of the X-AMP are distributed along the ladder, and a biasing interpolator, controlled by the gain interface, determines the input tap point. With overlapping bias currents, signals from successive taps merge to provide a smooth attenuation range from 0 dB to –48 dB. This circuit technique results in excellent, linear-in-dB gain law confor-mance and low distortion levels and deviates ±0.2 dB or less from ideal. The gain slope is monotonic with respect to the control volt-age and is stable with variations in process, temperature, and supply.

Rev. B | Page 18 of 32

AD8332 The X-AMP inputs are part of a gain-of-12 feedback amplifier, which completes the VGA. Its bandwidth is 150 MHz. The input stage is designed to reduce feedthrough to the output and ensure excellent frequency response uniformity across gain setting (see Figure 8 and Figure 9).

The output-referred noise is flat over most of the gain range, since it is dominated by the fixed output-referred noise of the VGA. Values are 48 nV/√Hz in LO gain mode and 178 nV/√Hz in HI gain mode. At the high end of the gain control range, the noise of the LNA and source prevail. The input-referred noise reaches its minimum value near the maximum gain control voltage, where the input-referred contribution of the VGA becomes very small.

GAIN CONTROL

Position along the VGA attenuator is controlled by a single-ended analog control voltage, VGAIN, with an input range of 40 mV to 1.0 V. The gain control scaling is trimmed to a slope of 50 dB/V (20 mV/dB). Values of VGAIN beyond the control range saturate to minimum or maximum gain values. Both channels of the AD8332 are controlled from a single gain interface to preserve matching. The gain of the AD8332 can be calculated using the expressions shown previously in Equations 1 and 2.

At lower gains, the input-referred noise, and thus noise figure, increases as the gain decreases. The instantaneous dynamic range of the system is not lost, however, since the input capacity increases with it. The contribution of the ADC noise floor has the same dependence as well. The important relationship is the magnitude of the VGA output noise floor relative to that of the ADC.

With its low output-referred noise levels, the AD8332 is well suited as a driver for modern ADCs. The converter noise floor drops 12 dB for every 2 bits of resolution and drops at lower input full-scale voltages and higher sampling rates. ADC quan-tization noise is discussed in the Applications section.

Gain accuracy for the AD8332 is very good since both the scaling factor and absolute gain are factory trimmed. The overall accu-racy relative to the theoretical gain expression is ±1 dB for varia-tions in temperature, process, supply voltage, interpolator gain ripple, trim errors, and tester limits. The gain error relative to a best-fit line for a given set of conditions is typically ±0.2 dB. Gain matching between channels is better than 0.1 dB (see Figure 7, which shows gain errors in the center of the control range). When VGAIN < 0.1 or > 0.95, gain errors are slightly greater.

The preceding noise performance discussion applies to a differ-ential VGA output signal. Although the LNA noise performance is the same in single-ended and differential applications, the VGA performance is not. The noise of the VGA is significantly higher in single-ended usage, since the contribution of its bias noise is designed to cancel in the differential signal. A trans-former can be used with single-ended applications when low noise is desired.

An inverted gain feature, illustrated in Figure 55, is available in the 32-lead AC package. The gain drops with a slope of –50 dB/V across the gain control range from maximum to minimum gain. This slope is useful in applications, such as automatic gain control, where the control voltage is made inversely proportional to the measured output signal amplitude. The inverse gain mode is selected by setting the MODE pin HI.

Gain control noise is an additional source of concern in very low noise applications. Thermal noise in the gain control inter-face can modulate the gain of the AD8332, producing noise-like fluctuations at the output. The gain control response time of the AD8332 is less than

750 ns to settle within 10% of the final value for a change from minimum to maximum gain. This noise is proportional to the output signal level and usually

only evident when a large signal is present. Its effect is observ-able only in LO gain mode, where the noise floor is substantially lower. The gain interface includes an on-chip noise filter, which reduces this effect significantly at frequencies above 5 MHz. Care should be taken to minimize noise at the GAIN input. An external RC filter may be used to remove VGAIN source noise. The filter bandwidth should be sufficient to accommodate the desired control bandwidth.

VGA NOISE

In a typical application, the AD8332 serves as a bridge between a wide dynamic range input signal and an ADC. While the input-referred noise of the LNA limits the minimum resolvable input signal, the output-referred noise, which depends primarily on the VGA, limits the maximum instantaneous dynamic range that can be processed at any one particular gain control voltage. This limit is set in conjunction with the quantization noise floor of the ADC.

COMMON-MODE BIASING

An internal bias network connected to a midsupply voltage establishes common-mode voltages in the VGA and postamp. An externally bypassed buffer maintains the voltage. The bypass capacitors form an important ac ground connection, since the VCM network makes a number of important connections in-ternally, including the center tap of the VGA’s differential input attenuator, the feedback network of the VGA’s fixed gain ampli-

Output and input-referred noise as a function of VGAIN are plot-ted in Figure 21 and Figure 23 for the short-circuited input con-dition. The input noise voltage is simply equal to the output noise divided by the measured gain at each point in the control range.

Rev. B | Page 19 of 32

AD8332

Rev. B | Page 20 of 32

fier, and the feedback network of the postamplifier in both gain settings. For best results, use a 1 nF and a 0.1 µF capacitor in parallel, with the 1 nF nearest to the AD8332. Separate VCM pins are provided for each channel. As an added feature, the AD8332’s VCM pins can be overridden with an external voltage source to define a common-mode voltage other than that of midsupply. A 1.5 V common-mode level, for example, can be set for a dc-coupled connection to a 3 V ADC.

Although the quantization noise floor of an ADC depends on a number of factors, the 48 nV/√Hz and 178 nV/√Hz levels of the AD8332 are well suited to the average requirements of most 12-bit and 10-bit converters, respectively. An additional tech-nique, described in the Applications section, can extend the noise floor even lower for possible use with 14-bit ADCs.

OUTPUT CLAMPING

Postamplifier Outputs are internally limited to a level of 4.5 V p-p differential, when operating at a 2.5 V common-mode voltage. The postamp implements an optional output clamp engaged through a resis-tor from RCLMP to ground. Table 5 shows a list of recommended resistor values.

The final stage of the AD8332 has a selectable gain of 3.5 dB or 15.5 dB, set by the logic Pin HILO. These correspond to linear gains of 1.5 or 6. A simplified block diagram of the postampli-fier is shown in Figure 61.

Output clamping can be used for ADC input overload protec-tion, if needed, or postamp overload protection when operating from a lower common-mode level, such as 1.5 V. The user should be aware that distortion products increase as output levels approach the clamping levels and should adjust the clamp resistor accordingly. Also, see the Applications section.

Separate feedback attenuators implement the two gain settings. These are selected in conjunction with an appropriately scaled input stage to maintain a constant 3 dB bandwidth between the two gain modes (~150 MHz). The slew rate is 1200 V/µs in HI gain mode and 300 V/µs in LO gain mode. The feedback net-works for HI and LO gain modes are factory trimmed to adjust the absolute gains of each channel. The accuracy of the clamping levels is approximately ±5% in LO

or HI mode. Figure 62 illustrates the output characteristics for a few values of RCLMP. NOISE

–3 –2

VINH – V

V OH

, VO

L–

V

0–1

0.5

21 3

1.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

0

5.0

8.8kΩ

3.5kΩ

RCLMP = ∞

RCLMP = 1.86kΩ

The topology of the postamplifier provides constant input-referred noise with the two gain settings and variable output-referred noise. The output-referred noise in HI gain mode increases (with gain) by four. This setting is recommended when driving converters with higher noise floors. The extra gain boosts the AD8332 output signal levels and noise floor appro-priately. When driving circuits with lower input noise floors, the LO gain mode optimizes the output dynamic range.

Gm2+

–Gm1

VOH

VOL

VCM

Gm1

Gm2

F1

F2

Figure 62. Output Clamping Characteristics

Figure 61. Postamplifier Block Diagram

AD8332

Rev. B | Page 21 of 32

APPLICATIONS

5V

LMD21

INH22

VPS23+5V 5V

LON24

LOP25

COM26

VIP27

8 VIN2

VCM29

GAIN10

RCLMP11

VOH212

VOL213

COMM14

LMD1 28

INH1 27

VPS1 26

LON1 25

LOP1 24

COM1 23

VIP1 22

VIN1 21

VCM1 20

HILO 19

ENB 18

VOH1 17

VOL1 16

VPSV 15

1nF

1nF0.1µF

1nF0.1µF

VGAIN

CLMD0.1µF

LNASOURCE

CSH* CFB*

RFB*1nF

0.1µF 0.1µF

LNA OUT

0.1µF

FB

1nF 0.1µF

0.1µF

5V

5V

*SEE TEXT

*VGA OUT

*VGA OUT

1nF 0.1µF

Figure 63 shows the basic circuit connections for one channel of the AD8332.

LNA

The AD8332 LNA requires several external components. The LMD pin (internally connected to the bias circuitry) must be decoupled to ground, and the INH pin is capacitively coupled to the signal source (see Figure 63). A 0.1 μF capacitor is recom-mended for both.

The unterminated input impedance of the LNA is 6 kΩ. The user may synthesize any LNA input resistance between 50 Ω and 6 kΩ. RFB is calculated according to Equation 6 or selected from Table 4.

( )( ) ( )6–Ω6

×Ω33=

IN

INFB Rk

RkR

Table 4. LNA External Component Values for Common Source Impedances

RIN (Ω) RFB (Nearest STD 1% Value, Ω) CSH (pF) 50 280 22 75 412 12 100 562 8 200 1.13k 1.2 500 3.01k None 6k ∞ None

Figure 63. Basic Connections for a Single Channel (AR Package Shown)

When active input termination is used, a 0.1 µF capacitor (CFB) is required to isolate the input and output bias voltages of the LNA.

LNACSH

5Ω

VIN

VIP

LOP

VCMLON

TO EXTCIRCUIT

TO EXTCIRCUIT

5Ω 50Ω100Ω

100Ω50Ω

The shunt input capacitor, CSH, reduces gain peaking at higher frequencies where the active termination match is lost due to the HF gain roll-off of the LNA. Suggested values are shown in Table 4; for unterminated applications, reduce the capacitor value by half.

When a long trace to Pin INH is unavoidable, or if both LNA outputs drive external circuits, a small ferrite bead (FB) in series with Pin INH preserves circuit stability with negligible effect on noise. The bead shown is 75 Ω at 100 MHz (Murata BLM21 or equivalent). Other values may prove useful. Figure 64. Interconnections of the LNA and VGA

Figure 64 shows the interconnection details of the LNA output. Capacitive coupling between LNA outputs and the VGA inputs is required because of differences in their dc levels and to elimi-nate the offset of the LNA. Capacitor values of 0.1 µF are rec-ommended. There is 0.4 dB loss in gain between the LNA out-put and the VGA input due to the 5 Ω output resistance. Addi-tional loading at the LOP and LON outputs will affect LNA gain.

Both LNA outputs are available for driving external circuits. Pin LOP should be used in those instances when a single-ended LNA output is required. The user should be aware of stray capacitance loading of the LNA outputs, in particular LON. The LNA can drive 100 Ω in parallel with 10 pF. If an LNA output is routed to a remote PC board, it will tolerate a load capacitance up to 100 pF with the addition of a 49.9 Ω series resistor or fer-rite 75 Ω/100 MHz bead.

AD8332

Rev. B | Page 22 of 32

VGA LOGIC INPUTS—ENB, MODE, AND HILO In the AR package, Pin ENB is common to both channels and controls the LNA and VGA. In the AC package, Pins ENBL and ENBV control the LNA and VGA. The input impedance of the ENB pin is nominally 25 kΩ and may be pulled up to 5 V (a pull-up resistor is recommended) or driven by any 3 V or 5 V logic families. As with the GAIN pin, several devices may be connected in parallel and driven from a common source.

GAIN INPUT

The input impedance of the GAIN pin is nominally 10 MΩ. The GAIN pin is common to both channels and a 100 pF–1 nF capacitor is required for bypassing.

If several AD8332s are connected in parallel, they may be driven by a common voltage source or DAC. The source de-coupling should take into account any bandwidth considera-tions of the drive waveform, using a total value of the selected bypass capacitance distributed among the devices.

Pin HILO is also compatible with 3 V or 5 V CMOS logic fami-lies. It is either connected to ground or pulled up to 5 V, depending on the required gain range and output noise.

If gain control noise in LO gain mode becomes a factor, main-taining ≤15 nV/√Hz noise at the GAIN pin will ensure satisfac-tory noise performance. Internal noise prevails below 15 nV/√Hz at the GAIN pin. Gain control noise is negligible in HI gain mode.

OPTIONAL OUTPUT VOLTAGE LIMITING

The RCLMP pin provides the user with a means to limit the output voltage swing when used with loads that have no provi-sions for prevention of input overdrive. The peak-to-peak lim-ited voltage is adjusted by a resistor to ground, and Table 5 lists several voltage levels and the corresponding resistor value. Unconnected, the default limiting level is 4.5 V p-p. VCM INPUT

The common-mode voltage of Pins VCM, VOL, and VOH defaults to 2.5 vdc. With output ac-coupled applications, the VCM pin will be unterminated; however, it must still be bypassed in close proximity for ac grounding of internal cir-cuitry. The VGA outputs may be dc connected to a differential load, such as an ADC. Common-mode output voltage levels between 1.5 V and 3.5 V may be realized at Pins VOH and VOL by applying the desired voltage at Pin VCM. DC-coupled opera-tion is not recommended when driving loads on a separate PC board.

Note that third harmonic distortion will increase as waveform amplitudes approach clipping. For lowest distortion, the clamp level should be set higher than the converter input span. A clamp level of 1.5 V p-p is recommended for a 1 V p-p linear output range, 2.7 V p-p for a 2 V p-p range, or 1 V p-p for a 0.5 V p-p operation. The best solution will be determined experimentally. Figure 66 shows third harmonic distortion as a function of the limiting level for a 2 V p-p output signal. A wider limiting level is desirable in HI gain mode.

HD

3–

dBc

5.0

–50

–40

–30

–80

–70

–60

2.0 3.51.5 3.02.5 4.0 4.5

–20

CLAMP LIMIT LEVEL – V p-p

VGAIN = 0.75V

HILO = HI

HILO = LO

The voltage on the VCM pin is sourced by a buffer with an out-put impedance of 30 Ω and a ±2 mA default output current (see Figure 65). If the VCM pin is driven from an external source, its output impedance should be 2 mA. If the VCM pins of several AD8332s are connected in parallel, the external buffer should be capable of overcoming their collective output currents. When a com-mon-mode voltage other than 2.5 V is used, a voltage-limiting resistor, RCLMP, is needed to protect against overload.

VCMNEW VCMRO

AD8332

Rev. B | Page 23 of 32

Table 5. Clamp Resistor Values

Clamp Resistor Value (kΩ) Clamp Level (V p-p) HILO = LO HILO = HI 0.5 1.21 1.0 2.74 2.21 1.5 4.75 4.02 2.0 7.5 6.49 2.5 11 9.53 3.0 16.9 14.7 3.5 26.7 23.2 4.0 49.9 39.2 4.4 100 73.2

OUTPUT FILTERING AND SERIES RESISTOR REQUIREMENTS

When the AD8332 drives large capacitive loads or circuits on other boards, series resistors are recommended for the VOH and VOL outputs to ensure stability at the high end of the gain control range. These resistors can be part of the external noise filter.

Recommended resistor values are 84.5 Ω for LO gain mode and 100 Ω for HI gain mode (see Figure 63) and are placed near Pins VOH and VOL. Lower value resistors are permissible for applications with nearby loads or with gains less than 40 dB. These resistors can also be part of an output filter circuit. Experimentation is encouraged when lower values are desired, but the above values are recommended when they do not pose a problem for the frequency response of the output.

An antialiasing noise filter is typically used with an ADC. Filter requirements are application dependent.

When the ADC resides on a separate board, the majority of filter components should be placed with it. This reduces noise picked up between boards and mitigates charge kickback from the ADC inputs. Any series resistance beyond that required for the AD8332 should be placed on the ADC board. Figure 67 shows a second order low-pass filter with a bandwidth of 20 MHz. The capacitor is chosen in conjunction with the 10 pF input capacitance of the ADC.

18pF

OPTIONALBACKPLANE

84.5Ω0.1µF

0.1µF

1.5µH

1.5µH

158Ω

158Ω84.5Ω ADC

Figure 67. 20 MHz Second Order Low-Pass Filter

Driving ADCs

The A8332 accommodates a wide range of ADCs. The noise floor requirements of the VGA will depend on a number of application factors, including bit resolution, sampling rate, full-

scale voltage, and the bandwidth of the noise/antialias filter. The output noise floor and gain range of the AD8332 can be adjusted by selecting HI or LO gain mode.

The relative noise and distortion performance of the two gain modes can be compared in Figure 21 and Figure 27–Figure 37. The 48 nV/√Hz noise floor of the LO gain mode is suited to converters with higher sampling rates or resolutions (such as 12 bits). Both gain modes can accommodate ADC full-scale voltages as high as 4 V p-p. Since AD8332 distortion perform-ance remains favorable for output voltages as high as 4 V p-p (see Figure 32), it is possible to lower the output-referred noise even further by using a resistive attenuator (or transformer) at the output. The circuit in Figure 68 has an output full-scale range of 2 V p-p, a gain range of –10.5 dB to +37.5 dB, and an output noise floor of 24 nV/√Hz, making it suitable for some 14-bit ADC applications.

AD8332VOH

VOL

LPF

2:1

187Ω

187Ω

374Ω ADCAD6644

4V p-p DIFF,48nV/ Hz

2V p-p DIFF,24nV/ Hz

Figure 68. Adjusting the Noise Floor for 14-Bit ADCs

Overload

The AD8332 responds gracefully to large signals that overload its input stage and to normal signals that overload the VGA when the gain is set unexpectedly high. Each stage is designed for clean-limited overload waveforms and fast recovery when gain setting or input amplitude is reduced.

Signals larger than ±275 mV at the LNA input are clipped to 5 V p-p differential prior to the input of the VGA. Figure 44 shows the response to a 1 V p-p input burst. The symmetric overload waveform is important for applications, such as CW Doppler ultrasound, where the spectrum of the LNA outputs during overload is critical. The input stage is also designed to accommodate signals as high as ±2.5 V without triggering the slow-settling ESD input protection diodes.

Both stages of the VGA are susceptible to overload. Postamp limiting is more common and results in the clean-limited out-put characteristics found in Figure 45. Under more extreme conditions, the X-AMP will overload, causing the minor glitches evident in Figure 46. Recovery is fast in all cases. The graph in Figure 69 summarizes the combinations of input signal and gain that lead to the different types of overload.

AD8332

Rev. B | Page 24 of 32

GA

IN–

dB

1m

LO GAINMODE

15mV

–4.5

25mV

LNA

OV

ERLO

AD

X-AMPOVERLOAD

POSTAMPOVERLOAD

X-AMPOVERLOAD

POSTAMPOVERLOAD

29dB

43.5

INPUT AMPLITUDE – V.2750.110m

24.5dB

GA

IN–

dBHI GAINMODE

4mV

7.5

25mV

LNA

OV

ERLO

AD

41dB

56.5

INPUT AMPLITUDE – V

24.5dB

1 1m 0.2750.110m 1

There are several critical areas relating to the AD8332 that require additional care, especially with the LNA. The LON and LOP output traces must be as short as possible before connect-ing to the coupling capacitors connected to Pins VIN and VIP. RFB must be placed close to the LON pins as well. Resistors must be placed as close as possible to the VGA output pins VOL and VOH to mitigate loading effects of connecting traces. Values are discussed in the Output Filtering and Series Resistor Requirements section.

Signal traces should be short and direct to avoid parasitic effects. Wherever there are complementary signals, symmetrical layout should be employed to maintain waveform balance. PCB traces should be kept adjacent when running differential signals over a long distance. Differential wiring should be twisted together to minimize the area of the loop that is formed. This will reduce the radiated energy and make the circuit less suscep-tible to interference. Where possible, signals should be run over ground planes to avoid radiating or to minimize susceptibility to radiating sources.

Figure 69. Overload Gain and Signal Conditions

The previously mentioned clamp interface controls the maxi-mum output swing of the postamp and its overload response. When no RCLMP resistor is provided, this level defaults to near 4.5 V p-p differential to protect outputs centered at a 2.5 V common mode. When other common-mode levels are set through the VCM pin, the value of RCLMP should be chosen for graceful overload. A value of 8.3 kΩ or less is recommended for 1.5 V or 3.5 V common-mode levels (7.2 kΩ for HI gain mode). This limits the output swing to just above 2 V p-p diff.

Multiple Input Matching

Active termination matching is particularly convenient for accommodating sources with dissimilar impedances. A relay and low supply voltage analog switch may be used to select between multiple sources and their associated feedback resistor. Figure 70 shows how such a scheme might be implemented using an ADG736 dual SPDT switch. Higher order switches are also available and users are referred to the Analog Devices Selection Guide for switches and multiplexers.

Layout, Grounding, And Bypassing

As with any high speed device, the AD8332 is sensitive to its PCB environment. Realizing its superior performance specifica-tions requires attention to various details generic to good high speed performance as well as those specific to the AD8332.

INH

LNALMDLOP

ADG736

LONAD8332

18nF

SELECT RFB

1.13kΩ

280Ω

5Ω

5Ω0.1µF50Ω

200Ω

0.1µF

A primary requirement is a good solid ground plane that covers as much of the board area surrounding the AD8332 as possible. The only exception to this is that the LNA output pins (LON and LOP) should be kept a few millimeters away from the ground plane. To minimize stray capacitance on these nodes and help preserve the bandwidth, the ground plane beneath these pins should be removed.

Multiple power and ground pins provide robust power distribu-tion to the device and must all be connected. The power supply pins (VPS1, VPS2, and VPSV) should each be bypassed to a nearby ground plane. Multiple values of high frequency ceramic chip capacitors are recommended to provide the lowest possible impedance path to ground over a wide frequency range. They should be placed as close as possible to the device and they should have capacitance values of 0.01 μF to 0.1 μF in parallel with 100 pF to 1 nF. In addition, it is best if each supply pin is isolated from the common 5 V power via ferrite beads. They, together with the decoupling capacitors, help eliminate unde-sired high frequencies at the supply pins without reducing the headroom, as do small value resistors.

Figure 70. Accommodating Multiple Sources

AD8332

Measurement Considerations Ultrasound TGC Application

Figure 51, Figure 52, and Figure 53 show typical measurement configurations and proper interface values for measurements with 50 Ω conditions.

The AD8332 ideally meets the requirements of medical and industrial ultrasound applications. The TGC amplifier is a key subsystem in such applications, since it provides the means for echolocation of reflected ultrasound energy.

Short-circuit input noise measurements are made using Figure 53. The input-referred noise level is determined by divid-ing the output noise by the numerical gain between Point A and Point B and accounting for the noise floor of the spectrum ana-lyzer. The gain should be measured at each frequency of interest and with low signal levels since a 50 Ω load is driven directly. The generator is removed when noise measurements are made.

Figure 71 through Figure 73 are schematics of a dual, fully dif-ferential system using the AD8332 and AD9238 12-bit high speed ADC with conversion speeds as high as 65 MSPS. In this example, the VGA outputs are dc-coupled, using the reference output of the ADC and a level shifter to center the common-mode output voltage to match that of the converter. Consult the data sheet of the converter to determine whether external CMV biasing is required for the device being used. If the CMV of the VGA and ADC are widely disparate, ac coupling is recom-mended.

A 100 Ω/120 nH resistor/bead network is recommended if the capacitance at the VGA output is greater than 10 pF, or in the event that A/D converters are located remotely from the VGA.

Rev. B | Page 25 of 32

AD8332

AD8332ARU

+3.3VDVDD

TB1+5V

TB2GND

+5VLNA

+5VGA

LDO+3.3VCLK

+3.3VADDIG

+3.3VAVDD

L7120nH FB

VR1ADP3339AKC-3.3

L6120nH FB

L2120nH FB

L3120nH FB

L4120nH FB

L5120nH FB

TP4(BLACK)

TP3(RED)

VOH1

21

25

VIN1

LON1

C580.1µF

C560.1µF

17

TP8

VIN+A

VIN–A

TP1

1 LMD2

2 INH2

3 VPS2

4 LON2

7

5

VIP2

LOP2

VPS1 26

COM26 COM1 23

8 VIN2

27INH1 S1EIN1

L13120nH FB

TP628LMD1

COM14

9 VCM2

C480.1µF

C781nF

C831nF

10 GAINGAIN

TP2

11CLMPR3

RCLMPC54

0.1µF

C550.1µF

VOH212

VIN+B

VIN–B

L11 120nH FB

TP7

VOL213L10 120nH FB

TP10

VPSV 15

VOL1 16L8 120nH FB

TP11L9 120nH FB

18ENB+5VGA

19HILO DO NOT INSTALL R12R130Ω

20VCM1

22

24

VIP1

LOP1

+5VLNA

VCM

AD8541

VCM

1kΩ2kΩ

76

3

2

R124.7kΩ

100Ω

R4100Ω

100Ω100Ω

100Ω

R2280Ω

C8218nF

R1280Ω

VREF

S3EIN2

L12120nH FB

TP5

C8118nF

+

-

1nF

+C461µF

+C441µF

C310.1µF

C490.1µF

C500.1µF

C700.1µF C60

0.1µF

C420.1µF

C590.1µF

C300.1µF

C8022pF

C7922pF

C771nF

C841nF

C851nF

C450.1µF

C430.1µF

C741nF

C410.1µF

C290.1µF

C10.1µF

0.1µF

C510.1µF

C530.1µF

1nF0.1µF

Figure 71. Schematic, TGC, VGA Section

Rev. B | Page 26 of 32

AD8332

VREF

VIN+_A

VIN –_A

VIN –_B

VIN+_B

MUX_SELECT

1

2

3

17

AVDD

62SHARED_REF

6

7

REFT_A

REFB_A

SENSE

11

10

REFT_B

REFB_B

14

15

CLK_A

18 CLK_B

63

DCS19

DFS20

PDWN_B

PDWN_A 60

21

OEB_B22

16

4

13

AGND

AGND

64

12

5

AVDD

AVDD

AVDD

8

9

AGND

AGND

D5_B

D4_B

D3_B

DRGND

D2_B

D1_B

D0_B

DNC

DNC

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

3332

31

30

29

28

27

26

25

24

23

DRVDD

D10_A

D11_A

OTRA_A

D11_A(MSB)

DRGND

D8_A

DRVDD

D7_A

D6_A

D5_A

D4_A

D3_A

D2_A

D1_A

D0_A

DRVDD

D10_A

DRGND

OTRB_B

61

D9_A

59

58

57

56

55

54

53

OTR_A

U1

A/D

CO

NVE

RTE

R A

D92

38

D9_A

D8_A

D6_A

D7_A

D5_A

D4_A

D3_A

D2_A

D1_A

D0_A

DNC

DNC

D4_B

D3_B

D2_B

D1_B

D0_B

DNC

DNC

OTR_B

D11_B

D10_B

D9_B

D8_B

D7_B

D6_BD5_B

20MHz

ADCLK+3.3VCLK

ADCLK

+3.3VAVDD

VIN–B

VIN+B

+

+

+3.3VADDIG

SG-636PCE14

3

2 U574VHC04

+

+

TP 9

TP 12

43 1 2

1213

1011

U574VHC04

U574VHC04

U574VHC04

U574VHC04

U574VHC04

SPARES

8965

TP 13

JP 1

3

21

VDD

OUT

GND

OE JP 4

S2EXT

CLOCK

+

JP 11JP 3

JP 2SHARED

REF

+3.3VADDIG

Y

D10_B

D9_B

D8_B

D7_B

D6_B

D11_B(MSB)

DNC

DNC

OEB_A

EXT

INT

VIN+_A

VIN–_A

N

DATACLK

VREF

C140.1µF

C1110µF6.3V

C140.1µF

C230.1µF

C251nF

R144.7kΩ

R11100ΩR10

0Ω

R150Ω

C220.1µF

C211nF

C860.1µF

C4710µF6.3V ADCLK

C210µF6.3V

C181nF

C170.1µF

C5210nF

C5710nF

C6118pF

C400.1µF

C390.1µF

R5158Ω

R6158Ω

1.5kΩ1.5kΩ

1.5kΩ1.5kΩ

C320.1µF

C320.1µF

R90Ω

R8158Ω

R7158Ω

C191nF

C200.1µF

C3410µF6.3V

C630.1µF

C260.1µF

C241nF

C3310µF6.3V

C380.1µF

C160.1µF

C6218pF

C151nF

C350.1µF

C360.1µF

C370.1µF

R204.7kΩ

R1749.9Ω

R414.7kΩ

+3.3VCLK

R19499Ω

R165kΩ

R18499Ω

+

Figure 72. Converter Schematic

Rev. B | Page 27 of 32

AD8332

19

1

D10_A

D11_A

24

39

VCC

GND

Y1A1

G11

2

3

6

7

10

4

5

8

9

17

11

14

15

18

19

20+

16

13

12

G2

A8

A7

A6

A5

A4

A3

A2

Y8

Y7

Y6

Y5

Y4

Y3

Y2

VCC

GND

Y1A1

G11

2

3

6

7

10

4

5

8

9

17

11

14

15

18

19

20+

16

13

12

G2

A8

A7

A6

A5

A4

A3

A2

Y8

Y7

Y6

Y5

Y4

Y3

Y2

VCC

GND

Y1A1

G11

2

3

6

7

10

4

5

8

9

17

11

14

15

18

19

20+ +

16

13

12

G2

A8

A7

A6

A5

A4

A3

A2

Y8

Y7

Y6

Y5

Y4

Y3

Y2

VCC

GND

Y1A1

G11

2

3

6

7

10

4

5

8

9

17

11

14

15

18

19

20+

16

13

12

G2

A8

A7

A6

A5

A4

A3

A2

Y8

Y7

Y6

Y5

Y4

Y3

Y2

2

3

6

7

10

4

5

8

9

17

11

14

15

18

20

16

13

12

37

21

26 25

30

22

23

28 27

35

29

34 33

38

40

36

3132

R3922Ω

DATACLKA

OTR_A

D9_A

D8_A

D6_A

D7_A

D5_A

D4_A

D3_A

D2_A

D1_A

D0_A

DNC

DNC

OTR_B

D11_B

D10_B

D9_B

D8_B

D7_B

D6_B

D5_B

D4_B

D3_B

D2_B

D1_B

D0_B

DNC

DNC

+3.3VDVDD

+3.3VDVDD

+3.3VDVDD

DATACLK

U374VHC541

U1074VHC541

U774VHC541

U274VHC541

SAM080UPM

76

61

79

58

41

80

77

73

72

78

75

74

71

63

69

68

65

64

62

66

67

70

43

59

56 55

52

60

57

54 53

45

51

48 47

44

42

46

4950

SAM080UPM

RP 9

1 8

7

6

54

3

2

1 8

7

6

54

3

2

1 8

7

6

54

3

2

1 8

7

6

54

3

2

1 8

7

6

54

3

2

1 8

7

6

54

3

2

7

6

54

3

2

1 8

7

6

54

3

2

RP 11

RP 12

RP 13

RP 14

1 8

RP 15

RP 16

R4022Ω

1 8

7

6

54

3

2 RP 1

1 8

7

6

54

3

2 RP2

1 8

7

6

54

3

2 RP 3

1 8

7

6

54

3

2 RP 4

1 8

7

6

54

3

2 RP 5

1 8

7

6

54

3

2 RP 6

1 8

7

6

54

3

2 RP 7

1 8

7

6

54

3

2 RP 8

22 × 4

22 × 4

RP 10

22 × 4

22 × 4

22 × 4

22 × 4

22 × 4

22 × 4

HEA

DER

UP

MA

LEN

OSH

RO

UD

HEA

DER

UP

MA

LEN

OSH

RO

UD

C30.1µF

C2810µF6.3V

C80.1µF

C100.1µF

C7610µF6.3V

C70.1µF

C90.1µF

C2710µF6.3V

C40.1µF

C50.1µF

C60.1µF

C7510µF6.3V

+3.3VDVDD

22 × 4

22 × 4

22 × 4

22 × 4

22 × 4

22 × 4

22 × 4

22 × 4

Figure 73. Converter Schematic

Rev. B | Page 28 of 32

AD8332

Rev. B | Page 29 of 32

PIN FUNCTION DESCRIPTIONS Table 6. 28–Lead TSSOP (AR PACKAGE)

Pin No. Name Description 1 LMD2 CH2 LNA Signal Ground 2 INH2 CH2 LNA Input 3 VPS2 CH2 Supply LNA 5 V 4 LON2 CH2 LNA Inverting Output 5 LOP2 CH2 LNA Noninverting Output 6 COM2 CH2 LNA Ground 7 VIP2 CH2 VGA Noninverting Input 8 VIN2 CH2 VGA Inverting Input 9 VCM2 CH2 Common-Mode Voltage 10 GAIN Gain Control Voltage 11 RCLMP Output Clamping Resistor 12 VOH2 CH2 Noninverting VGA Output 13 VOL2 CH2 Inverting VGA Output 14 COMM VGA Ground (Both Channels) 15 VPSV VGA Supply 5 V (Both Channels) 16 VOL1 CH1 Inverting VGA Output 17 VOH1 CH1 Noninverting VGA Output 18 ENB Enable—VGA/LNA 19 HILO VGA Gain Range Select (HI or LO) 20 VCM1 CH1 Commom-Mode Voltage 21 VIN1 CH1 VGA Inverting Input 22 VIP1 CH1 VGA Noninverting Input 23 COM1 CH1 LNA Ground 24 LOP1 CH1 LNA Noninverting Output 25 LON1 CH1 LNA Inverting Output 26 VPS1 CH1 LNA Supply 5 V 27 INH1 CH1 LNA Input 28 LMD1 CH1 LNA Signal Ground

Table 7. 32–Lead LFCSP (AC PACKAGE)

Pin No. Name Description 1 LON1 CH1 LNA Inverting Output 2 VPS1 CH1 LNA Supply 5 V 3 INH1 CH1 LNA Input 4 LMD1 CH1 LNA Signal Ground 5 LMD2 CH2 LNA Signal Ground 6 INH2 CH2 LNA Input 7 VPS2 CH2 LNA Supply 5 V 8 LON2 CH2 LNA Inverting Output 9 LOP2 CH2 LNA Noninverting Output 10 COM2 CH2 LNA Ground 11 VIP2 CH2 VGA Noninverting Input 12 VIN2 CH2 VGA Inverting Input 13 VCM2 CH2 Common-Mode Voltage 14 MODE Gain Slope Logic Input 15 GAIN Gain Control Voltage 16 RCLMP Output Clamping Level Input 17 COMM VGA Ground 18 VOH2 CH2 Noninverting VGA Output 19 VOL2 CH2 Inverting VGA Output 20 COMM VGA Ground 21 VPSV VGA Supply 5 V 22 VOL1 CH1 Inverting VGA Output 23 VOH1 CH1 Noninverting VGA Output 24 COMM VGA Ground 25 ENBV VGA Enable 26 ENBL LNA Enable 27 HILO VGA Gain Range Select (HI or LO) 28 VCM1 CH1 Commom-Mode Voltage 29 VIN1 CH1 VGA Inverting Input 30 VIP1 CH1 VGA Noninverting Input 31 COM1 CH1 LNA Ground 32 LOP1 CH1 LNA Noninverting Output

AD8332

Rev. B | Page 30 of 32

PIN CONFIGURATIONS

AD8332TOP VIEW

(Not to Scale)8

7

6

5

1

4

3

2

14

13

9

12

11

10

21

22

23

24

28

25

26

27

15

16

20

17

18

19

COM1

LOP1

LMD1

LON1

VPS1

INH1

VOH1

ENB

VIP1

VCM1

VIN1

VPSV

VOL1

HILO

VCM2

RCLMP

COMM

VOL2

VOH2

VIP2

GAIN

VIN2

LOP2

COM2

LMD2

LON2

VPS2

INH2PIN 1IDENTIFIER

Figure 74. 28-Lead TSSOP

AD8332TOP VIEW

(Not to Scale)

VIP2

VIN

2

LOP2

CO

M2

LMD2

LON2

VPS2

INH2

8

7

6

5

1

4

3

2

29303132 28 252627

CO

M1

LOP1

LMD1

LON1

VPS1

INH1

VIP1

VIN

1

14139 121110

RC

LMP

COMM

VOL2

VOH2

HIL

O

GA

IN

15 16

20

17

18

19

VOH1

ENB

L

VCM

2VC

M1

VOL1

MO

DE

21

22

23

24

COMM

VPSV

COMM

ENB

V

PIN 1IDENTIFIER

Figure 75. 32-Lead LFCSP

AD8332

Rev. B | Page 31 of 32

OUTLINE DIMENSIONS

4.504.404.30

28 15

141

9.809.709.60

6.40 BSC

PIN 1

SEATINGPLANE

0.150.05

0.300.19

0.65BSC 1.20 MAX

0.200.09

0.750.600.45

8°0°

COMPLIANT TO JEDEC STANDARDS MO-153AE

COPLANARITY0.10

Figure 76. 28-Lead This Shrink Small Outline Package [TSSOP] (RU-28)—Dimensions shown in millimeters

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

0.300.230.18

0.20 REF

0.80 MAX0.65 NOM

0.05 MAX0.02 NOM

12 ° MAX

1.000.900.80

SEATINGPLANE

COPLANARITY0.08

132

89

2524

1617

BOTTO MVIEW

0.500.400.30

3.50REF

0.50BSC

PIN 1INDICATOR

TOPVIEW

5.00BSC SQ

4.75BSC SQ SQ

3.253.102.95

PIN 1INDICATOR

0.60 MAX0.60 MAX

Figure 77. 32-Lead Frame Chip Scale Package [LFCSP] (CP-32)—Dimensions shown in millimeters

ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

AD8332

Rev. B | Page 32 of 32

Ordering Guide AD8332 Products Temperature Range Package Description Package Outline AD8332ARU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-28

AD8332ARU-REEL –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-28

AD8332ARU-REEL7 –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-28

AD8332ACP-REEL –40°C to +85°C Lead Frame Chip Scale Package (LFCSP)* CP-32

AD8332ACP-REEL7 –40°C to +85°C Lead Frame Chip Scale Package (LFCSP)* CP-32

AD8332-EVAL Evaluation Board with AD8332ARU

*Contact factory.

© 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective compa-nies. C03199-0-5/03(B)

FEATURESAPPLICATIONSGENERAL DESCRIPTIONFUNCTIONAL BLOCK DIAGRAMTABLE OF CONTENTSREVISION HISTORYSPECIFICATIONSABSOLUTE MAXIMUM RATINGSTYPICAL PERFORMANCE CHARACTERISTICSTEST CIRCUITSTHEORY OF OPERATIONOverviewLow Noise Amplifier (LNA)ACTIVE IMPEDANCE MATCHINGLNA NOISE

Variable Gain AmplifierX-AMP VGAGAIN CONTROLVGA NOISECOMMON-MODE BIASING

PostamplifierNOISEOUTPUT CLAMPING

APPLICATIONSLNAVGAGAIN INPUTVCM INPUTLOGIC INPUTS—ENB, MODE, AND HILOOPTIONAL OUTPUT VOLTAGE LIMITINGOUTPUT FILTERING AND SERIES RESISTOR �REQUIREMENTS

Driving ADCsOverloadLayout, Grounding, And BypassingMultiple Input MatchingMeasurement ConsiderationsUltrasound TGC Application

PIN FUNCTION DESCRIPTIONSPIN CONFIGURATIONSOUTLINE DIMENSIONSOrdering Guide