A Wide Tuning Triple-Band Frequency Generator MMIC in 0.18µm SiGe BiCMOS Technology

Hechen Wang1, Feng Zhao1, Fa Foster Dai1, Guofu Niu1, Bogdan Wilamowski1, Jun Fu2, Wei Zhou2, and Yudong Wang2

1. Dept. of Electrical and Computer Eng., Auburn University, Auburn, AL 36849 2. Inst. of Microelectronics, Tsinghua University, Beijing, China

Abstract— This paper presents a wide-tuning frequency

generation scheme based on bottom-series coupled quadrature VCO (QVCO). The low band and middle band frequency signal is generated from the QVCO while the high band signal is obtained from a gilbert mixer. The tuning-range enhancement technique allows a three band frequency generation in the range from 2.4GHz to 8.4GHz without penalizing its phase noise. The VCO monolithic microwave integrated circuit (MMIC) is implemented in a 0.18 μm SiGe BiCMOS technology with 1.8 mm2 area. The measured frequency range is 15.4% for the three bands centered at 2.5GHz, 5GHz, and 7.5GHz. The measured phase noise are -124.4dBc/Hz, -119.1dBc/Hz and -108.8dBc/Hz at 1 MHz offset for the low, middle, high band signals, separately. The measurement results demonstrate that proposed frequency generation technique can achieve wide tuning range capability as well as the low phase noise with very compact circuit.

Keywords—quadrature VCO; RF; voltage-controlled oscillator; frequency doubler; tripler; Gilbert mixer; phase noise; tuning range

I. INTRODUCTION Multi-standard wireless transceivers are in high demand for

emerging applications such as smart phones and multi-function PDAs. However, wireless standards allocate channel frequencies across wide-spread spectrum from 900MHz to 5.8GHz. Ultra-wide band (UWB) requires even wider frequency band from 3GHz to 13 GHz. Radar transceivers also requires wide-tuning frequency synthesis to cover the specific radar band such as C-band (4-8GHz) and X-band (8-12GHz) [1]. Among these multi-band communication transceivers, the frequency generation block usually costs large area and power consumption since each band needs its own oscillator core. The requirement of noise optimization for each VCO core adds the design complexity. As a result, a frequency generation scheme which can provide wide frequency range from a compact circuit without several inductors becomes a valid technique to address those demands.

Frequency range and phase noise are two crucial parameters for VCO designs. Following traditional design approach, the target of low phase noise and wide frequency range usually cannot be achieved simultaneously with one VCO core since it requires large varactor size but this will deteriorate the quality factor Q of the tank and thus leading to poor phase noise performance. Moreover, large varactor will

increase the sensitivity of noise to amplitude fluctuations due to AM-FM conversion mechanism.

As a result, enlarging varactors dimensions are unacceptable when the bandwidth requirement extends to a certain level. Therefore, a compact frequency generation scheme that can provide both wide range and low phase noise at the same time will relax such design challenges.

This paper proposes a frequency generation scheme that achieves wide tuning range without penalizing phase noise performance from a low-noise QVCO circuitry. Section II will describe the proposed technique and main functional blocks. The implementation and measurement results will be given in Section III. Section IV draws the conclusion.

II. PROPOSED FREQUENCY GENERATION MODULE The system diagram of the proposed frequency scheme is

given in Fig. 1. The low-band quadrature signals are generated at the output of QVCO core. The differential middle band signals are obtained at the common-mode node of the cross-coupled differential pair. Mixing the differential fundamental frequency signals (f0+ and f0-) with its second harmonic (2f0) produces an upper sideband and a lower sideband (2f0± f0) at the output nodes of the differential mixer. By filtering the lower frequency terms with the bandpass filter (BPF), signal with a frequency 3f0 can be produced at the output of BPF block. The BPF-load is formed by an inductor and two capacitors that peaks at frequency 3fvco which provides filtering effect to rest frequency bands. As a result, triple band signal generation is achieved with one QVCO core and a mixer. The QVCO core not only functions as low-band frequency generation but also works as frequency doubler without extra circuit.

Fig. 1. Proposed triple band frequency generation scheme.

A. Bottom-Series QVCO Core Fig. 2(b) illustrates the QVCO core circuit. SiGe bipolar

199978-1-4799-7230-2/14/$31.00 ©2014 IEEE

Fig 2. Proposed circuit. (a) band switches. (b) circuit schematic of the proposed QVCO. (c) Gilbert cell based frequency tripler.

transistors are used for oscillation transistors in order to obtain a better current efficiency. Signal swing of the oscillator output was maximized to improve the phase noise performance. A tradeoff between signal swing and avoiding BJT’s saturation are carefully balanced through the transistors’ size, the bias voltage and current optimization. If the main oscillation transistors are operated in the saturation region, noise coupling to the substrate will degrade the overall VCO phase noise greatly.

The resonant tank is built by using a three turns differential inductor with optimized Q factor at 2.5GHz and two varactors with reasonable size to improve the phase noise performance. This work uses bottom-series MOSFET coupling (BS-QVCO) to achieve a relatively low phase noise and lower power consumption [2].

B. 2-Bits Capcitor Array Band Switch As mentioned before, the tradeoff between tuning range

and phase noise eventually determines the size of the varactors. As a result we cannot arbitrarily increase VCO’s tuning range by simply increasing the size of varactors. In order to widen the tuning range without affecting overall phase noise, this work introduces a 2-bit band switch controlled capacitor array to the LC-tank resonator to switch the resonant frequency band instead of using large varactors.

The capacitor array is built using four capacitors. Binary weighted capacitance is adopted to enlarge tuning range. The implemented capacitance ratio is (C1=C2): (C3=C4) = 1: 2. Each bit contains two identical capacitors to compensate the process, voltage and temperature (PVT) variations. In this arrangement, two binary bits can provide the control of four different frequency sub-bands.

Conventional switches used for coarse tuning between different VCO bands consist of three NMOS transistors. However, parasitic capacitances resulted from parasitic drain (n+)-to-substrate (p+) diodes vary with the dc voltage applied to its drain, i.e. the smaller the dc voltage, the larger the parasitic capacitance. When the NMOS transistors are off, the drain of the NMOS switch would be floating and close to zero and thus large parasitic capacitance loads the LC tank. Moreover, to decrease the series resistor and increase the

quality factor of the capacitor array, the NMOS transistors for switches are usually implemented with large dimensions. Then the large tuning range is suffered from these parasitic drain-substrate diodes. In order to widen the VCO frequency tuning range, when the NMOS switches are off, a dc voltage equal to supply voltage is applied to the drain through two parallel resistors as shown in Fig. 2 (a). With the proposed frequency extending technique, the frequency tuning range can be increased to cover 15.4% tuning range without degrading the phase noise.

C. Frequency Doubling & Tripling The double frequency band is obtained at the virtual ground

(nodes VC+, VC- in Fig.2 (b)) of the differential pair, where odd order harmonics are cancelled and even order harmonics survived. Comparing to MOSFET transistors, which have greater parasitic capacitors than BJTs, BJT differential pair has larger 2nd order harmonic component at its common mode. And derived from differential pair nonlinear signal model, the 2nd order harmonic gains for BJT and MOSFET transistors at virtual ground are given by

,

,

where Itail is tail current of the differential pair, VOV and VT are transistor’s overdrive voltage and thermal voltage, and RS is current mirror’s output resistance.

Thermal voltage is 26mV and MOSFET’s overdrive voltage is around 100mV for low power design, normally. Under identical working condition, same tail current, 1/VT2 is much larger than 1/(VOV2/2), which leads to a greater 2nd harmonic gain for BJT transistors. The amplitude of the 2nd order harmonics at the common mode node of a BJT differential pair can reach as high as 254mVpp or –5.95dBm in simulation.

As far as the triple frequency band concerned, many designs use single balanced mixer to construct the frequency

(a) (b) (c)

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multiplication [3], which is easy to be implemented. However, when the frequency increases, clock feed through and coupling to the substrate will degrade the mixer performance which is not desirable.

In order to achieve low noise and low spurious tones, a frequency tripler built with double-balanced Gilbert cell is utilized. The Gilbert mixer has a high common-mode rejection ratio and can suppress the clock feed through. The two input signals from the frequency doubler (virtual ground of the QVCO) are differential signals that can be directly connected to Gilbert cells’ differential inputs. The triple frequency band generation mechanism is inferred as follows:

,

. Mixing fundamental quadrature frequency signals with double-frequency signal generates quadrature phase triple-frequency signals.

D. VCO Output Buffer An output buffer is needed for the oscillator testing. Fig 3.

shows the circuit of the output buffer. A 3-stage-buffer is implemented in this design to isolate the LC-tank from loading and to increase the output buffer’s drive capability. Directly loading the oscillator LC-tank will alter oscillation center frequency and lower the loaded Q of the tank as well. The bias currents of these stages are gradually increased stage by stage. MOSFETs are used in the first two stages because they can handle larger voltage swings than BJTs.The last stage uses BJTs which have better current drive capability with higher gm efficiency.

Fig. 3. Output buffer circuit.

III. IMPLEMENTATION AND MEASURED RESULTS The prototype of this wideband frequency generator MMIC

is implemented in a 0.18μm SiGe BiCMOS process. The VCO core consumes 15mW and the frequency multiplier consumes 40mW under a 2.5V supply voltage. The die photograph is shown in Fig. 4 with total area including bond pads of 3.6m2. The VCO core area is 1.8x1.0 mm2, and the rest on-chip area is occupied by a built-in band pass filter for 7.5GHz band output. Off-chip filter can substitute for it when chip’s size is limited.

A. Measured Phase Noise Results Phase noise measurements were performed on an Agilent

E4446A spectrum analyzer with the phase noise measurement

option. The phase noise is measured as -124.4dBc/Hz, -119.1dBc/Hz and -108.8dBc/Hz at 1 MHz offset in each band, respectively.

Fig. 4. Die photo of the wideband frequency generator MMIC

Fig. 5. shows the measured and simulated phase noise in the 2.5GHz band, 5GHz band, and 7.5GHz band at center point of each band’s tuning curve (a 1.2 V voltage difference across the varactors). In the first two bands, measurements show good agreement with the simulation results. For 7.5GHz band, the measured result has a relatively large deviation from simulation result, mainly due to the process drifting of the built-in band pass filters.

Fig. 5. Measured/simulated phase noise at 2.5, 5.0, and 7.5GHz, respectively.

B. Measured Tuning Range The measured tuning range of the QVCO fundamental

frequency band is presented in Fig. 6. According to the measured results, a 15.4% tuning range (from 2.395GHz to 2.804GHz) is achieved in the fundamental frequency band (f0=2.5G).

Tuning ranges of other two frequency bands are derived from the fundamental band accordingly, since they are produced by mixing the fundamental frequencies. Phase noise varies within the tuning range. Fig. 7. Shows the measured phase noise of the QVCO at 1MHz offset across the entire

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tuning range of the fundamental frequency band. The phase noise degraded at 2.4GHz point is because varactors have been biased at the edge of forward biasing range.

0 0.5 1 1.5 2 2.52.3

2.4

2.5

2.6

2.7

2.8

2.9

Vtuning (V)

Freq

uenc

y (G

Hz)

2.5GHz Band Tuning Range 2.395-2.804GHz

Fig. 6. Measured tuning rang of the QVCO fundamental frequency.

Fig. 7. Measured phase noise versus the tuning range of the proposed circuit

@1MHz offset in fundamental frequency band.

C. VCO Performance Comparison

Table I summarizes the performance of the proposed QVCO and comparison with previously published QVCO work. When compared with prior art, the proposed QVCO and frequency multiplier achieves a Figure of Merit (FoM) of 182.2dB, 182.9dB and 170.4dB for each band separately, where the FoM is defined as [4]:

.

In the above definition, L(Δf) is the phase noise at the Δf offset from the oscillator frequency f0, and P is the QVCO’s core power consumption in mW. The FoM is calculated for each band. First two bands consume same amount of power. The third band’s power include main core and mixer cell.

IV. CONCLUSIONS Using a 0.18um SiGe BiCMOS technology, this paper have

presented a compact integration design consisting a mixer based low phase noise wide tuning range QVCO producing three frequency bands of 2.5GHz, 5GHz, 7.5GHz respectively.

According to the tested results, the proposed QVCO with frequency multiplier demonstrated a low-phase-noise and wide tuning range performance. Each frequency band achieves 15.4% tuning range while the phase noise is -124.4dBc/Hz, -119.1dBc/Hz and -108.8dBc/Hz respectively. The QVCO uses NPN transistors for oscillation and NMOS devices for coupling. The second harmonic of QVCO is easy to obtain and utilize with SiGe BiCMOS process. The QVCO occupies a core area of 1.8mm2.

TABLE-I PERFORMANCE COMPARISON OF QVCOS.

Ref./Tech Freq. [GHz]

Tuning Range

PN@1MHz [dBc/Hz]

Power [mW]

FoM [dB]

[5] /CMOS 0.13μm 5.5 / -117 5.28 184.58

[6] /CMOS 0.13 μm 9.6 6.6%

-121 @3MHz

9 182.6

[7] /CMOS 0.18 μm 10 15% -95 14.4 163

[8] /CMOS 0.18 μm 4.8 / -125 22 185

This work /SiGe 0.18

μm

2.5 5

7.5

15.4% all bands

-124.4 -119.1 -108.8

15 15 55

182.2 182.9 170.4

ACKNOLEGEMENT The authors would like to acknowledge Huahong Grace

Semiconductor Manufacturing Corporation for support of the IC fabrication.

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