Signal Processing : Image Communication 1 (1989) 239-243

239Elsevier Science Publishers B .V .

SHORT COMMUNICATION

A GENERAL ARCHITECTURE OF VIDEO CODEC FOR REAL TIMECOMMUNICATION AT 64 kbit/s

M. BALESTRI and A. RINAUDOCSELT-Centro Saudi E Laboratori Telecomunicazioni, Via G. Reiss Romoli, 274 1-10148 Torino, Italy

Received 16 November 1988Revised 14 February 1989 and 12 May 1989

Abstract . In the field of videocoding high computational power is needed to perform special functions such as movementdetection, DCT, quantisation, Huffman coding and decoding, etc . A DSP-based parallel architecture can efficiently realizea moving image communication system operating at low bit rate, without using specialized hardware : the main advantageof this approach is that it allows to change easily the coding algorithms, by simply modifying the software which controlsthe system, so that the same equipment can be used to realize different codecs .

The flexibility of this solution was exploited in designing a video codec able to act as a moving image communicationsystem for inter-personal communication, with sufficient spatial resolution for moving images, or as a still picture transmissionsystem, working at full CCIR resolution, which gives a good image quality in a rather short time (5-6 s) for several applicationssuch as device monitoring, photography or document transmission, etc .

Zusammenfassung . Ire Bereich der Bildcodierung wird grope Rechenleistung ben6tigt, um Algorithmen wie Bewegungsdetek-tion, DCT, Quantisierung, Huffman-Codierung u .a . durchzufuhren . Mit einer auf digitalen Signalprozessoren basierendenParallel-Architektur kann man effizient ein Bewegtbild-Kommunikationssystem fur niedrige Ubertragungs-Ritraten realisi eren,ohne eine spezielle Hardware zu verwenden . Der wichtigste Vorteil dieses Ansatzes ist espdap er es gestahet, durch Modifikationder Software auf einfache Weise die Codier-Algorithmen zu verandern . Dieselbe Hardware kann also benutzt werden, umverschiedene Codecs zu realisieren .

Die Flexibilitat dieser Losung wurde genutzt, um einen Video-Codec zu entwerfen, der entweder als Bewegtbild-Kommunikationssystem oder als Einzelbild-Uhertragungssystem arbeiten kann . Im ersten Fall wird eine fur Bildtelefon-Anwendung ausreichende ortliche Auflosung bereitgestellt, im zweiten Fall bei einer Ubertragungszeit von i-6 s die voileCCIR-Auflosung fur Anwendungen wie Gerate-Uberwachung oder Dokumenten-Ubertragung .

Resume . Dans le domaine du codage video d'importantes ressources de calcul sent necessaires pour effectuer des tSchesspeciales telles que detection de mouvement, DCT, quantification, codage et d€eodage de Huffman, etc . Une architectureparallele basee sur on traitement numerique du signal pent permettre de realiser un systeme de transmission d'images enmouvement operant avec on faible taux de transmission sans utiliser on materiel specialise : l'avantage principal de cetteapproche reside en la possibilite de changer facilement d'algorithme de codage par simple modification du logiciel pilotantce systeme, ce qui fait que le meme equipement pent etre employe pour realiser plusieurs codecs .

La flexibility de cette solution a ete exploitee pour la conception d'un codec video capable de servir de systeme detransmission d'images clans le cas de communication inter-individus, ceci avec une resolution spatiale suffisante pour desimages en mouvement, on de servir de systeme de transmission d'images stables, fonctionnant avec Is plain resolution CCIR,ce qui assure une bone qualite d'image on temps plutot court (5-6 s .) Bans le cadre de plusieurs applications telles quesurveillance de processus, transmission de photographics on dc documents, etc .

Keywords . Photovideotex, videophone, video coding, parallel processing .

0923-5965/89/$3 .50 Q 1989, Elsevier Science Publishers B .V.

240

1 . Introduction

Standardisation of video communication at p x64kbit/s is currently taking place at an acceleratedpace [5, 6, 8]. The proposed algorithms are gen-erally tested by means of software simulationscarried out on standard reference video sequences .This approach makes it possible to get codedresults in a very short time compared to hardwareimplementations, and makes results obtained indifferent laboratories easily comparable .

Nevertheless a video codec may be faced witha wide range of possible situations that cannot beinvestigated simply by simulating the codingalgorithm on short test sequences . To operate in areal time environment, a good coding schemeshould be able to modify dynamically some codingparameters according to the external conditions ofthe scene. Furthermore the fine tuning of all thecoding parameters in a real time environment mustaccount for a variety of situations and it appearsas a much more difficult task than when only afew simple sequences are coded .

The cost of designing and developing a real timevideo codec to test each variant of a codingalgorithm certainly becomes too high if a lot ofexperimental hardware must be developed . Theonly way to reduce this cost in the experimentalphase is to design a flexible video codec which canbe implemented using a parallel architecture basedon general purpose DSPs .

2. General processing architecture for a flexiblevideo codec

To design a flexible architecture to implementin real time a set of coding algorithms for videocommunication implies being confronted with afew general problems . Some functions such asvideo conversion, frame storing, subsampling andinterpolation must be implemented to work atvideo speed, so it is difficult to design them tooperate with great flexibility, while other functions

M. Balestri, A . Rinaudo / A 64 kbif/s widen codec Jor real time communication

involving high computational load can be carriedout following two different approaches :(1) Specialized modules can be developed toimplement specific functions such as DCT, motioncompensation, video multiplex and so on .(2) A general purpose processing board can beused to implement all the processing functions,with a few of these boards operating in parallel toprocess a field .

The former approach is the more efficient solu-tion if the number of processing boards must bereduced at a minimum, while the latter solution,instead, has a large degree of flexibility andrequires less design effort as just a single boardneeds to be developed . The processing power ofthe video codec can be easily increased just byusing as many computational boards as arerequired and a large range of bit rates can becovered .

On the basis of the above considerations thebasic architecture which has been taken as a guide-line in developing a flexible, multiprocessor videocodec is shown in Fig . 1 .

Analog input signals R, G, B and Sync areconverted following CCIR 601 and 656 Recom-mendations [2, 3] . In this way the full resolutionof 720 pixels by 576 lines is made available whenrequired .A 2D digital filter with programmable

coefficients can be applied to the input signal, sothat spatial subsampling can be carried out to geta lower resolution signal without noticeable alias-ing effects .

The incoming signal can be stored in a framememory, whose capacity is large enough to storea full resolution frame (1 Mbyte) . The content ofthis frame store can be distributed to all processingboards by means of a specialized memory con-troller unit which is able to scan the video memoryand transfer its content at a very high transfer rate(27 Mbyte/s) .

The video frame is in this way distributed to allthe processing boards which are able to store theportion of the field they have to process on a videobuffer. Each one of these units can be programmed

Gy CCIRB . E01S- _

20 VARIABLECOEFF. FILTER

M. Halestri, A . Rinaudn / A 64 kbit/s video codes for real time communication

VIDEO

ORCONTROLLER

ItFRAMEMEMORY

H

to implement the whole coding process and to passthe coded data to the video multiplex board, other-wise it can be used to execute a specific functionpassing the intermediate results to the next boardor group of boards . In this way a fully parallelprocessing as well as a partially serialized one canbe implemented .

Two special busses are provided to interchangedata between modules . A standard microprocessorbus can be controlled by each processing moduleas a master to access video information that isstored in each video buffer, which are designed asa multiport RAM . This facility is provided to makepossible the implementation of algorithms that donot allow for a rigid partitioning of the image intoblocks because some overlapping areas must beavailable to two or more processing boards . Asecond specialized bus, called the micro-data linkhere, is used to transfer data between modules onthe basis of variable length messages . This bus isparticularly useful in transferring the coded datato the video multiplex unit to be processed in orderto produce the serial stream of data that can besent on the channel by means of the appropriateinterface.The architecture of the decoder unit is quite

similar to that of the encoder. A 2D digital filteris used here to carry out the interpolation process,

VID O BU R

PROC SSING

VIDEO BUFFER8

PROC 551 G

VIDEO BUF Rd

PROCESSING

0

Fig. 1 . A video coder reference architecture .

H VIDEO MUX _y INS INTERFACE

241

if required, to convert the video format of thedecoded image to the full CCIR resolution fordisplaying purposes. The D/A conversion unitoperates according to the CCIR 601 Recommenda-tion and R, C, B and Sync or Y, CR and CBcomponents are generated to feed a color monitor .Each processing board receives coded video datafrom the video demultiplex unit by means of themicro-data-link and reconstructs a portion of theframe, writing the reconstructed pixels in its videobuffer. When a full field has been reconstructedthe memory controller unit is activated and theframe is transferred in the frame memory . Thismemory is continuously scanned to produce theimage that is displayed on the monitor . This simplescheme allows for variable temporal subsamplingsince the last received frame is displayed until anew one has been fully reconstructed .

3. A 64 kbit/s video codec hardware implementation

The previously described general video process-ing architecture has been followed to implementa video codec on which two different codingschemes have been programmed to operate in realtime as a moving picture videophone codec as wellas a still picture ISO photovideotex compatible

Vol . I, Nn . 2, October 1989

242

S

Signal Processing : Image C'nmmunicarion

M. Balestri, A . Rinaudo / A 64 kbir/s video codec for real rime communication

Fig. 2 . The ISDN videophone terminal .

encoder-decoder [7] . Fig. 2 gives the picture ofthe full ISDN videophone terminal which will beused for the pilot ISDN service in Italy [1] .

The block diagram of the video codec is shownin Fig .3 . Its structure is very similar to the referencearchitecture and just two video processing boardshave been used . Two different spatial resolutionsare used for moving and still pictures . For the firstone a subsampled image of 180 pixels by 144 linesper field with variable temporal subsampling wasadopted whereas the full spatial resolution isrequired for still picture coding . The spatial sub-

AIDmin _!DtY.CS(CR

sampling process is carried out by the 2D filteringunit described above .

The first processing unit is used to operate onthe luminance component while the second oneoperates on both chrominance signals . To get themaximum flexibility also the video-multiplex func-tion has been implemented on a fully program-mable way using a microprocessor board .

The structure of the decoder reflects the sameconsiderations just outlined for the decoder . Inthis case just one video processing board is enoughto implement the coding function .

4. Still and moving picture coding algorithms

The coding algorithm adopted for moving pic-tures is based on conditional replenishmentapplied to a filtered and subsampled video signal(144 x 180 pixels for luminance, and 144 x 90 pixelsfor chrominance) . Further temporal subsampling,controlled by the fullness level of the output buffer,is also possible . Temporal subsampling is variable,and the maximum allowable frame frequency is25 Hz. The subsampled image is divided into 8 x 8blocks, and only changed blocks are coded andtransmitted . Each 8 x 8 block is transformed bymeans of the discrete cosine transform ; the trans-formed coefficients are quantized with a quantiza-tion step size decided according to the number of

MICROPROCESSOR BUS!

VIDEO BUS

RO DATA LIN

Fig. 3 . A 64 kbit/s video coder .

t7

t7 DATA_OUTt7

SVIDEO MEMORY DSP I DSP 2 ~~64_ Kblt/s

VIDEO /~

q CONTROLLER (Y) ICBICR) LINEMEMORY V 7D VIDEO VIDEO TERFACE RS

FILTER RAM RA 232 I!'

S7- C7 t7

M. Balestri, A . Rinaudo / A 64 khit/s video codec far real time communication

changed blocks detected in the conditional replen-ishment phase. A two-dimensional variable lengthcode [4] is applied to the zig-zag scanning of thequantized coefficients, and finally the coded datastream is stored in the transmission buffer and sentto the receiver .

The flexible architecture of the codec has beenexploited realizing a second kind of video com-munication : the still picture facility . For this appli-cation the draft ISO standard [7] for photographicimage transmission has been adopted . Therefore,the image is represented at the full resolutiondefined by CCIR Recommendation 601 (576lines x720 pixels) and progressively or sequen-tially transmitted using adaptive DCT. The trans-mitted frame memory is used as a pre-coding bufferwhere the entire frame is stored, accessed andcoded in progressive form ; at the receiver side, theframe memory is used to display the picture whileit is building up . A good image quality can beobtained in a rather short time (5-6 s) using a64kbit/s communication link .

Acknowledgments

The work described in this paper is the result ofthe effort of a team which included, in addition to

243

Veen. The dedication of all the team to the workhas been the reason of its successful completion .The support of SIP (Societa Italiana Per LeTelecomunicazioni) in the development of theISDN videophone terminal is also acknowledged .

References

[1] M . Balestri, S . Cracas and A . Rinaudo, "A multiprocessorsystem for still and moving image communication at64 kbit/s", Int. Workshop 64 kbit/ s Coding ofMoving Video,Hannover, June 1988 .

[21 CCIR Recommendation 601, "Encoding parameters ofdigital television for studios", Geneva, 1986 .

[3] CCIR Recommendation 656, "Interfaces for digital com-ponent video signals in 525-line and 625-line televisionsystems", Geneva, 1986 .

[4] CCITT SGXV, Working Party XV/1, "Coding ofcoefficients with a two-dimensional table", SpecialistsGroup on Coding for Visual Telephony, Doe. No. 170,November 1986 .

[5] CCITT SGXV, Working Party XV/1, "Studies on quantiz-ing characteristics based on flexible hardware", SpecialistsGroup on Coding for Visual Telephony, Doc. No. 256,October 1987, Source: NTT, KDD, NEC FUJITSU .

[6] CCITT SGXV, Working Party XV/1, "Description of Ref .Model 5 (RM5)", Specialists Group on Coding for VisualTelephony, Doc . No.339, March 1988, Source : The Nether-lands, France, FRG, Italy, Sweden, BTRL .

[7] ISO-IEC/JTCI/SC2/WG8, "Adaptive discrete cosinetransform coding scheme for still image telecommunicationservices", Doe . No . 800 .S. Okuho, R . Nicol, B . Haskel and S . Sabri, "Progress ofCCITT standardization on nx384kbit/s video codec",GLOBECOM '87.

Vol. t, No . 2, October 1999

the authors : Giovanni Baronetti, Alessandro[8]

Campassi, Luisa Conte, MarioGiovanni Pucci, Benedetto Riolfo,

Guglielmo,Wouter Van