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A CMOS 79GHz PMCW Radar SoC

Jan Craninckx

Abstract

▪ High-performance, small form factor millimeter-wave radar systems are key enablers for the new smart society. Application for automotive driver assistance and even autonomous cars is obvious, but also many other systems like vital signs monitoring, gesture recognition, self-guided drones, etc are envisioned.

▪ The research presented in this talk investigates the use of nanoscale CMOS technology for 79GHz radar systems, which will be a key enabler to open up this market for cost-effective high-volume production, and allows integration of large digital processing in the same System-on-Chip. A new concept of phase-modulated radar detection is also introduced that blends perfectly with the integration capabilities of CMOS.

2

Why mmWave radars?

mmWave Sensors are Extremely Robust

snow & rain smokefog

dust

heat

lightingdirt

noise &

vibration

4

mmWave Sensors are Fully Sealed and Invisibly Mounted

perfect aesthetics

discreet monitoring

privacy

5

Radar

evolution

fixed

mobile

automotive today

79 GHz radar SoC module

140 GHz antenna-on-chip systems?

yesterday

tomorrow

6

Speed

(improves with

higher carrier)

Angle

(improves with larger antenna)

Range

(improves with wider bandwidth)

Radar resolution (smaller is better)

“voxel”

24 GHz 77 GHz 79 GHz 140 GHz

7

10+ radars per car

▪ High-resolution, 360 degree radar coverage

Medium Range Radar

(MRR) up to 80m

Short Range Radar

(SRR) up to 30m

Long Range Radar

(LRR) up to 250m

8

79 GHz PMCW Radar System

New Paradigm: mmWave CMOS Radar-on-Chip

leveraging standard foundry technology

high resolution – low power – low cost – small size

10

Waveform Possibilities

11

HPF LPF

TX

RX(spillover

cancellation,

RMIN limit)

(RMAX limit)

PA

LNA

Fast chirp

Fast-time

FFT

Slow-time

FFTADC

Range-

Doppler

map

In-phase

mixer Range

processing

FMCW

Doppler

processing

LPF ADC

TX

RX

PA

LNA

Binary sequence

LO

Correlator

bank

Slow-time

FFT

Bi-phase

mod

Range-

Doppler

map

I,Q

Quadrature

mixer

PMCW

Range

processing

Doppler

processing

VCO/PLL

High Level Comparison: PMCW vs FMCW

12

PMCW FMCW

Ambiguity function, sidelobes +

Sensitivity to phase noise, flicker noise +

ADC resolution +

ADC speed / IF bandwidth +++

PSD +

Sensitivity to interference +/-

TX orthogonality for MIMO +

Communications capability ++

Industrial acceptance +++

easier market entry / limited IP and patents ++

PMCW Radar Operating Principle

Target

Distance D79 GHz LO

m Correlations (multiplication and integration)

∫

∫

∫

∫

∫

0

0

0

0

G * m

∫0

∫0

m Tchip

Tchip

Target at

D = (4 * Tchip * C) / 2

C = speed of light in air

G = Path Loss

TX

RX

2 Gbps

13

... and TX-to-RX Spillover

Target

79 GHz LO

m Correlations (multiplication and integration)

∫

∫

∫

∫

∫

S * m

0

0

0

G * m

∫0

∫0

m Tchip

Tchip

Target at

D = (4 * Tchip * C) / 2

C = speed of light in air

G = Path Loss

TX

RX

TX-to-RX

spillover

Spillover produces a large

response for 0 delay

2 Gbps

14

Range Bins c

RT

2

Time / Doppler

PMCW Radar System

Radar IC

Accumulations

improve SNR

FFTs

determine the frequency

shift of every range bin the

speed of the object found on

that range bin (Doppler)

Also improves SNR

Correlations with delayed

version of the PN sequence

Determine the delay T the

position R

15

System

design

IC

design

Module& antennas

Validation & demonstration

System design, Implementation and Verification

16

System design

17

Matlab chain

PMCW Radar-on-Chip: SISO Block Diagram

Lc parallel

Integrate Lc

pulses

Accumulate

M pulses

PRN code

ADC N-point DFT

Lc parallel paths Lc parallel Lc parallel

CFAR

detection

-

DoA

estimation

-

Tracking

S

PRN code

antennasRF

ADCs

High-speed digital front-end Reconfigurable digital baseband

TC Range resolution

LC Ambiguous range

M Ambiguous speed

N Speed resolution

18

MIMO Block Diagram

Lc parallel

Lc parallel

Lc parallel

Lc parallel paths

Integrate Lc

pulses

Accumulate

M pulses

PRN code

ADC

Integrate Lc

pulses

Accumulate

M pulses

N-point DFT

PRN code

ADC

Beam-

forming

. . .

N-point DFT

MIMO

array

synthesis

Lc parallel paths Lc parallel Lc parallel

. . . Nrx*Ntx virtual

MIMO antennasLc parallel

Peak

extraction

-

DoA

estimation

-

Tracking

S

PRN code

. . .

PRN code

antennasanalog front-end

ADCs

High-speed digital front-end Reconfigurable digital baseband

19

IC – Module - Platform

IC module platform

integrated circuit

containing the core

functionality

carrier containing antennas

and mounted ICs,

similar form factor to product

carrier containing module, components

and connectors, complemented with

computation component (PC, FPGA or

similar) for demonstration20

SOC Implementation

PHADAR 2x2 SoC▪ Integrated mmWave PLL, TRX, ADCs, digital front end

∫

Δ

IQ MXLNAILO

(x5)

MIMO

PN-LEAK

CANC

∫

Δ

MIMO

PN-LEAK

CANC

ILO

(x5)Modulator

PA

Prog.

Buffer

Prog.

Delay-Line

PA

Prog.

Buffer

Prog.

Delay-Line

Int-N

PLL

LO-PLL

PRF=1/(Tc*Lc)

Fc=1/Tc=2Gbps

∫

1 0 0 1 1 1 1

PRN Code

PRF=1/(Tc*Lc)

Fc=1/Tc=2Gbps

∫

1 0 0 1 1 1 1

PRN Code

2 GHz CK

2 GHz CK

VGA ADC

VGA ADC

PLL

RF

NoC MS

ADC

DIGDIG

RX RX

TXTXTX

RXRX

TX

RX

1IP

RX

1Q

M

RX

1IM

RX

1Q

P

NOC_DO /

PLL_LOCK /

PLL_Fdiv

NO

C_

DI

NOC_TE

NO

C_

RS

T

NO

C_

CL

K

PL

L_

Fre

f

VDDRX1dig

VD

DB

B18

VS

SB

B18

NO

C_

CE

ADC

VD

DB

B18

TR

X1

_D

O

VD

D18

dig

TR

X2

_D

O

VDDTX2VDDTX1

VDDLOVDDPLL

VSSTX1 VSSTX2

VSSRX2

VDDRX2

TR

X_

CL

KO

VS

S18

dig

VSSPLL VSSLO

VSSRX1

VDDRX1

RX

2Q

P

RX

2IM

RX

2Q

M

RX

2IP

TR

X4

_D

O

TR

X3

_D

O

VDDRX2dig

VSSRX1dig

No

C S

LN

oC

SL

No

C S

LN

oC

SL

NoC SL

TR

X_

DA

VSSRX2dig

TR

X_

SY

NC

TX1P

TX1M

TX2P

TX2M

VS

SB

B182 RX

PLL 2 TX

2 I/Q

ADC2 Digital Correlator/Accumulator

22

LO Architecture: 5x ILO

▪ A 5th Subharmonic, Inverter-Based Injection Locked Oscillator▪ Avoid frequency distribution at 79GHz across the IC

▪ Frequency multiplication▪ Harmonic based multipliers

▪ Wide functional range, but less damping at ω0/N

▪ Injection locked oscillators▪ Oscillator must be locked

▪ 3X or 5X?▪ 3X locks easier, but PLL @26.333 GHz

▪ 5X is only 15.8GHz PLL and frequency distribution▪ Needs lots of 5th order distortion generation

▪ Inverters!

23

Inverter Based ILO for 79GHz

Vb

VDD

A@ω0

A/3@3ω0

A/5@5ω0 ....

M1

A=450mV

iout∙ejΘ

@5ω0

Input iout(mA) Θ(°)

ω0 0.31 148.6

ω0,3ω0 0.58 148.7

ω0,3ω0,5ω0 0.82 143.8

Up to 15ω0 0.91 145.1

• A>1V for iout=0.82mA,

while VDD in 28nm is 0.9V

• Also reliability is worse

Classical approach Inv based approach

Vb

VDD

Tuned amplifier

M1

iout∙ejΘ

@5ω0A@ω0

ω0=15.8GHz * 2π

24

Implementation

▪ Inverter chain

▪ WP/WN ratio is adjusted to have 50-50 duty cycle.

▪ Oscillator core

▪ VDC2 used to enhance self resonance

2 2 3

20K

12um

9um

16um

13.5um

Lmos=35nm

3

VDCVDC VDC2

Vinj+Vinj-

VCO+ VCO-

M1 M2

[3:0]

M1:M2=5:1

Qind=15 Qvar=8.5~20

Slice 25

Measurements

26

0 5 10 1574

76

78

80

82

84

Varactor bits

Os

cilla

tio

n F

req

ue

nc

y (

GH

z)

79 ± 2GHz

8GHz Free-running Tuning Range

70 72 74 76 78 80 82 84-7

-6

-5

-4

-3

-2

-1

Frequency (GHz)

Inp

ut

Po

we

r (d

Bm

)

VDC2=0.55 V

VDC2=0 V

10GHz Locking Tange

104

106

108

-140

-130

-120

-110

-100

-90

-80

-70

-60

Offset Frequency (Hz)

Ph

as

e N

ois

e (

dB

c/H

z)

SMR40@15.8GHz

ILO@79GHz

14dB±1dB

Locked Phase Noise

I+ I- Q

+ Q-

Cartesian combiner

Combiner

LP

F

Div/8

25MHz

To Dig/ADC

PFD/C

P

Div/N

(79)

Ibias,I Ibias,Q

2-stage PPF

Subsamplig

PLL

Tx_ILO

Rx_QILO Rx_QILO

Tx_ILO

SS-

PDGm

CP-PLL

15.8GHz VCO

Combiner

TX

In-Phase

ILOs

Integer-N PLL

VCO @

15.8 GHz

15.8 GHz distribution

PLL and LO Distribution

Poly-phase

filters

generate

quadrature

RX

QILOs

PPF for

quadrature

phase shifters

27

Antenna Path Details

Sub-harmonic Injection Locked Oscillators

multiply the PLL frequency by 5

Digital Core

TransmitterRX Front-End

Analog BB and

ADCs

TX-to-RX Spillover

cancellationTransmitter side-lobe

suppression

28

TX architecture

1 0 0 1 1 1 1 PRF=1/(Tc*Lc)

PRN Code Fc=1/Tc=2Gbps

CMOS

BUF

IL-VCO

(x5)

Modulator

PA

Harmonic Rejection &

Pulse shaping

15

.8G

Hz

CMOS28

• No LO quadrature

• Transmits @ Psat

• Low side-lobes

BPSK frequency side-lobes

at least -17dBc needed!

29

79GHz Phase-Modulator

1 0 0 1 0 1 .. Lc

PRN Code

generator

79GHz

LO79 8177 GHz

Linear BBX

Non-linear LO

Linear LOX

Non-linear BB

79GHz

LO

PRN Code

generator

1 0 0 1 0 1 .. Lc79 8177 GHz

• Lower 79GHz swing

• More power efficient

79GHz

LO

PRN Code

generator

1 0 0 1 0 1 .. Lc79 8177 GHz

30

TX Sidelobe Reduction by Harmonic Rejection

79GHz

LO

PRN Code

generator

Σ

Δ Delay

Tc/3

1

1

1 0 0 1 0 1 .. Lc

Tc=1/Fc

79 8177 GHz

Most effective side-lobe

rejection @ lowest cost

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79GHz Modulator and PA: Schematic Detail

VDD

VSMX

0

180

60

240VDD

LOp

LOm

MPA

MPA

CnPA

VDD

CnPA

VGPA

3-stage PAGain

Tuner Balun

HR3 Mixer

Prog. Buffer

BBin Prog.Delay-Line

BBin 0°60°180°240°

MMX

32

VGA

VDD

RL

RS

ADC

Buffer

Output

Buffer

To IO

Pads

ADCs

VBIAS

Mixer

LO+ LO-LO-

VDD

VDD

k

I and Q

k

VDD

VBIAS

k

7bits

Vout

VDD

Vin

VB

Vin

Vin

Vout

Receiver Implementation

Gilbert cell

mixer

2dB Gain

2-stage LNA

18dB Gain

VGA stage

≈ 3 → 10.5 dB

in 7 stepsADC driver

≈-2dB gain

33

RX Spillover Cancellation

LNA OUTVDD

VDD

Mix

OUT

Correlation (multiplication with the TX sequence and integration)

Mixer

LO+ LO-LO-

C

C

R

R

BB

WP

WM

BB

BB BB

C2C2

BB

BB

BB Weighted copy of BB injected at the

mixer outputs to cancel the spillover

In steady state the mixer output is uncorrelated with the TX BB sequence:

the spillover is cancelled!

Digital Core Block Diagram

▪ Digital core generates the sequence and performs correlation and

accumulation of the ADC samples

m’[k]

D<6:0>(from ADC)

To TX

Out interface

Correlator (Lc) Accumulator (M)

CK gen

CK (1.975 GHz)

Data Out

I and Q

CK CK/4

CK/<prog>

18 29

7

1

1+1

Clock Out

Data AvailableTRX Sync

Other antenna path35

IC Realization

▪ 28nm CMOS

▪ Die size 3 x 2.63mm

▪ Supply 0.9V/1.8V

▪ Flip chip assembly

36

IC Floorplan

▪ 28nm CMOS

▪ Die size 3 x 2.63mm

▪ Supply 0.9V/1.8V

▪ Flip chip assembly

PLL

RX FE RX FE

ADC

RX BBADC

RX BB

TX TX

DIG.

CORE

DIG.

CORE

SH - ILOs SH - ILOsLO

Distr.

37

IC Photograph

▪ 28nm CMOS

▪ Die size 3 x 2.63mm

▪ Supply 0.9V/1.8V

▪ Flip chip assembly

38

PLL Measurements

▪ 25 MHz reference

▪ 16GHz VCO▪ VCO only Phase Noise

-116 dBc/Hz @ 10 MHz

▪ 2GHz VCO tuning range corresponding to 78 to 88 GHz at TX output

▪ 79GHz ILO▪ -107dBc/Hz @ 10 MHz

CP-PLL = Charge Pump PLL SS-PLL = Sub-Sampling PLL

Measured at 79 GHz with R&S FS-Z90 and FSU and Agilent E5052 Signal Analyzer

39

A

EXTM IX ERef -17 dBm

EXT

1 GHz/Center 80 GHz Span 10 GHz

3DB

RBW 3 MHz

VBW 10 MHz

SWT 60 ms

2 AP

CLRWR

1 AP

VIEW

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

1

Marker 1 [T1 ]

-48.05 dBm

79.839743590 GHz

Date: 15.DEC.2015 15:19:49

Transmitter Measurements

▪ Pout > 10dBm

▪ 4 GHz BW

4 GHz BW

BPSK

SideLobe Supp

Measured with SAGE E band WR12 horn antenna, R&S FS-Z90 and FSU

40

Receiver Measurements

▪ NF < 12dB @ 1 GHz

▪ Including module input

transition

▪ More than 30dB gain

control in VGA

▪ BW > 1 GHz

Measured with NOISE COM 5112 and R&S FSU on a dedicated module with GSG pads instead of antennas

Base Band Analog output before the ADC measured

41

Indoor Antenna Module and Evaluation Board

2 dies on the

back of the

module

Antennas on the

front

Panasonic MegTron6®42

PMCW DemonstratorMatlab

framework

for data analysis

FPGA/ARM core platform for data capture and analysis

Radar module (2 chips):

• 4 TX antennas in azimuth

• 4 RX antennas in elevation

• MIMO configuration results in 2x2 and 4x4 array

• Targets can be localized in both azimuth and elevation

43

Radar Measurements

3 targets in an anechoic

environment at different

distance, azimuth and

elevation

RCS = 20dBs

RCS = 15dBsm

RCS = 10dBsm

Radar board with antenna facing the

targets

Lc = 511 (m-Seq), M = 23244

Range & Speed Measurements

45

MIMO 4x4 Measurements

46

Angle of Arrival:

Conclusions

▪ CMOS Radar SoCs area key building block for next-generation (self-driving) cars

▪ And smart homes, buildings, things, etc.

▪ PMCW radar system is a feasible alternative for current FMCW architectures

▪ Major advantage for large-scale radar imagers

▪ IMEC PMCW radar SoCs prototypes show functionality

▪ And are used by partner companies in various application experiments

▪ The future is still to come; we haven’t seen the last innovation in radars yet ☺

47

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