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Microprocessor 8085 Dr. Rakesh Geetraj Prasher Architecture 9796228000
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Chapter –I
8085 Microprocessor Architecture
Contents
Architecture of 8085 microprocessor
8085 pin description.
8085 system bus.
Internal data operations.
Externally initiated operations.
Demultiplexing AD7-AD0.
Bus timings.
Memory read/write.
By Dr. Rakesh Geetraj Prasher Ph.D, M.Phil in Electronics
Microprocessor 8085 Dr. Rakesh Geetraj Prasher Architecture 9796228000
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Introduction
Microprocessor is a digital device on a chip which can fetch instructions
from a memory, decode and execute them i.e. performs certain arithmetic
and logical operations, accept data from input device, and send results to
output devices. Therefore, a microprocessor interfaced with memory and
Input/Output devices forms a Microcomputer. Basically, there are five
building blocks of a digital computer namely:
Input Unit: Through this unit data and instructions are fed to the memory of
the computer. The basic purpose of this unit is to read the data into the
machine. E.g. keyboards, etc.
Memory Unit: The memory unit of a digital computer consists of devices
which are capable of storing information. The memory of a computer is used
for storing two distinct type of information such as data to be processed by
the computer and program through which the result of the desired problem is
obtained. Computer program and data are stored in the Memory Unit. This
usually consists of chips of both ROMs (Read Only Memories) and RAMs
(Random Access Memories) either bipolar or MOS.
Arithmetic and Logical Unit (ALU): This unit is used for performing
arithmetic operations such as Addition, Subtraction, Multiplications,
division and other logical operations on the data. The control unit guides
ALU which of the operations are to be performed. The sequence of the
instructions is controlled by the control unit.
Control Unit The control unit performs the most important function in a
computer. It controls all other units and also controls the flow of data from
one unit to another for performing computations. It also sequences the
operations. It instructs all the units to perform the task in a particular
sequence with the help of clock pulses.
Output Unit After processing of the data in the Arithmetic and Logical
Unit, the results are displayed to the output world through this unit. The
CRTs (Cathode Ray Tubes), 7 segments LED display.
8085 is pronounced as "eighty-eighty-five" microprocessor. A
microprocessor is a controlling unit of a micro-computer, fabricated on
a small chip capable of performing Arithmetic Logical Unit (ALU)
Microprocessor 8085 Dr. Rakesh Geetraj Prasher Architecture 9796228000
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operations and communicating with the other devices connected to it. It
is an 8-bit microprocessor designed by Intel in 1977 using NMOS
technology.
Or
The microprocessor is a programmable device that takes in numbers,
performs on them arithmetic or logical operations according to the
program stored in memory and then produces other numbers as a
result.
Fig. 1.1 Microcomputer
The features of INTEL 8085 are:
It is an 8 bit processor.
It is a single chip N-MOS device with 40 pins.
It has multiplexed address and data bus. (AD0-AD7).
It works on 5 Volt dc power supply.
Maximum clock frequency is 3 MHz while minimum frequency is
500 kHz.
It provides 16 address lines so it can access = 64 Kbytes of
memory.
It generates 8 bit I/O address so it can access = 256 input ports.
ALU
Control Unit
Central Processing Unit (CPU)
Output Unit
Input Unit
Memory Unit
Microprocessor 8085 Dr. Rakesh Geetraj Prasher Architecture 9796228000
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8085 Architecture____________________________________________
8085 Microprocessor – Functional Units
8085 consists of the three main functional units:
Processing Unit
Instruction Unit
Storage and interface Unit
The internal architecture of 8085 includes the ALU, timing and control unit,
instruction register and decoder, register array, interrupt control and serial
I/O control. The ALU performs the arithmetic and logical operations. The
operations performed by ALU of 8085 are addition, subtraction, increment,
decrement, logical AND, OR, EXCLUSIVE -OR, compare, complement and
left / right shift. The accumulator and temporary register are used to hold the
data during an arithmetic / logical operation. After an operation the result is
stored in the accumulator and the flags are set or reset according to the result
of the operation.
Arithmetic and logic unit (ALU)
The ALU performs the arithmetic and logical operations such Addition,
Subtraction, AND, OR, etc. on 8-bit data. Uses data from memory and from
Accumulator to perform arithmetic. Always stores result of operation in
Accumulator.
General purpose register
The 8085 includes six registers, one accumulator, and one flag register, as
shown in Fig. 1.2. In addition, it has two 16-bit registers: the stack pointer
and the program counter. There are 6 general purpose registers in 8085
processor to store 8 bit data; these are identified as B, C, D, E, H, and L as
shown in the figure. They can be combined as register pairs - BC, DE, and
HL - to perform some 16-bit operations. The programmer can use these
registers to store or copy data into the registers by using data copy
instructions.
Accumulator
The 8085 microprocessor is an accumulator (A) based microprocessor,
Accumulator register must be the one of the operand in Arithmetic and
logical operations. The accumulator is an 8-bit register that is a part of
arithmetic/logic unit (ALU). This register is used to store 8-bit data and to
perform arithmetic and logical operations. It is connected to internal data bus
Microprocessor 8085 Dr. Rakesh Geetraj Prasher Architecture 9796228000
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Microprocessor 8085 Dr. Rakesh Geetraj Prasher Architecture 9796228000
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& ALU. The result of an operation is stored in the accumulator. The
accumulator is also identified as register A.
Temporary register
It is an 8-bit register, which holds the temporary data of arithmetic and
logical operations.
Program counter
It is a 16-bit register deals with sequencing the execution of instructions.
This register is a memory pointer. Memory locations have 16-bit addresses,
and that is why this is a 16-bit register. The microprocessor uses this register
to sequence the execution of the instructions. The function of the program
counter is to point to the memory address from which the next byte is to be
fetched. When a byte (machine code) is being fetched, the program counter
is incremented by one to point to the next memory location
Stack pointer
The stack pointer is also a 16-bit register used as a memory pointer. It points
to a memory location in R/W memory, called the stack. The beginning of the
stack is defined by loading 16-bit address in the stack pointer.
The stack is an area of memory identified by the programmer for
temporary storage of information. The stack is a Last In First Out (LIFO)
structure. It normally grows backwards into memory. In other words, the
programmer defines the bottom of the stack and the stack grows up into
reducing address range.
Given that the stack grows backwards into memory, it is customary to place
the bottom of the stack at the end of memory to keep it as far away from user
programs as possible. In the 8085, the stack is defined by setting the SP
(Stack Pointer) register.
Microprocessor 8085 Dr. Rakesh Geetraj Prasher Architecture 9796228000
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• LXI SP, FFFFH-----This sets the Stack Pointer to location FFFFH
(end of memory for the 8085).
The Size of the stack is limited only by the available memory. Information is
saved on the stack by PUSHing it on. It is retrieved from the stack by
POPing it off. The 8085 provides two instructions: PUSH and POP for
storing information on the stack and retrieving it back. Both PUSH and POP
work with register pairs ONLY.
Flag register
The ALU includes five flip-flops, which are set or reset after an operation
according to data conditions of the result in the accumulator and other
registers. These are the set of 5 flip-flops:
Sign Flag:
Used for indicating the sign of the data in the accumulator. The sign
flag is set if negative (1 –negative).
The sign flag is reset if positive (0 –positive).
Zero Flag:
It is set if result obtained after an operation is 0.
It is set following an increment or decrement operation of that
register.
Auxiliary Carry Flag:
Is set if there is carry out from 3rd-bit (lower nibble position).
Parity Flag:
Is set if the result contains even number of 1s.
Carry Flag:
Is set if there is a carry out of the 7th-bit (MSB).
X- Not used
Its bit position is shown in the fig.1.3.
Fig. 1.3. Flag register of 8085 microprocessor
Microprocessor 8085 Dr. Rakesh Geetraj Prasher Architecture 9796228000
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The most commonly used flags are Zero, Carry, and Sign. The
microprocessor uses these flags to test data conditions. It is an 8-bit register
having five 1-bit flip-flops, which holds either 0 or 1 depending upon the
result stored in the accumulator.
Instruction register and decoder
It is an 8-bit register. When an instruction is fetched from memory then it is
stored in the Instruction register. Instruction decoder decodes the
information present in the Instruction register.
Register Selector
This block controls the use of the register stack in the example. Just a logic
circuit which switches between different registers in the set will receive
instructions from Control Unit.
Timing and control unit
It provides timing and control signal to the microprocessor to perform
operations. Following are the timing and control signals, which control
external and internal circuits:
Control Signals: READY, RD’, WR’, ALE
Status Signals: S0, S1, IO/M’
DMA Signals: HOLD, HLDA
RESET Signals: RESET IN, RESET OUT
Interrupt control
As the name suggests it controls the interrupts during a process. When a
microprocessor is executing a main program and whenever an interrupt
occurs, the microprocessor shifts the control from the main program to
process the incoming request. After the request is completed, the control
goes back to the main program. There are 5 interrupt signals in 8085
microprocessor: INTR, RST 7.5, RST 6.5, RST 5.5, and TRAP.
Microprocessor 8085 Dr. Rakesh Geetraj Prasher Architecture 9796228000
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Pin diagram of 8085:
Fig 1.4. Pin diagram of 8085 microprocessor
Microprocessor 8085 Dr. Rakesh Geetraj Prasher Architecture 9796228000
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The pins of a 8085 microprocessor can be classified into seven groups:
Address bus
A15-A8 (Output 3 State): it carries the most significant 8-bits of memory/IO
address.
Data bus
AD7-AD0 (Input/ Output 3 state) Multiplexed Address/Data Bus: it carries
the least significant 8-bit address and data bus. Lower 8 bits of the memory
address (or I/0 address) appear on the bus during the first clock cycle of a
machine state. It then becomes the data bus during the second and third
clock cycles. 3 stated during Hold and Halt modes.
Control and status signals
These signals are used to identify the nature of operation. There are 3 control
signal and 3 status signals.
Three control signals are RD, WR & ALE.
RD: (Output 3state) This signal indicates that the selected IO or
memory device is to be read and is ready for accepting data available
on the data bus.
WR (Output 3state): This signal indicates that the data on the data
bus is to be written into a selected memory or IO location.
ALE: Address Latch Enable (Output): It is a positive going pulse
generated when a new operation is started by the microprocessor.
When the pulse goes high, it indicates address. When the pulse goes
down it indicates data.
Three status signals are IO/M, S0 & S1.
IO/M: This signal is used to differentiate between IO and Memory
operations, i.e. when it is high indicates IO operation and when it is
low then it indicates memory operation.
S1 & S0 (Output): These signals are used to identify the type of
current operation.
Encoded status of the bus cycle:
S1 S0 status
0 0 HALT
0 1 WRITE
1 0 READ
1 1 FETCH
S1 can be used as an advanced R/W status.
Microprocessor 8085 Dr. Rakesh Geetraj Prasher Architecture 9796228000
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Power supply
There are 2 power supply signals: VCC & VSS. VCC indicates +5V power
supply and VSS indicates ground signal.
Clock signals
There are 3 clock signals, i.e. X1, X2, CLK OUT.
X1, X2: A crystal (RC, LC N/W) is connected at these two pins and is
used to set frequency of the internal clock generator. This frequency is
internally divided by 2.
CLK OUT: This signal is used as the system clock for devices
connected with the microprocessor.
Interrupts & externally initiated signals
Interrupts are the signals generated by external devices to request the
microprocessor to perform a task. There are 5 interrupt signals, i.e. TRAP,
RST 7.5, RST 6.5, RST 5.5, and INTR.
Interrupts in 8085
Interrupts are the signals generated by the external devices to request the
microprocessor to perform a task. There are 5 interrupt signals, i.e. TRAP,
RST 7.5, RST 6.5, RST 5.5, and INTR.
Interrupt are classified into following groups based on their parameter:
A. Vector interrupt: In this type of interrupt, the interrupt address is
known to the processor. For example: RST7.5, RST6.5, RST5.5, TRAP.
B. Non-Vector interrupt: In this type of interrupt, the interrupt address is
not known to the processor so, the interrupt address needs to be sent
externally by the device to perform interrupts. For example: INTR.
C. Maskable interrupt: In this type of interrupt, we can disable the
interrupt by writing some instructions into the program. For example:
RST7.5, RST6.5, and RST5.5.
D. Non-Maskable interrupt: In this type of interrupt, we cannot disable
the interrupt by writing some instructions into the program. For
example: TRAP.
E. Software interrupt: In this type of interrupt, the programmer has to add
the instructions into the program to execute the interrupt. There are 8
software interrupts in 8085, i.e. RST0, RST1, RST2, RST3, RST4,
RST5, RST6, and RST7.
F. Hardware interrupt: There are 5 interrupt pins in 8085 used as
hardware interrupts, i.e. TRAP, RST7.5, RST6.5, RST5.5, INTA.
Microprocessor 8085 Dr. Rakesh Geetraj Prasher Architecture 9796228000
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Note: INTA is not an interrupt, it is used by the microprocessor for sending
acknowledgement. TRAP has the highest priority, then RST7.5 and so on.
INTR (Input): INTERRUPT REQUEST
It is used as a general purpose interrupt. It is sampled only during the
next to the last clock cycle of the instruction. If it is active, the
Program Counter (PC) will be inhibited from incrementing and an
INTA will be issued. During this cycle a RESTART or CALL
instruction can be inserted to jump to the interrupt service routine. The
INTR is enabled and disabled by software. It is disabled by Reset and
immediately after an interrupt is accepted.
INTA (Output): INTERRUPT ACKNOWLEDGE
It is used instead of (and has the same timing as) RD during the
Instruction cycle after an INTR is accepted. It can be used to activate
the 8259 Interrupt chip or some other interrupt port.
RST 5.5, 6.5, 7.5 (Inputs): RESTART INTERRUPTS
These three inputs have the same timing as INTR except they cause an
internal RESTART to be automatically inserted.
RST 7.5 --------- Highest Priority
RST 6.5
RST 5.5--------Lowest Priority
The priority of these interrupts is ordered as shown above. These
interrupts have a higher priority than the INTR.
TRAP (Input): Trap interrupt is a non-maskable restart interrupt. It is
recognized at the same time as INTR. It is unaffected by any mask or
Interrupt Enable. It has the highest priority of any interrupt.
RESET IN: This signal is used to reset the microprocessor by setting
the program counter to zero.
RESET OUT: This signal is used to reset all the connected devices
when the microprocessor is reset.
READY (Input): This signal indicates that the device is ready to send
or receive data. If READY is low, then the CPU has to wait for
READY to go high.
HOLD (Input): This signal indicates that another master is requesting
the use of the address and data buses.
HLDA (HOLD Acknowledge) (Output): It indicates that the CPU
has received the HOLD request and it will relinquish the bus in the
Microprocessor 8085 Dr. Rakesh Geetraj Prasher Architecture 9796228000
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next clock cycle. HLDA is set to low after the HOLD signal is
removed.
Serial I/O signals
There are 2 serial signals, i.e. SID and SOD and these signals are used for
serial communication.
SOD (Serial output data line): The output SOD is set/reset as
specified by the SIM instruction.
SID (Serial input data line): The data on this line is loaded into
accumulator whenever a RIM instruction is executed.
8085 System Bus
Typical system uses a number of busses, collection of wires, which transmit
binary numbers, one bit per wire. A typical microprocessor communicates
with memory and other devices (input and output) using three busses:
Address Bus, Data Bus and Control Bus.
Fig. 1.5. Bus System of 8085
Address Bus
Generally, Microprocessor has 16 bit address bus. The bus over which the
CPU sends out the address of the memory location is known as Address bus.
The address bus carries the address of memory location to be written of to be
read from. The address bus is unidirectional. It means bits flows in one
direction – from the MPU to peripheral devices. We can find that how
much memory location it can use the formula . Where n is the number
of bits used for address lines. Here
= 65536 bytes or 64Kb
So we can say that it can access upto 64 kb memory location.
Microprocessor 8085 Dr. Rakesh Geetraj Prasher Architecture 9796228000
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Q.: If a processor has 4 GB memory then how many address lines are
required to access this memory?
Ans: 4 GB = 4× 1GB
4 =
1GB =
4GB = × =
So 32 address lines are required to access the 4 GB memory. Intel 8088
processor has 20 and the Pentium processor has 32 lines.
One wire for each bit, therefore 16 bits = 16 wires. Binary number
carried alerts memory to ‘open’ the designated box. Data (binary) can then
be put in or taken out. The Address Bus consists of 16 wires, therefore 16
bits. Its "width" is 16 bits. A 16 bit binary number allows 216 different
numbers, or 32000 different numbers, i.e. 0000000000000000 up to
1111111111111111. Because memory consists of boxes, each with a unique
address, the size of the address bus determines the size of memory, which
can be used. To communicate with memory the microprocessor sends an
address on the address bus, eg 0000000000000011 (3 in decimal), to the
memory. The memory the selects box number 3 for reading or writing data.
Address bus is
unidirectional, i.e. numbers only sent from microprocessor to memory, not
other way.
Question?: If you have a memory chip of size 256 kilobytes (256 x 1024 x 8
bits), how many wires does the address bus need, in order to be able to
specify an address in this memory? Note: the memory is organized in groups
of 8 bits per location, therefore, how many locations must you be able to
specify?
Data Bus
8085 Microprocessor has 8 bit data bus. So it can be used to carry the 8 bit
data starting from 00000000H (00H) to 11111111H (FFH). Here ‘H’ tells
the Hexadecimal Number. It is bidirectional. These lines are used for data
flowing in both direction means data can be transferred of can be received
through these lines. The data bus also connects the I/O ports and CPU. The
largest number that can appear on the data bus is 11111111.
Data Bus: carries ‘data’, in binary form, between μP and other
external units, such as memory. Typical size is 8 or 16 bits. Size determined
by size of boxes in memory and μP size helps determine performance of μP.
The Data Bus typically consists of 8 wires. Therefore, 28 combinations of
Microprocessor 8085 Dr. Rakesh Geetraj Prasher Architecture 9796228000
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binary digits. Data bus used to transmit "data", ie information, results of
arithmetic, etc, between memory and the microprocessor. Bus is bi-
directional. Size of the data bus determines what arithmetic can be done. If
only 8 bits wide then largest number is 11111111 (255 in decimal).
Therefore, larger numbers have to be broken down into chunks of 255. This
slows microprocessor. Data Bus also carries instructions from memory to the
microprocessor. Size of the bus therefore limits the number of possible
instructions to 256, each specified by a separate number.
Control Bus
The control bus is used for sending control signals to the memory and I/O
devices. The CPU sends control signal on the control bus to enable the
outputs of addressed memory devices or I/O port devices.
Control Bus is various lines which have specific functions for coordinating
and controlling µP operations. Eg: Read/Not Write line, single binary digit.
Control whether memory is being ‘written to’ (data stored in mem) or ‘read
from’ (data taken out of mem) 1 = Read, 0 = Write. May also include clock
line(s) for timing/synchronizing, ‘interrupts’, ‘reset’ etc. Typically μP has 10
control lines. Cannot function correctly without these vital control signals.
The Control Bus carries control signals partly unidirectional, partly bi-
directional. Control signals are things like "read or write". This tells memory
that we are either reading from a location, specified on the address bus, or
writing to a location specified. Various other signals to control and
coordinate the operation of the system. Modern day microprocessors, like
80386, 80486 have much larger busses. Typically 16 or 32 bit busses, which
allow larger number of instructions, more memory location, and faster
arithmetic. Microcontrollers organized along same lines, except: because
microcontrollers have memory etc inside the chip, the busses may all be
internal. In the microprocessor the three busses are external to the chip
(except for the internal data bus). In case of external busses, the chip
connects to the busses via buffers, which are simply an electronic connection
between external bus and the internal data bus.
The Address and Data Busses:
The address bus has 8 signal lines A8 –A15 which are unidirectional. The
other 8 address bits are multiplexed (time shared) with the 8 data bits. So,
the bits AD0 –AD7 are bi-directional and serve as A0 –A7 and D0 –D7 at
the same time. During the execution of the instruction, these lines carry the
address bits during the early part, then during the late parts of the execution,
Microprocessor 8085 Dr. Rakesh Geetraj Prasher Architecture 9796228000
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they carry the 8 data bits. In order to separate the address from the data, we
can use a latch to save the value before the function of the bits changes.
Demultiplexing AD7-AD0:
From the above description, it becomes obvious that the AD7–AD0 lines are
serving a dual purpose and that they need to be demultiplexed to get all the
information. The high order bits of the address remain on the bus for three
clock periods. However, the low order bits remain for only one clock period
and they would be lost if they are not saved externally. Also, notice that the
low order bits of the address disappear when they are needed most. To make
sure we have the entire address for the full three clock cycles, we will use an
external latch to save the value of AD7–AD0 when it is carrying the address
bits. We use the ALE signal to enable this latch. Fig. 1.6 shows a schematic
that uses a latch the ALE signal to demultiplex the bus.
Generally, 74LS373 Latch IC is used for latching the address issued by
Microprocessor. The bus AD7-AD0 is connected as the input to the latch
74LS373. The AKE signal is connected to the Enable (G) pin of latch, and
the Output Control (OC) signal of the latch is grounded. It has 8-latches (D-
flip flop). Address will appear on AD0-AD7 lines. ALE will go high and
forcing enable G pin of Latch. This will make the latch transparent. It means
whatever will be input, will be output. Presently input address is A0-A7.
Therefore output is A0-A7. When ALE = 0, then AD0-AD7 will now be
used as data bus.
Fig. 1.6. Demultiplexing low order Address Bus
Microprocessor 8085 Dr. Rakesh Geetraj Prasher Architecture 9796228000
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Timing diagram of 8085
Timing diagram is the display of initiation of read/write and transfer
of data operations under the control of 3-status signals IO/M, S1, and S0. As
the heartbeat is required for the survival of the human being, the CLK is
required for the proper operation of different sections of the
microprocessors. All actions in the microprocessor are controlled by either
leading or trailing edge of the clock. If I ask a man to bring 6-bags of wheat,
each weighing 100 kg, he may take 6-times to perform this task in going and
bringing it. A stronger man might perform the same task in 3- times only.
Thus, it depends on the strength of the man to finish the job quickly or
slowly. Here, we can assume both weaker and strong men as machine. The
weaker man has taken 6-machine cycle (6-times going and coming with one
bag each time) to execute the job where as the stronger man has taken only
3-machine cycle for the same job.
Fig 1.7. Machine cycle showing clock period
OPCODE FETCH machine cycle (OFMC)
A microprocessor either reads or writes to the memory or I/O devices.
The time taken to read or write for any instruction must be known in terms
of the µP clock. The 1st step in communicating between the microprocessor
and memory is reading from the memory. This reading process is called
opcode fetch. The process of opcode fetch operation requires minimum 4-
clock cycles T1, T2, T3, and T4 and is the 1st machine cycle (M1) of every
instruction. In order to differentiate between the data byte pertaining to an
opcode or an address, the machine cycle takes help of the status signal IO/
M, S1, and S0. The IO/ = 0 indicates memory operation and S1 = S0 = 1
indicates Opcode fetch operation. The opcode fetch machine cycle M1
consists of 4-states (T1, T2, T3, and T4). The 1st 3- states are used for
fetching (transferring) the byte from the memory and the 4th-state is used to
decode it.
Microprocessor 8085 Dr. Rakesh Geetraj Prasher Architecture 9796228000
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Timing Diagram of OPMC
The process of opcode fetch operation requires minimum 4-clock
cycles T1, T2, T3, and T4 and is the 1st machine cycle (M1) of every
instruction.
Example: Opcode fetch MOV B, C.
T1: The 1st clock of 1st machine cycle (M1) makes ALE high
indicating address latch enabled which loads low-order address 00H on AD7
⇔ AD0 and high-order address 20H simultaneously on A15 ⇔ A8. The
address 00H is latched in T1.
T2: During T2 clock, the microprocessor issues control signal to
enable the memory and memory places 41H from 2000H location on the
data bus.
Fig. 1.8. Data flow from memory to microprocessor
T3: During T3, the 41H is placed in the instruction register and = 1
(high) disables signal. It means the memory is disabled in T3 clock cycle.
The opcode cycle is completed by end of T3 clock cycle.
T4: The opcode is decoded in T4 clock and the action as per 41H is
taken accordingly. In other word, the content of C-register is copied in B-
register.
Microprocessor 8085 Dr. Rakesh Geetraj Prasher Architecture 9796228000
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Fig. 1.9. Opcode Fetch (MOV B, C)
Execution time for opcode 41H is
Clock frequency of 8085 = 3.125 MHz
Time (T) for one clock = 1/3.125 MHz = 325.5 ns = 0.32 µS
Execution time for opcode fetch = 4T = 4×0.32 µS = 1.28 µS
Example: Explain the execution of MVI B, 05H stored at locations
indicated below
Mnemonics
MVI B, 05H
Machine code
06H
05H
Memory location
3000H
3001H
The MVI B, 05H instruction requires 2-machine cycles (M1 and M2). M1
requires 4-states and M2 requires 3-states, total of 7-states as shown in
Fig.1.10. Status signals IO/ , S1 and S0 specifies the 1st machine cycle as
the op-code fetch.
In T1-state, the high order address {30H} is placed on the bus A15 ⇔
A8 and low-order address {00H} on the bus AD7 ⇔ AD0 and ALE = 1. In
T2 -state, the line goes low, and the data 06H from memory location
3000H are placed on the data bus. The fetch cycle becomes complete in T3-
state. The instruction is decoded in the T4-state. During T4-state, the
contents of the bus are unknown. With the change in the status signal, IO/
= 0, S1 = 1 and S0 = 0, the 2nd machine cycle is identified as the memory
read. The address is 3001H and the data byte [05H] is fetched via the data
Microprocessor 8085 Dr. Rakesh Geetraj Prasher Architecture 9796228000
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bus. Both M1 and M2 perform memory read operation, but the M1 is called
op-code fetch i.e., the 1st machine cycle of each instruction is identified as
the opcode fetch cycle. Execution time for MBI B, 05H i.e., memory read
machine cycle and instruction cycle is
Fig. 1.10. Timing diagram for MVI B,05H
Mnemonic
MVI B, 05H
Instruction byte
Opcode
Immediate Data
Machine cycle
Opcode Fetch
Read Immediate Data
T states
4
3
7
Clock frequency of 8085 = 3.125 MHz
Time (T) for one clock = 1/3.125 MHz = 0.32 µS
Time for Memory Read = 3T = 3×0.320 µS = 0.96 µS
Total Execution time for Instruction = 7T = 7×0.320 µS = 2.24 µS
Read Cycle
The high order address (A15 ⇔ A8) and low order address (AD7
⇔ AD0) are asserted on 1st low going transition of the clock pulse. The
timing diagram for memory read ( ) are shown in Fig. 1.11. The A15
⇔ A8 remains valid in T1, T2, and T3 i.e. duration of the bus cycle, but
AD7 ⇔ AD0 remains valid only in T1. Since it has to remain valid for
the whole bus cycle, it must be saved for its use in the T2 and T3. ALE
is asserted at the beginning of T1 of each bus cycle and is negated
towards the end of T1. ALE is active during T1 only and is used as the
clock pulse to latch the address (AD7 ⇔ AD0) during T1. The is
asserted near the beginning of T2. It ends at the end of T3. As soon as
the becomes active, it forces the memory to assert data. becomes
Microprocessor 8085 Dr. Rakesh Geetraj Prasher Architecture 9796228000
21
inactive towards the end of T3, causing the port or memory to terminate
the data.
Fig. 1.11. Memory read timing diagram
Write Cycle
Immediately after the termination of the low order address, at the
beginning of the T2, data is asserted on the address/data bus by the
processor. Control is activated near the start of T2 and becomes inactive
at the end of T3. The processor maintains valid data until after WR is
terminated. This ensures that the memory or port has valid data while WR is
active. It is clear from Fig. 1.12, that for READ bus cycle, the data appears
on the bus as a result of activating and for the bus cycle, the time
the valid data is on the bus overlaps the time that the is active.
Fig. 1.12. Memory Write timing diagram