6 . Graphics Adapters

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6. Graphics Adapters

Structure of a Graphics Adapter Color Representation Video Memory Graphics Accelerators3D AcceleratorsGraphics Processing UnitsDigital Interfaces for Monitors

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2Input/Output Systems and Peripheral Devices (06-2)

Graphics Processing Units

Graphics Processing UnitsOverviewGPGPU ComputingThe CUDA ArchitectureThe Kepler Architecture

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Overview (1)

GPU – Graphics Processing UnitDedicated graphics processors for PCs, workstations, and game consoles

Initially used to accelerate the rendering stage for 3D graphics (e.g., texture mapping)Later also used to accelerate the geometric computations (rotation, translation)

GPUs contain shader units, modules for texture mapping, anti-aliasing etc.

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Overview (2)

Vertex shader units Transform the 3D position of each vertex to the 2D coordinates on the screen and to the depth value for the z-buffer Modify the attributes of vertices: position, color, texture coordinates

Geometry shader unitsGenerate geometric figures or add volumetric details to objects

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Overview (3)Pixel/fragment shader units

Determine the color, z depth, and alpha value for each pixel or fragment

Unified shader units Programmable units Able to perform various shading operations (vertex, geometry, pixel) GPUs contain an array of computing units and a unit that distributes the operations to be performed

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Overview (4)

The architecture with programmable units allows a more flexible use of the hardware resources The programmable units can also be used for other types of computations A flexible parallel architecture is obtained

GPUs also include modules for 2D acceleration, MPEG compression, high-definition video decoding

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Overview (5)

GPUs can be dedicated or integrated Dedicated GPUs

Used in graphics cards interfaced with the motherboard via a PCI Express bus or AGP (Accelerated Graphics Port) interface Have a dedicated memory to the card use Examples

AMD Radeon HD 8xxx (e.g., 8970)

NVIDIA GeForce GTX 7xx (e.g., 780)

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Overview (6)

Integrated GPUsAre integrated into a chipset or processorUse a portion of the system memory Have lower performance compared to dedicated GPUs Examples

Intel HD Graphics (e.g., HD Graphics 4600) AMD Radeon HD 8xxx in APU (Accelerated Processing Unit) processorsNVIDIA in Tegra processors

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Overview (7)

The design of GPUs was influenced by the 2D and 3D programming interfaces

Implement API functions in hardware OpenGL (Open Graphics Library)

For various platforms and languages Functions to draw 3D scenes from primitives

Direct3D (component of DirectX) Only for the Microsoft operating systemsLow-level interface to the 3D hardware functions

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Overview (8)

Technologies for connecting multiple GPUs on different graphics cards NVIDIA: SLI (Scalable Link Interface)

2 .. 4 identical graphics cards are connected via a motherboard (PCIe x 16)

AMD: CrossFireX Up to 4 graphics cards can be connectedThe graphics cards do not have to be identicalThe cards have external connectors

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GPGPU Computing (1)GPGPU (General Purpose computing on GPU)The GPU processing cores provide massive FP computational power

Example: a single NVIDIA GK110 GPU (2,880 cores) achieves 4.29 TFLOPS

The graphics pipeline can also be used for general-purpose applications

The performance can be orders of magnitude higher than that of conventional CPUs



GPGPU Computing (2)

GPUs can process independent vertices and pixels/fragments stream processors

Stream: set of records that require similar computation Kernel function: applied to each element in the stream Shared memories cannot be used

Ideal GPGPU applications: large data sets, high parallelism, reduced dependencies

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GPGPU Computing (3)Disadvantages of GPGPU computing:

The programmer needs to be familiar with the graphics APIs and the GPU architectureProblems need to be expressed in terms of coordinates, textures, shader functions The need to use graphics programming languages: OpenGL, DirectX, Cg

API extensions for running some program functions on GPU's processors: CUDA (NVIDIA), OpenCL (Khronos Group)

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The CUDA Architecture (1)

CUDA (Compute Unified Device Architecture)Software and hardware architecture

Enables GPUs to execute programs written in C, C++, Fortran, OpenCL languagesAllows to use Microsoft's DirectCompute API Allows to access directly the GPU resources for general-purpose computing

Exploits the GPU's capability to operate on large matrices in parallel

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A CUDA program calls kernel functions executed by threadsThreads are organized into blocks and groups of blocks (grids) Thread block:

Set of concurrent threadsCommunicate via a shared memory Each thread has an identifier, registers, private memory, inputs, outputs

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Grid of blocks:Group (array) of thread blocks The blocks execute the same kernel function Ensure synchronization between dependent kernel functions Results are shared in a global memory allocated to an application global synchronization

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The hierarchy of threads is executed on a hierarchy of processors on the GPU

Threads: executed by CUDA cores and other execution units Thread blocks: executed by a streaming multiprocessor (SM, SMX) Group of 32 threads: warp Grids of blocks: executed by the GPU

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The Kepler Architecture (1)Improvement of the Fermi architecture

Implementations: GK110, GK210 GPUsContain 7.1 billion transistorsIncreased number of CUDA cores and double-precision arithmetic unitsImproved power efficiency up to 3x the performance/Watt of the Fermi architectureNew architecture for the streaming multiprocessor (SMX)Enhanced memory subsystem

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The Kepler Architecture (2)

A full implementation contains:15 SMX units with 192 CUDA cores each (15x192 = 2,880 cores)Six 64-bit memory controllers (384-bit interface)Common L2 cache memory for the SMX unitsPCI Express 3.0 interface to the CPU Global scheduler GigaThread Engine

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Each CUDA core contains:Integer arithmetic and logic unit Floating-point unit IEEE 754-2008Fused multiply-add instruction (FMA) more accurate

64 double-precision (DP) units 32 Load/Store units (LD/ST)32 special-function units (SFU) transcendental functions

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Threads are scheduled in groups of 32 (warps)Each SMX unit contains:

Four warp schedulersEight instruction dispatch units

From each warp, two instructions can be dispatched in each cycleEach thread can access up to 255 registers

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Memory subsystemEach SMX unit contains 64 KB or 128 KB of memory shared or L1 cache memoryConfigurations (shared/L1): 48 KB/16 KB; 16 KB/48 KB; 32 KB/32 KB48 KB of read-only data cache memory1536 KB of L2 cache memory: allows to share data between the SMX unitsThe register files and memories are protected by an ECC code

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The Tesla K80 GPU AcceleratorBased on the Kepler GPU architecture and the CUDA parallel computing model Designed to accelerate scientific computingContains two GK210 GPUsNumber of CUDA cores: 2 x (13x192) = 4,992

Only 13 SMX units are enabled in each GPUSingle-precision FP performance: 5.6 TFLOPSDouble-precision FP perform.: 1.87 TFLOPSMemory size: 24 GB (GDDR5)

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6. Graphics Adapters

Structure of a Graphics Adapter Color Representation Video Memory Graphics Accelerators3D AcceleratorsGraphics Processing UnitsDigital Interfaces for Monitors

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Digital Interfaces for Monitors

Digital Interfaces for MonitorsDVIHDMI DisplayPort

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DVI (1)

DVI – Digital Visual InterfaceDeveloped by DDWG (Digital Display Working Group) Intended for liquid crystal monitors and digital projectors Based on the PanelLink technology of Silicon Image serial interface for uncompressed digital video data Partially compatible with HDMI (digital mode) and VGA (analog mode) interfaces

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DVI (2)

Contains signals for a DDC (Display Data Channel) between the monitor and computer

Implemented with the ACCESS.bus serial bus (based on I2C)DDC2 provides bidirectional communication between the monitor and computer Allows for automatic system configuration The format of the configuration data is defined by the EDID (Extended Display Identification Data) standard EDID EPROM

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DVI (3)

The TMDS ProtocolTransition Minimized Differential SignalingDeveloped by Silicon ImageDifferential signaling is used Minimizes the number of transitions for the signals from 1 to 0 and conversely 8b/10b encoding A TMDS link consists of a TMDS transmitter and a TMDS receiver

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DVI (4)

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DVI (5)

Contains three identical encoders The inputs of each encoder are 8 bits for pixel data and 2 control bits In each clock cycle, the encoder generates a 10-bit character:

From the 8 data bits, or From the 2 control bits

The output of each encoder is a continuous stream of serialized TMDS characters

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DVI (6)

Maximum pixel clock frequency: 165 MHz The binary data rate of a TMDS channel: 10 x pixel clock frequency For a TMDS link: 3 x 1.65 = 4.95 Gbits/s

Maximum pixel rate: 165 megapixels/s 2.75 megapixels/frame at 60 Hz

Maximum resolution: 19201440 (4:3) or 20481152 (16:9) at 60 Hz

Increasing the resolution: dual TMDS link The connector contains pins for two links

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DVI (7)

Refresh Rate Single TMDS Link Dual TMDS Link

60 Hz 1920 1080 (HDTV) 2048 1536 (QXGA)

75 Hz 1280 1024 (SXGA) 2048 1536 (QXGA)

85 Hz 1280 1024 (SXGA) 1920 1080 (HDTV)

Maximum resolutions supported by DVI

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DVI (8)

Types of connectorsDVI-I (DVI-Integrated): contains the digital signals for a single- or dual-link and the analog signals (a) DVI-D (DVI-Digital-only): contains only the digital signals (b)

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HDMI (1)

HDMI – High-Definition Multimedia InterfaceAudio/video interface for uncompressed digital data

For connecting A/V sources to computer monitors, digital TVs, digital audio devices

Enables to send on a single cable:Various TV and PC video formats Up to 8 digital audio data streams Auxiliary data and control information

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HDMI (2)Uses the TMDS protocol

HDMI signals are electrically compatible with the DVI signals passive adapter Video period: for the pixels of an active video line (8b/10b); includes horizontal and vertical blanking intervals Data period: for audio and auxiliary data packets (4b/10b) audio mute, color depth, color space Control period: between video and data periods



HDMI (3)

Version 1.0 (2002)Maximum bandwidth of 4.95 Gbits/s (165 MHz) resolution of 19201200 (WUXGA) at 60 Hz

Version 1.1 (2004)Supports the DVD Audio format

Version 1.2 (2005)Supports the SACD (Super Audio CD) format Allows PC applications to only support the RGB color space

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HDMI (4)Version 1.3 (2006)

Bandwidth of 10.2 Gbits/s (340 MHz) resolution of 25601600 (WQXGA) at 60 HzSupports video images with more colors: 30, 36, or 48 bits/pixel (Deep Color, optional) Supports the Dolby TrueHD and DTS-HD Master Audio formats (optional) Two types of cables:

Category 1: up to 74.25 MHz (720p or 1080i) Category 2: up to 340 MHz (1080p or more)

A smaller connector: type C 12/17/2015


HDMI (5)

Version 1.4 (2009)The same bandwidth Resolutions of 4K2K: 38402160p (Quad HD) at 24, 25, or 30 Hz; 40962160p at 24 Hz HDMI Ethernet channel (100 Mbits/s)Audio return channel (ARC) Stereoscopic 3D formats Micro HDMI connector (type D) Automotive connection system

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HDMI (6)

Version 1.4a (2010) Specifies two new mandatory 3D formats

Version 1.4b (2011)Support for resolution of 19201080p, 120 Hz

The HDMI Forum (www.hdmiforum.org) has been created in 2011 Version 2.0 (2013)

Bandwidth has increased to 18 Gbits/s 4K2K resolutions at 60 Hz

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http://www.hdmiforum.org/


HDMI (7)HDMI connections

Single-link: pixel rate of 25 MHz .. 340 MHzDual-link: pixel rate of 25 MHz .. 680 MHz

Audio formats Uncompressed audio: PCM (Pulse Code Modul.)Sampling rates: 32; 44.1; 48; 96; 192 KHz Sample sizes: 16, 20, or 24 bitsCompressed audio: Dolby Digital, DTSLossless compressed audio: Dolby TrueHD, DTS-HD Master Audio

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HDMI (8)

Video formats Color spaces: RGB, YCbCr, xvYCC (optional) YCbCr: Y luminance and synchronization; Cb and Cr chroma (Cb = B Y, Cr = R Y)xvYCC: chroma values may correspond to negative RGB values more saturated colors Deep Color option: 10 bits, 12 bits, or 16 bits per color component

12 bits per color component: 68.7 billion colors

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HDMI (9)

CEC (Consumer Electronics Control) One-wire bidirectional serial bus used to transfer remote control commands

One Touch Play, System Standby, Tuner Control The user can control several devices connected through HDMI with a single remote control Devices can command each other without user intervention Alternative names: Anynet+ (Samsung), BRAVIA Link (Sony), EasyLink (Philips)

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HDMI (10)

ConnectorsType A: 19 pins, single-link connectionType B: 29 pins, dual-link connectionType C: mini-connector, 19 pins; can be connected to a Type A connector Type D: micro-connector, 19 pins (similar to micro-USB)Type E: for automobiles

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DisplayPort

DisplayPort Overview DisplayPort Architecture Embedded DisplayPort (eDP)

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Overview (1)

Developed by VESA (Video Electronics Standards Association) Intended to replace the DVI and VGA interfaces, and the LVDS (Low-Voltage Differential Signaling) protocol DisplayPort and HDMI interfaces may coexist in consumer electronics devices Versions of DisplayPort specifications

Version 1.0: published in 2006Version 1.2: published in 2009 Version 1.3: published in 2014

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Overview (2)

Main link (unidirectional) 1, 2, or 4 lanes The transmission protocol is based on micro packets pixel and audio data 8b/10b encoding the clock signal is embedded into the data stream

Auxiliary (AUX) channel (bidirectional) For device control and auxiliary data Default (standard) mode: Manchester encoding Fast mode: 8b/10b encoding

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Overview (3)

Allows external and internal connections For internal connections of portable computers: Embedded DisplayPort (eDP)

Copper or fiber optic cables DisplayPort signals are not compatible with DVI and HDMI signals

Optional dual-mode: DVI/HDMI signals can be generated with a simple converter The main link and AUX channel transmit 3 TMDS signals, a clock signal, and DDC data

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Overview (4)

Video data18, 24, 30, 36, or 48 bits per pixel (bpp) High resolutions, refresh rates, and color depths (up to 4096 2160, 24 bpp, 60 Hz)

Audio data 1..8 channels, uncompressed dataSampling rates: 48; 96; 192 KHz Sample sizes: 16 or 24 bits Maximum bit rate: 6.144 Mbits/s

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Overview (5)

Improvements in version 1.2 The bandwidth is doubled to 5.4 Gbits/s per lane higher resolutionsMultiple independent audio/video streams

Up to 63 A/V streams across a single connection Higher speed of the auxiliary channel

USB peripherals, video cameras, touch panel data Support for stereoscopic 3D images Addition of the Mini DisplayPort connector (Apple)

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Overview (6)

Improvements in version 1.3Bandwidth has been increased to 8.1 Gbits/s per lane (with 4 lanes: 32.4 Gbits/s)The bandwidth allows:

Two 4K monitors (4096 2160) at 60 HzA 4K stereo 3D displayA combination of 4K display and USB 3.0A 5K display (5120 2880) in RGB modeAn UHD 8K television display (7680 4320)

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Overview (7)

Connectors and cables 20 pins for external connectionsPowered connectors 3.3 V, 500 mA (~1.5 W) Cable length: up to 2 m for full bandwidth; 15 m for reduced bandwidth



DisplayPort


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DisplayPort Architecture (1)

Hot Plug Detect signal: 0 V or 3.3 V Indicates the presence or absence of a monitor May signal an interrupt from the monitor

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Main link (version 1.2)Clock signal frequency: 162; 270; 540 MHz Raw bit rates: 1.62; 2.7; 5.4 Gbits/s per lane Actual bit rates: 80% of raw bit rates (with 4 lanes: 5.18; 8.64; 17.28 Gbits/s) No. of displays supported (24 bpp, 60 Hz)

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Resolution 1280x768 1680x1050 1920x1080 2560x1600 4096x2160

Resolution name WXGA WSXGA HDTV WQXGA 4 K x 2K

No. of displays 10 5 4 2 1



Auxiliary channel Default mode: 1 Mbit/s (200 Kbits/s duplex) Fast mode: 720 Mbits/s (200 Mbits/s duplex) Used by the video source (GPU) to identify the capabilities of the monitor

Rendering capabilities: reading the monitor EDID memory Support of video content protection: HDCP (High-bandwidth Digital Content Protection) key exchanges

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DisplayPort Architecture (4)Allows to maintain link integrity

The monitor can notify the video source if data errors have occurred on the main link

Can transport auxiliary data Camera and microphone data, USB 2.0 data

Can be used to control monitor setting and operation

Supports the VESA MCCS (Monitor Control Command Set) standard: commands to control the properties of monitors I2C channel

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Example of application using AUX data transport

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DisplayPort


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Embedded DisplayPort (1)

Interface for connecting video adapters to display panels of portable computers

Typically, an interface based on the LVDS electrical protocol is used (e.g., LDI)

Based on the DisplayPort standard Same electrical interfaceSame basic digital protocol

Can use the same GPU video port as external DisplayPort connections

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Data transferred in main link: Pixel data and timing (e.g., pixel clock) Video format information (e.g., color space, bpp) ECC (Error Correction Code) for video data

Data transferred in AUX channel: EDID information Display control: brightness control; dynamic backlight control; frame rate control (FRC) Power state control

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Advantages compared to LVDS interfaces A single connector (data, control, power signals)

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Embedded DisplayPort (4)Reduced wire count simplified cable

Example for a resolution of 19201080, 24 bpp: 4 signal wires vs. 20 signal wires

Lower electromagnetic interference Enables new display panel control capabilities Reduced power consumption (e.g., display panel self-refresh feature) The packet-based protocol is extensible

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Enables highly integrated display controllers

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Summary (1)

GPUs are used to accelerate the geometric stage and the rendering stage of 3D graphics

Can be dedicated or integrated in a chipset GPUs contain a large number of processing cores, programmable for various shadings

The processing power of GPUs can also be used for applications that require vector operations

The CUDA architecture allows to access directly the GPU resources for general-purpose computing

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Summary (2)

The DVI interface has been designed for liquid crystal displays and digital projectors

Uses a serial interface for uncompressed video data and the TMDS signaling protocol

The HDMI interface is intended especially for consumer electronics devices

Allows to send video data, audio data, and control information over a single cableUses the same signaling protocol as the DVI interface, while providing a larger bandwidth

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Summary (3)

The DisplayPort interface will replace the VGA and DVI interfaces

Uses a new protocol based on micro packetsVideo and audio data are sent on a main link with up to 4 lanesControl information is sent on an auxiliary channel

The eDP interface is intended for internal display panels

Uses the same protocol as DisplayPortHas several advantages compared to LVDS

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Concepts, Knowledge (1)

Types of shader units contained by GPUsUnified shader unitsDedicated and integrated GPUsAdvantages and disadvantages of GPGPU computingThe CUDA architectureThread block in the CUDA architectureGrid of blocks in the CUDA architectureThe DDC channel used by the DVI interface

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Concepts, Knowledge (2)

The TMDS protocol and linkOverview of the HDMI interfaceFeatures of HDMI version 1.4The CEC (Consumer Electronics Control) busOverview of the DisplayPort interfaceImprovements in version 1.2 of DisplayPortFunctions of DisplayPort auxiliary channelOverview of the eDP interfaceAdvantages of the eDP interface

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Documents

6 . Graphics Adapters