52 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 1, JANUARY 2017

Generation of Higher Number of Voltage Levels byStacking Inverters of Lower Multilevel Structures

With Low Voltage Devices for DrivesViju Nair R, Student Member, IEEE, Arun Rahul S, Student Member, IEEE,

R. Sudharshan Kaarthik, Student Member, IEEE, Abhijit Kshirsagar, Student Member, IEEE,and K. Gopakumar, Fellow, IEEE

Abstract—This paper proposes a new method of generatinghigher number of levels in the voltage waveform by stacking mul-tilevel converters with lower voltage space vector structures. Animportant feature of this stacked structure is the use of low volt-age devices while attaining higher number of levels. This will findextensive applications in electric vehicles since direct battery driveis possible. The voltages of all the capacitors in the structure canbe controlled within a switching cycle using the switching stateredundancies (pole voltage redundancies). This helps in reducingthe capacitor size. Also, the capacitor voltages can be balancedirrespective of modulation index and load power factor. To verifythe concept experimentally, a nine-level inverter is developed bystacking two five-level inverters and an induction motor is run us-ing V/f control scheme. Both steady state and transient results arepresented.

Index Terms—Cascaded H-bridge inverter (CHB), flying capac-itor (FC), induction motor (IM) drive, low voltage devices, multi-level inverter (MLI), pulse width modulation (PWM), topology.

I. INTRODUCTION

IN order to obtain a better quality output voltage or currentwaveform, the switching frequency needs to increase in the

conventional two-level and three-level inverters. But in highvoltage and high power applications, there is a limitation onswitching frequency due to the associated switching lossesand power dissipation. Increasing the number of levels inthe output voltage reduces harmonic distortion in the outputphase voltage waveform [1]. Multilevel converters (MLC)are capable of generating higher levels in the output voltagewaveform with low voltage stress on the switches. In additionto better waveform quality and lower total harmonic distortionin the phase voltages, they also have advantages of reducedelectromagnetic interference, lower device voltage ratings,and lower switching frequency. Hence, they found widespreadapplications in motor drives, grid-tied converters, high-voltage

Manuscript received September 4, 2015; revised November 18, 2015; ac-cepted February 1, 2016. Date of publication February 11, 2016; date of currentversion September 16, 2016. Recommended for publication by Associate EditorB. Wang.

Viju Nair R, Arun Rahul S, A. Kshirsagar, and K. Gopakumar are with the De-partment of Electronic Systems Engineering, Indian Institute of Science, Banga-lore 560012, India (e-mail: vijuee@gmail.com; arun.rahul@dese.iisc.ernet.in;kabhijit@cedt.iisc.ernet.in; kgopa@dese.iisc.ernet.in).

R. Sudharshan Kaarthik is with the Concordia University, Montreal, QC H4B1R6, Canada (e-mail: sudharshan@cedt.iisc.ernet.in).

Digital Object Identifier 10.1109/TPEL.2016.2528286

dc transmission, reactive power compensation, wind energyconversion, and in many other high power applications [2].

Basic multilevel topologies include diode clamped multilevelinverter (DC-MLI), flying capacitor inverter (FC) and cascadedH-bridge inverter (CHB) [2], [3]. Three-level DC-MLI, com-monly known as neutral point clamped inverters (NPC) havebecome popular in industry. But for higher levels, more clamp-ing diodes are needed and also balancing the capacitors for en-tire modulation range is an issue [3]. It also suffers from seriousdrawback of unequal loss distribution among the semiconductorswitches which limits the switching frequency, output currentthrough the device and, hence, the power output [4]. To over-come the loss balancing problem, a modified version of NPC,known as the active NPC (ANPC) is introduced wherein theclamping diodes are replaced with the switches for balancinglosses among the switches [5].

FCs are another class of MLCs where in several charged ca-pacitors are used in generating higher number of voltage levels.The capacitor voltages can be maintained at the desired valuesusing the available switching state redundancies. Here again asthe number of levels are increased, more capacitors are needed.These electrolytic capacitors are the weakest link in an inverter.They add to the cost and also make the converter less reliable[6]. There is a tradeoff between the cost of clamping diodes inDC-MLI and the FCs for choosing the topologies for an applica-tion. At low switching frequencies, NPC becomes the obviouschoice because of the larger capacitor size requirement of FCs.

Another breed of power converters are the CHB converters[2]. They have the least component count compared to DC-MLIsand FCs especially due to absence of any clamping diodes orFCs. But CHB-based topologies reported with single dc supplyand multiple floating capacitors in each phase are dependent onload power factor and modulation index for the floating capacitorbalancing.

In an attempt to increase the number of levels, several newtopologies are introduced by modifying the above basic topolo-gies. By combining three-level ANPC and two-level cell, a newtopology with higher number of levels is developed [7]. Anotherpaper discusses about adding a common cross-converter stagebetween three-level ANPC and the FC and thereby generatingmore levels [8]. An interesting way of generating higher levels isdiscussed in [9] by feeding the induction machine with open endstator winding specially for drives application. Also many newhybrid topologies for specific applications are discussed in the

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R et al.: GENERATION OF HIGHER NUMBER OF VOLTAGE LEVELS BY STACKING INVERTERS OF LOWER MULTILEVEL STRUCTURES 53

Fig. 1. Power circuit for the proposed stacked nine-level inverter and its modulating signal for phase “a.” (a) Proposed 9 level inverter by stacking two 5 levelinverters, (b) Signal 1 for modulating the top structure and signal 2 for modulating the bottom structure along with the 8 carriers.

literature [10]–[13]. Stacked multicell converter was introducedto generate more levels. They use less number of capacitors butrequire more switches [14]. Multilevel structures of 5-level [15],9-level [13], and 17-level [16] have been reported with a sin-gle dc power supply by cascading conventional three-level FCtopology and capacitor-fed H bridges with inherent capacitorbalancing during inverter switching cycles.

In this paper, a new method of generating higher number ofvoltage levels by stacking MLCs of lower space vector struc-tures and having a single dc power supply as mentioned earlierwith low voltage devices is presented in detail for drives appli-cation. The concept can also be generalized for obtaining highervoltage levels. To verify the concept experimentally, a nine-levelinverter is developed by stacking two hybrid five-level invert-ers. The operation, notable features, and experimental resultsare discussed in the following sections.

II. INVERTER TOPOLOGY AND ITS OPERATION

The proposed inverter structure for a nine-level is shown inFig. 1(a). It is realized by stacking two five-level inverters ineach phase. Each of the five-level inverters are obtained by cas-cading a three-level FC inverter and a capacitor fed H bridge[15]. There are two selector switches in each phase to connectthe respective outputs to the induction machine. The FC in eachstructure has to be maintained at Vdc/4 and H-bridge capacitorshave to be maintained at Vdc/8, where Vdc is the dc link for aconventional two-level inverter. The structure overall has ninepairs of complimentary switches in each phase (S1-S1′, S2-S2′

... S9-S9′). Each of the switches in FC needs to block only Vdc/4and each of the switches in H bridge needs to block only Vdc/8.The top structure generates five pole voltages with respect to“O” such as levels 0, Vdc/8, 2Vdc/8, 3Vdc/8, 4Vdc/8. Bottomstructure also generates same five pole voltages with respect to“N.” But with respect to “N,” top structure generates five polevoltages which are Vdc/2 added with the above ones. So overallstacked structure generates nine pole voltages (VAN ) for phase

“a” such as levels 0, Vdc/8, 2 Vdc/8, 3 Vdc/8, 4 Vdc/8, 5 Vdc/8,6 Vdc/8, 7 Vdc/8, Vdc. Level-shifted carrier-based pulse widthmodulation (PWM) technique can be used for modulation[17], [18] of the proposed structure.

The operation of the stacked structure is as follows. Duringthe positive half cycle of the reference waveform [signal-1 inFig. 1(b)], the bottom structure is clamped to the midpoint “O”by turning ON S5, S6, S7, S8. Because of this operation, thevoltage rating of S9′ has to be Vdc/2 only. The selector switchesS9 is kept ON and S9′ is OFF during this period. Now the topstructure will switch to generate the required pole voltages. Sim-ilarly during the negative half cycle [signal-2 in Fig. 1(b)], thetop inverter structure is clamped to the midpoint “O” by turningON S1′, S2′, S3′, S4′. S9′ is kept ON and S9 is permanently keptOFF. Again S9 has to be rated for only Vdc/2. Here, the bot-tom structure will switch to generate the required pole voltages.So the selector switches are switching at line frequency only.The selector switches switch only during the zero crossing ofthe modulating signal. When the modulating signal is transitingfrom positive half cycle to negative half cycle, the upper selectorswitch has to go OFF and bottom selector switch has to turn ON.During this transition, it can be seen that all the top switches ofthe bottom structure (S5, S6, S7, S8) and all the bottom switchesof the top structure (S1′, S2′ S3′, S4′) are ON. If S9′ is turnedON just before S9 turns OFF, S9 can undergo a zero voltageswitching OFF. At the same time, S9′ is undergoing a zero volt-age switching ON as shown in Fig. 2. The darkened switchesin the figure are ON. The figures from (a) to (c) represent thistransition shown using the solid arrow. The reverse transitionfrom negative half cycle to positive half cycle can also be madezero voltage switching by going through the intermediate state(b), shown using the dotted arrow. Hence, the selector switchesdo not add to any switching loss.

The proposed structure for nine-level shown in Fig. 1(a) re-quires 54 switches although the six selector switches are switch-ing at line frequency without causing any switching loss and allthe remaining switches are operating only in one half cycle.

54 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 1, JANUARY 2017

Fig. 2. Transition states during zero crossing of modulating signal to eliminateswitching loss in the selector switches. The solid arrow shows transition frompositive to negative half cycle. The dotted arrow shows transition from negativeto positive half cycle. All the darkened switches are ON.

TABLE ISWITCHING STATE REDUNDANCIES FOR THE POLE VOLTAGES AND THEIR

EFFECT ON THE CAPACITOR VOLTAGES

S.No Switch States VA N Ia C1 C2

1 0000 0000 0 0 + U U2 0000 0011 0 0 + U U3 0000 0001 0 Vdc/8 + U D4 0000 0110 0 Vdc/8 + D C5 0000 1010 0 Vdc/8 + C C6 0000 0100 0 Vdc/4 + D U7 0000 0111 0 Vdc/4 + D U8 0000 1000 0 Vdc/4 + C U9 0000 1011 0 Vdc/4 + C U10 0000 0101 0 3Vdc/8 + D D11 0000 1001 0 3Vdc/8 + C D12 0000 1110 0 3Vdc/8 + U C13 0000 1100 0 Vdc/2 + U U14 0000 1111 0 Vdc/2 + U U15 0000 1111 1 Vdc/2 + U U16 0011 1111 1 Vdc/2 + U U17 0001 1111 1 5Vdc/8 + U D18 0110 1111 1 5Vdc/8 + D C19 1010 1111 1 5Vdc/8 + C C20 0100 1111 1 3Vdc/4 + D U21 0111 1111 1 3Vdc/4 + D U22 1000 1111 1 3Vdc/4 + C U23 1011 1111 1 3Vdc/4 + C U24 0101 1111 1 7Vdc/8 + D D25 1001 1111 1 7Vdc/8 + C D26 1110 1111 1 7Vdc/8 + U C27 1100 1111 1 Vdc + U U28 1111 1111 1 Vdc + U U

Note: “U” - Unaffected, “C”- Charging, “D” - Discharg-ing. “+” indicates current flow from inverter pole “A” tomachine neutral “n.” Switch State is defined as (S1 S2S3 S4 S5 S6 S7 S8 S9). “1” indicates switch is ON and“0” indicates switch is OFF.

Also this inverter has a modular structure, since the H bridgescan be bypassed if it fails and the inverter can still operate in theentire modulation range with lower number of voltage levels.

III. CAPACITOR VOLTAGE BALANCING

The capacitor voltages need to be maintained at the respec-tive levels for generating the pole voltages [19]. Each of the

Fig. 3. Switching redundancies available for a pole voltage. (a), (b), and(c) show current paths and charge and discharge of capacitors for switchingredundancies available for pole voltage of 5Vdc/8.

capacitor voltages in the topology has to be maintained at theirreference values. Hence, we define a small hysteresis band [15]for each of the capacitor voltage references and maintains thevoltages within this band using the available switching state re-dundancies. During a sampling instant, if the capacitor chargesand reaches the upper limit of the hysteresis band, immediatelyin the next sampling instant, the switching state is changed todischarge that capacitor. Since, the capacitors are designed con-sidering the switching frequency, peak of load current, and thevoltage deviation, the capacitor voltages always lie within thehysteresis band.

The steady-state operation of the top and bottom structure inFig. 1(a) are similar and, hence, the capacitor voltage balancingalgorithm is also similar. For the topology, there are switch-ing state redundancies available for generating a pole voltage.These redundancies can either charge or discharge a capacitorwhile maintaining the same pole voltage. These redundanciesare used to maintain the capacitor voltages. Table I lists all theswitching redundancies of all the pole voltages and also theireffect on the capacitor voltages for a particular direction of cur-rent. As the current reverses, the effect on capacitor voltagesalso reverses. Fig. 3 shows the use of switching state redun-dancies to charge and discharge a capacitor for a pole voltage(VAN ) of 5Vdc/8. For obtaining 5Vdc/8, the top structure onlyneeds to operate. Hence, only top structure is shown in Fig. 3.From the Table I, it can be seen that for the positive directionof current from “A” to “n,” the switching state (0001 1111 1)

R et al.: GENERATION OF HIGHER NUMBER OF VOLTAGE LEVELS BY STACKING INVERTERS OF LOWER MULTILEVEL STRUCTURES 55

TABLE IISWITCHING STATE SELECTION TABLE BASED ON CURRENT DIRECTION AND CAPACITOR VOLTAGE STATUS FOR PHASE “A”

Ia Ha 1 /Ha 3 Ha 2 /Ha 4 Switching state selection for the various pole voltages

Vdc/8 Vdc/4 3Vdc/8 5Vdc/8 3Vdc/4 7Vdc/8

+ 0 0 0000 1010 0 0000 1011 0 0000 1110 0 1010 1111 1 1011 1111 1 1110 1111 1+ 0 1 0000 0001 0 0000 1011 0 0000 1001 0 0001 1111 1 1011 1111 1 1001 1111 1+ 1 0 0000 0110 0 0000 0111 0 0000 1110 0 0110 1111 1 0111 1111 1 1110 1111 1+ 1 1 0000 0001 0 0000 0111 0 0000 0101 0 0001 1111 1 0111 1111 1 0101 1111 1- 0 0 0000 0001 0 0000 0111 0 0000 0101 0 0001 1111 1 0111 1111 1 0101 1111 1- 0 1 0000 0110 0 0000 0111 0 0000 1110 0 0110 1111 1 0111 1111 1 1110 1111 1- 1 0 0000 0001 0 0000 1011 0 0000 1001 0 0001 1111 1 1011 1111 1 1001 1111 1- 1 1 0000 1010 0 0000 1011 0 0000 1110 0 1010 1111 1 1011 1111 1 1110 1111 1

Note: “+” indicates current flow from inverter pole “A” to machine neutral “n.” Switch State is defined as (S1 S2 S3 S4 S5 S6 S7S8 S9) where “1” indicates switch is ON and “0” indicates switch is OFF. Ha x = “1” implies capacitor needs discharging and Ha x

= “0” implies capacitor needs charging to maintain the capacitor voltages within the hysteresis band where x = 1,2,3,4.

discharges C4 while C3 is unaffected which is shown in Fig. 3(a).To charge C4, the switching state (0110 1111 1) is used but itdischarges C3 which is shown in Fig. 3(b). Again to chargeC3, the switching state (1010 1111 1) is used but it chargesC4 also which is shown in Fig. 3(c). Whenever the capacitorvoltages crosses the hysteresis limits, switching states need tochange to maintain the capacitor voltages to desired values. Forpole voltages of 0, Vdc/2 and Vdc, none of the capacitors areaffected due to the current flow. For all other pole voltages,capacitor voltages change with current flow. Again the applica-tion of switching state depends on the present state of capacitorvoltages and the current directions. Hence, all the 12 capaci-tor voltages and currents are sensed. All the capacitor voltagesare compared with their references and capacitor voltage statuswhether it has exceeded the upper or lower limit of the hys-teresis band is given by Hax , where x = 1,2,3,4 respectively,for C1, C2, C3, and C4. Hax = “1” implies capacitor needsdischarging and Hax = “0” implies capacitor needs charging tomaintain the capacitor voltages within the hysteresis band. Ca-pacitor voltage status, the required pole voltage, and the currentdirection decide the switching state at any instant. Table II tellswhich switching state needs to be applied at any instant depend-ing on the above factors. Thus, instantaneous capacitor voltagecontrol using switch-state redundancies are possible within in-verter switching cycle. This is also independent of load powerfactor.

IV. GENERALIZATION

In the proposed nine-level inverter shown in Fig. 1(a), twofive-level inverters are stacked and each five-level inverter isgenerating half of the total inverter pole voltage. Experimentalresult showing the modulating signals and the generated polevoltages at 45 Hz operation are shown in Fig. 11. Trace 1 and2 of Fig. 11 show the total inverter pole voltage and the totalmodulating signal. Trace 4 and 5 of Fig. 11 show the modulatingsignal and the inverter pole voltage for the positive half cycle[from the top structure of Fig. 1(a)]. Trace 6 and 7 of Fig. 11show the modulating signal and the inverter pole voltage forthe negative half cycle [from the bottom structure of Fig. 1(a)].

Fig. 4. Modified power circuit to reduce number of switches for the proposedstacked nine-level inverter topology for phase “a.”

During the positive half cycle of the reference modulating signal(trace-2 of Fig. 11), the top selector switch is ON and during thenegative half cycle, the bottom selector switch is ON, to connectthe respective five-level stacked inverter modules to the output.The gate signal to the top selector switch is shown in trace-3 ofFig 11.

To reduce the number of switches, the structure in Fig. 1(a)can be modified as shown in Fig. 4. Here, the H bridge is madecommon to both the FC and the selector switches are connectedin between. Here, the H-bridge switches need to switch through-out the cycle. But they need to block voltage of Vdc/8 only[same as that in Fig. 1(a)]. Therefore, the switching losses arecontrolled. Also by using redundant H bridges, the system relia-bility can be improved. This method of stacking can be extendedto obtain higher voltage levels. In Fig. 5, a 49-level inverter isshown which is developed by stacking three FC and cascadingwith three capacitor fed H bridges (which are of lower voltageratings) through a three-level selector switch. It is shown that anFC cascaded with three H bridges can generate 17 levels [16].Since there are three stacked 17-level inverters, the reference

56 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 1, JANUARY 2017

Fig. 5. Power circuit schematic for generation of 49 levels by stacking three FC and cascading with three capacitor fed H bridges of low voltage ratings.

signal has to be divided into three parts and each will be used formodulating each of the 17-level inverter formed by cascadingthree capacitor fed H bridges with an FC. Hence, this stackedinverter is capable of generating 49 levels (two levels beingredundant).

As the number of voltage levels are increased by stacking,the devices need to block only lower voltages and the invertercan be driven directly from battery cells. Also due to the highernumber of voltage levels, switching frequency can be reducedand, therefore, higher efficiency is achievable. These advantageswill make the stacked inverter structure suitable for applicationin electric vehicles where the inverter can be driven directlyfrom the stacked low voltage batteries.

V. COMPARISON WITH OTHER INVERTER TOPOLOGIES

The modified nine-level inverter in Fig. 4 is compared withother existing nine-level topologies in this section. The modifiedproposed topology requires total of 42 switches. Out of which,six selector switches are switching at line frequency and whoseswitching losses can be minimized using the method discussedin the earlier section. The top and bottom FC is operating onlyfor one half of a fundamental cycle and is idle during the otherhalf.

In the conventional NPC and FC topologies for nine level,many clamping diodes and FCs are required for their oper-ation, respectively. In the proposed structure with less num-ber of floating capacitors, capacitor balancing can be donethroughout the modulation range irrespective of any load powerfactor, whereas in a nine-level NPC, there is a limitationon modulation index due to the capacitor unbalance problem[20], [21]. The basic conventional CHB structure, although

requires least number of components among the conventionaltopologies, needs more number of isolated dc sources. The openend nine-level configuration uses lesser number of switches butit has 12 Vdc/2 switches which have to operate throughout thecycle whereas in the proposed inverter, there are only six Vdc/2switches (selector switches) and they switch only once in a fun-damental cycle and their switching losses are also minimized.In addition, all the Vdc/4 switches in the FC of the proposed in-verter operate only in one half of fundamental cycle unlike in thecase of an open-end configuration. Again comparing with thestandard nine-level ANPC, the switching losses in the Vdc/2switches (selector switches) in the proposed inverter (6 com-pared to 12 in ANPC) are highly minimized with zero voltageswitching. Also the Vdc/4 switches in the proposed inverter (al-though 24 in number) operate only in one half of fundamentalcycle. The comparison is detailed in Table III.

VI. EXPERIMENTAL RESULTS

A three-phase, 415-V, 7.5-KW, 50-Hz induction motor (IM)is driven with the proposed nine-level inverter shown in Fig. 1(a)using open-loop V/f control scheme. The implementation blockdiagram is shown in Fig. 6. TMS320F28335 is the processorused for implementing the level-shifted PWM. All the capacitorvoltages and currents are sensed using the ADC channels inDSP. The PWM information, level data, capacitor voltage sta-tus, and the current directions are encoded and send to Spartan 3XCS3200 FPGA module which is used for selecting the appro-priate switching state from the lookup table stored in the FPGA.Dead time of 2.5 μs is provided between the complimentary sig-nals. All the capacitor voltages are maintained within a ripple of2%. The capacitance value is given by, C = IpTs/ΔVc where

R et al.: GENERATION OF HIGHER NUMBER OF VOLTAGE LEVELS BY STACKING INVERTERS OF LOWER MULTILEVEL STRUCTURES 57

TABLE IIICOMPARISON OF NINE-LEVEL INVERTER TOPOLOGIES

Topologies IGBT Capacitors Clamping diodes DC sources

Vdc/2 Vdc/4 Vdc/8 Vdc/4 Vdc/8 3Vdc/8 Vdc/2 Vdc Vdc/2 Vdc/8

Proposed (see Fig. 4) 6 24 12 6 3 0 0 0 0 2 0NPC 0 0 48 0 8 0 0 168 1 0 0FC 0 0 48 0 84 0 0 0 1 0 0Conventional CHB 0 0 48 0 0 0 0 0 0 0 12Open end 9L [9] 12 12 12 0 9 0 0 0 0 2 0Standard 9L-ANPC 12 0 24 3 3 3 0 0 0 2 0

Fig. 6. Block diagram representation of the implemented inverter topology.

C is the capacitance value of C1, C2, C3, C4 in all phases,Ip is the peak load current, ΔVc is the peak to peak voltageripple, and Ts is inverter switching time. Capacitance value of2200 μF is selected for all the capacitors in the experiment.Synchronous PWM technique is implemented for the proposedinverter. Number of samples per cycle is taken as 48 for funda-mental frequency ranging from 35 to 45 Hz, 60 for 27 to 35 Hz,72 for 21 to 27 Hz, and 90 for 17 to 21 Hz, 120 for 13 to 17 Hz,and 180 for 6 to 13 Hz. Samples per cycle should be an inte-gral multiple of 6 so that waveforms will have both half-waveand three-phase symmetry. IM is run at frequencies 10, 20, 30,and 45 Hz with reference voltage tracing different layers in thespace vector structure. Experimental results showing the inverterphase voltages (trace-1), pole voltages with respect to midpoint“O” (trace-2), the FC voltage ripple of top structure (trace-3)and phase current (trace-4) for “a” phase are shown for 10-Hzoperation [see Fig. 7(a)], 20-Hz operation [see Fig. 7(b)], 30-Hzoperation [see Fig. 7(c)], and 45-Hz operation [see Fig. 7(d)].It can be seen in the above figures that as the speed commandis increased from 10 to 45 Hz, the number of levels in the polevoltage waveform (trace-2) increases from 3 to 9. All the experi-mental results shown are at no load since no load operation givesworst case current ripple. Capacitor voltage ripple for three ofthe capacitors (traces 1-3) during 10 and 45 Hz operation are

shown separately in Fig. 8. Transient results showing the ac-celeration of motor from 10 to 45 Hz in 2.5 s and the capacitorvoltages during this transient are shown in Fig. 9(a). Duringthe acceleration, the phase voltage waveform (trace-1) shows alinear rise and the phase current (trace-4) remains constant. Thecapacitor voltages (traces 2, 3) are controlled within the bandduring the operation. To test the capacitor voltage balancing al-gorithm, the balancing algorithm is intentionally disabled at Tdand then enabled at Te as shown in Fig. 9(b). It can be noticedthat capacitor voltages (traces 2, 3) return to their reference val-ues in less than 1 s at Tss. Capacitor balancing algorithm takescare of the capacitor voltage build up during starting. Hence,no precharging circuitry is needed. Experimental result show-ing the capacitor voltage build up during starting is shown inFig. 10(a). The voltages of the capacitors in FC and H bridge oftop structure (traces 2,3) are building up to their desired valuesin less than 4 s. In Fig. 10(b), the reduced switching of FC andthe H bridge to maintain the respective capacitor voltages todesired values at 45-Hz operation is shown. Trace-1 shows thetotal modulating signal. Traces-2 and 3 show the top and bottomFC pole voltages with respect to midpoint “O.” Traces-4 and 5show the top and bottom H-bridge switchings. It can also be ob-served from Fig. 10(b) that the two stacked cells are switchingonly for one half of the fundamental cycle.

58 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 1, JANUARY 2017

Fig. 7. Motor Phase voltage (VAn ), Inverter pole voltage (VAO ), Capacitorvoltage ripple (ΔVc3 ), Phase current (Ia ) for phase A for different modulationindices. (b), (c) and (d) y-axis 1) VAn : 100 V/div, 2) VAO : 100 V/div 3) ΔVc3 :5 V/div 4) Ia : 2 A/div. (a) y-axis 1) VAn : 50 V/div, 2) VAO : 50 V/div 3)ΔVc3 : 5 V/div 4) Ia : 2 A/div. (a) 10 Hz operation, x–axis: 20 ms/div, (b) 20 Hzoperation, x–axis: 10 ms/div, (c) 30 Hz operation, x–axis: 10 ms/div, (d) 45 Hzoperation, x–axis: 5 ms/div.

Fig. 8. Capacitor voltages ripple and motor phase current for “a” phase.y-axis: 1) ΔVc1 : 5 V/div, 2) ΔVc3 : 5 V/div, 3) ΔVc4 : 5 V/div, 4) Ia : 2 A/div.(a) 10 Hz, x-axis: 20 ms/div. (b) 45 Hz, x-axis: 10 ms/div.

Fig. 9. (a) Motor acceleration. (b) Intentional capacitor unbalancing. y-axes:1) Motor Phase voltage (VAn ), 2) Capacitor voltage Vc4 , 3) Capacitor voltageVc3 , 4) Phase current (Ia ).

Fig. 10. (a) Motor starting transients. y-axis: 1) Motor Phase voltage (VAn ),2) Capacitor voltage Vc3 , 3) Capacitor voltage Vc4 , 4) Phase current (Ia ).(b) Individual FC pole voltages (traces-2,3) and Individual H-bridge switchings(traces-4,5). 1) Modulating signal, 2) VWO , 100V/div, 3) VYO , 100V/div, 4)VXW , 20V/div, 5) VZY , 50V/div.

Fig. 11. Modulating signals and the generated pole voltages by each of thestacked cells and the inverter at 45 Hz operation. x-axis: 10 ms/div. 2) VAO ,100 V/div, 3) Gating signal, 50 V/div, 5) VXO , 100 V/div, 7) VZO , 100 V/div.

VII. CONCLUSION

In this paper, a new method of generating higher numberof voltage levels by stacking MLCs having lower space vectorstructures is presented. Here, each of the stacked inverter ishaving only one dc supply. The proposed stacked MLI has amodular structure which is realized by stacking the FC and cas-cading it with series-connected capacitor fed H bridges. Sincethe voltage across the H-bridge switches are low, the switchingloss can be further reduced. Also the H bridges can be bypassedif it fails. Thus, using this system has an improved reliableoperation. Also when one of the FC fails, inverter can still beoperated with reduced voltage and power levels. The concept ofstacking can be generalized to obtain higher voltage levels. Asthe number of levels increases, blocking voltages of switchesreduces and the proposed structure can be fed from low voltagebattery cells. Also, higher number of voltage levels implylower switching frequency and, therefore, higher efficiency,which makes it suitable for application in electric vehicles.Hysteresis based capacitor voltage balancing algorithm is usedto maintain the capacitor voltages irrespective of modulationindex and load power factor. Detailed experimental results,using a stacked nine-level inverter, showing the steady-stateoperation at different frequencies and the transient results,ensure that the proposed structure will be a viable scheme forhigh power applications with improved reliability.

REFERENCES

[1] A. Nabae, I. Takahashi, and H. Akagi, “A new neutral-point-clampedPWM inverter,” IEEE Trans. Ind. Appl., vol. IA-17, no. 5, pp. 518–523,Sep. 1981.

[2] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. Franquelo, B. Wu,J. Rodriguez, M. Perez, and J. Leon, “Recent advances and industrialapplications of multilevel converters,” IEEE Trans. Ind. Electron., vol. 57,no. 8, pp. 2553–2580, Aug. 2010.

[3] J. Rodriguez, S. Bernet, P. Steimer, and I. Lizama, “A survey on neutral-point-clamped inverters,” IEEE Trans. Ind. Electron., vol. 57, no. 7,pp. 2219–2230, Jul. 2010.

[4] P. Barbosa, P. Steimer, J. Steinke, L. Meysenc, M. Winkelnkemper, and N.Celanovic, “Active neutral-point-clamped multilevel converters,” in Proc.IEEE Power Electron. Spec. Conf., Jun. 2005, pp. 2296–2301.

[5] T. Bruckner, S. Bernet, and H. Guldner, “The active NPC converter andits loss-balancing control,” IEEE Trans. Ind. Electron., vol. 52, no. 3,pp. 855–868, Jun. 2005.

R et al.: GENERATION OF HIGHER NUMBER OF VOLTAGE LEVELS BY STACKING INVERTERS OF LOWER MULTILEVEL STRUCTURES 59

[6] H. Wang and F. Blaabjerg, “Reliability of capacitors for dc-link appli-cations in power electronic converters: An overview,” IEEE Trans. Ind.Appl., vol. 50, no. 5, pp. 3569–3578, Sep. 2014.

[7] S. Pulikanti and V. Agelidis, “Hybrid flying-capacitor-based active-neutral-point-clamped five-level converter operated with SHE-PWM,”IEEE Trans. Ind. Electron., vol. 58, no. 10, pp. 4643–4653, Oct. 2011.

[8] T. Chaudhuri, P. Steimer, and A. Rufer, “Introducing the common crossconnected stage (c3s) for the 5l ANPC multilevel inverter,” in Proc. IEEEPower Electron. Spec. Conf., Jun. 2008, pp. 167–173.

[9] P. Rajeevan, K. Sivakumar, K. Gopakumar, C. Patel, and H. Abu-Rub, “Anine-level inverter topology for medium-voltage induction motor drivewith open-end stator winding,” IEEE Trans. Ind. Electron., vol. 60, no. 9,pp. 3627–3636, Sep. 2013.

[10] G. Adam, I. Abdelsalam, K. Ahmed, and B. Williams, “Hybrid multilevelconverter with cascaded h-bridge cells for HVDC applications: Operatingprinciple and scalability,” IEEE Trans. Power Electron., vol. 30, no. 1,pp. 65–77, Jan. 2015.

[11] Z. Zheng, K. Wang, L. Xu, and Y. Li, “A hybrid cascaded multilevelconverter for battery energy management applied in electric vehicles,”IEEE Trans. Power Electron., vol. 29, no. 7, pp. 3537–3546, Jul. 2014.

[12] J. Li, S. Bhattacharya, and A. Huang, “A new nine-level active NPC(ANPC) converter for grid connection of large wind turbines for distributedgeneration,” IEEE Trans. Power Electron., vol. 26, no. 3, pp. 961–972,Mar. 2011.

[13] P. Rajeevan and K. Gopakumar, “A reduced device-count hybrid multilevelinverter topology with single dc source and improved fault tolerance,” EPEJ., vol. 23, 2013.

[14] G. Gateau, T. Meynard, and H. Foch, “Stacked multicell converter (SMC):Properties and design,” in Proc. IEEE 32nd Annu. Power Electron. Spec.Conf., 2001, vol. 3, pp. 1583–1588.

[15] P. Roshankumar, P. Rajeevan, K. Mathew, K. Gopakumar, J. Leon, andL. Franquelo, “A five-level inverter topology with single-dc supply bycascading a flying capacitor inverter and an h-bridge,” IEEE Trans.PowerElectron., vol. 27, no. 8, pp. 3505–3512, Aug. 2012.

[16] P. Kumar, R. Kaarthik, K. Gopakumar, J. Leon, and L. Franquelo,“Seventeen-level inverter formed by cascading flying capacitor and float-ing capacitor H-bridges,” IEEE Trans. Power Electron., vol. 30, no. 7,pp. 3471–3478, Jul. 2015.

[17] R. Kanchan, M. Baiju, K. Mohapatra, P. Ouseph, and K. Gopakumar,“Space vector PWM signal generation for multilevel inverters using onlythe sampled amplitudes of reference phase voltages,” IEE Proc. Electr.Power Appl., vol. 152, no. 2, pp. 297–309, Mar. 2005.

[18] B. McGrath and G. Holmes, “Multicarrier PWM strategies for multilevelinverters,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 858–867, Aug.2002.

[19] B. McGrath and D. Holmes, “Natural capacitor voltage balancing fora flying capacitor converter induction motor drive,” IEEE Trans. PowerElectron., vol. 24, no. 6, pp. 1554–1561, Jun. 2009.

[20] S. Guanchu, K. Lee, L. Xinchun, and L. Chongbo, “New neutral point bal-ancing strategy for five-level diode clamped converters used in statcom ofwind energy conversion systems,” in Proc. IEEE 6th Int. Power Electron.Motion Control Conf., May. 2009, pp. 2354–2358.

[21] N. Celanovic and D. Boroyevich, “A comprehensive study of neutral-point voltage balancing problem in three-level neutral-point-clamped volt-age source PWM inverters,” IEEE Trans.Power Electron., vol. 15, no. 2,pp. 242–249, Mar. 2000.

Viju Nair R. (S’15) received the B.Tech. degreein electrical and electronics engineering from MarAthanasius College of Engineering, Kothamangalam,India, in 2009, and the M.Tech. degree in electricalengineering with specialization in power electron-ics and power systems from the Indian Institute ofTechnology, Bombay, India, in 2013. He is currentlyworking toward the Ph.D. degree in the Departmentof Electronic Systems Engineering, Indian Instituteof Science, Bangalore, India.

His research interests include high power convert-ers for motor drives and grid integration of renewable energy sources.

Arun Rahul S. (S’15) received the B.Tech. degreein electrical engineering from the Rajiv Gandhi Insti-tute of Technology, Kottayam, India, in 2008, and theM.Tech degree in machine drives and power electron-ics from the Indian Institute of Technology, Kharag-pur, India, in 2011. He is currently working towardthe Ph.D. degree in the Department of ElectronicsSystems Engineering (formerly CEDT), Indian Insti-tute of Science, Bangalore.

His research interests include multilevel powerconverters, motor drives, power converters for renew-

able energy conversion, and power quality.

R. Sudharshan Kaarthik (S’10) received theB.Tech. degree from the National Institute of Tech-nology, Rourkela, India, in 2010, and the M.Tech.and Ph.D. degrees from the Department of ElectronicSystems Engineering (formerly CEDT), Indian Insti-tute of Science, Bangalore, India, in 2012 and 2015,respectively.

He is currently a Postdoctoral Fellow in ConcordiaUniversity, Canada. His research interests include theareas of PWM converters and motor drives.

Abhijit Kshirsagar (S’04) received the B.Tech. de-gree from VIT University, Vellore, India, in 2008,and the M.Tech. degree from the Indian Institute ofScience, Bangalore, India, in 2010. He is currentlyworking toward the Ph.D. degree in the Departmentof Electronic Systems Engineering (formerly CEDT),Indian Institute of Science, Bangalore, India.

His research interests include power converters,renewables, and embedded systems.

K. Gopakumar (M’94–SM’96–F’11) received theB.E., M.Sc. (Eng.), and Ph.D. degrees in electricalengineering from the Indian Institute of Science, Ban-galore, India, in 1980, 1984, and 1994, respectively.

He was with the Indian Space Research Organi-zation, Bangalore, India, from 1984 to 1987. He cur-rently holds the position of Professor at the Depart-ment of Electronics System Engineering (formerlyCenter for Electronics Design and Technology), In-dian Institute of Science. His research interests in-clude PWM converters and high power drives.

Dr. Gopakumar is a Fellow of the Institution of Electrical and Telecommu-nication Engineers India and Indian National Academy of Engineers. He is cur-rently a Coeditor-in-Chief of IEEE TRANSACTION ON INDUSTRIAL ELECTRONICS

and also a Distinguished Lecturer of IEEE Industrial Electronics Society.