4 December 2002, ITRS 2002 Update Conference The International Technology Roadmap for Semiconductors 2002 Update Summary Overall Roadmap Technology Characteristics

4 December 2002, ITRS 2002 Update Conference

The International Technology Roadmap for Semiconductors

2002 Update Summary

Overall Roadmap Technology Characteristics (ORTC) Overview12/04/02

Alan Allan / Intel Corporation


Key Messages• The Technology Roadmap for Semiconductors has

guided the R&D activities for the last 10 years!• 2003 marks the year of 100nm or below: Welcome to the

challenges of the Nanotechnology Era! • NO CHANGES from the 2001 Scaling targets and Chip Size

models– First Time Since 1994!– Economics (Chip Size) consistent with historical trends through 2004– Performance (Frequency) consistent with historical trends through 2005– Density (Functionality) consistent with historical trends through 2004

• …..but need “breakthroughs” after 2005!• We will continue to look for evidence of Industry Trend

Acceleration/Deceleration in 2003


Production Ramp-up Model and Technology NodeV

olu

me

(Par

ts/M

on

th)

1K

10K

100K

Months0-24

1M

10M

100M

Alpha

Tool

12 24-12

Development Production

Beta

Tool

Production

Tool

First

Conf.

Papers

First Two Companies

Reaching Production V

olu

me

(Waf

ers/

Mo

nth

)

2

20

200

2K

20K

200K

Source: 2001 ITRS - Exec. Summary

2002 ITRS Update – (No Changes from 2001 ITRS)


MOS Transistor Scaling(1974 to present)

S=0.7[0.5x per 2 nodes]

Pitch Gate



SCALING Timing Highlights• Technology Node and Industry Pace: The DRAM Half-

Pitch (HP) on a 3-year-cycle trend after 130nm/2001

• The MPU/ASIC HP remains on a 2-year-cycle trend until 90nm/2004, and then remains equal to DRAM HP (3-year cycle)

• The MPU Printed Gate Length (Pr GL ) and Physical Gate Length (Ph GL) will be on a 2-year-cycle until 45nm and 32nm, respectively, until the year 2005

• The MPU Pr GL and Ph GL will proceed parallel to the DRAM/MPU HP trends on a 3-year cycle beyond the year 2005

• The ASIC/Low Power Pr/Ph GL is delayed 2 years behind MPU Pr/Ph GL

• ASIC HP equal to MPU HP


ITRS Roadmap Acceleration Continues...Half Pitch

10

100

1000

1995 1998 2001 2004 2007 2010 2013 2016

Year of Production

Tech

no

log

y N

od

e -

DR

AM

Hal

f-P

itch

(n

m)

2001 DRAM ½ Pitch

2001 MPU/ASIC ½ Pitch

1999 ITRS DRAM Half-Pitch

2-year Node Cycle

3-year Node Cycle

Source: 2001 ITRS - Exec. Summary, ORTC



ITRS Roadmap Acceleration Continues…Gate Length

10

100

1000

1995 1998 2001 2004 2007 2010 2013 2016

Year of Production

Tech

no

log

y N

od

e -

DR

AM

Hal

f-P

itch

(n

m)

2001 MPU Printed Gate Length

2001 MPU Physical Gate Length

1999 ITRS MPU Gate-Length

2-year Cycle

3-year Cycle

Source: 2001 ITRS - Exec. Summary, ORTC


1

10

100

1,000

10,000

100,000

1980 1985 1990 1995 2000 2005 2010 2015

Fre

qu

ency

(M

Hz)

2X / 4 Years

2X / 2 - 2½ Years

2X / 2½ Years

MPU Clock Frequency Historical Trend:

Gate Scaling, Transistor Design contributed ~ 17-19%/year

Architectural Design innovation contributed additional ~ 21-13%/year

Actual Scaling Acceleration, Or Equivalent Scaling Innovation Needed to maintain historical trend

Historical <- > 1999 ITRS 2001 ITRS

MPU Clock Frequency Actual vs ITRS

Sources: Sematech, 2001 ITRS ORTC 28



1.59/yr

1.41/yr

0.71/yr

0.74/yr

1.26/yr

1.47/yr

1.34/yr

2001 ITRS DRAM Model Trend Analysis (cont.)DRAM Historical Trends vs. ITRS (3-Year Node Cycle]

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

1980 1985 1990 1995 2000 2005 2010 2015 2020

Year of First Production

Cell Area (CA) (u2)

Cell Area Efficiency(CAE)

bits (Nb) (M)

Chip Size (mm2)

Ave Density(Gbits/cm2)

Source: SEMATECH, ITRS, FEP TWG

History <= 2000 => Forecast [2001 I TRS]

CAE

Chip Size = (CA

x N)/CAE

N bits/chip

CA = Cell Area =

A x f 2̂Ave Density =

N/Chip Size



572mm2 Litho Field Size

286mm2 2 per Field Size

800mm2 Litho Field Size

MPU Chip size (mm2) – Historical Trends vs 2001 ITRS Model*

1000

100

101980 1985 1990 1995 2000 2005 2010 2015 2020

CP MPU 140mm2

HP MPU 310mm2

CP Shrink 70mm2

* ITRS Design TWG MPU Transistors/Chip Model: ~2x/Node = 2x/2yrs from 1999 - 2001; then 2x/3yrs from 2001- 2016

*1999 Leading-Edge .18u CP MPU:

512KB (28Mt [58.3%] x 1.18u2/t = 34mm2) + 20Mt Logic x 5.19u2/t = 104mm2 + 2mm2 OH= 106mm2 = Total 48Mt x ave 2.92u2/t = 140mm2

*1999 Leading- Edge .18u HP MPU:

2MB (113Mt [81.9%] x 1.18u2/t = 135mm2) + 25Mt Logic x 5.19u2/t = 130mm2 + 45mm2 OH= 310mm2 = Total 138Mt x ave 2.25u2/t = 310mm2



Density Trends (bits/cm2, t/cm2) – ITRS / ORTC

1

10

100

1000

10000

100000

1E+06

1E+07

1E+08

1E+09

1E+10

1E+11

1985

1986

1987

1988

1989

1990

1991

1992

1993

1994

1995

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

2012

2013

2014

2015

ITRS01 Tx/cm2

ITRS01 bits/cm3

Logic and DRAM densities

DRAM

uP

P99c / .18u 28Mt SRAM

+20MT Logic = 48Mt

/ 1.4cm2

= 34Mt/cm2

256M / .18u 268Mbits

/ 1.3cm2

= 200Mbits/cm2

"Moore's Law"Target:

2x / 2years Functions/Chip at FLAT Chip Size &

Cost =

+ 41% / yr Density

- 29% / yr Cost/Fn

"Moore's Law"Target:

2x / 1.5years Functions/Chip at

1.4x/3yr Chip Size & Cost =

+ 41% / yr Density

- 29% / yr Cost/Fn


ITRS 2001 “Moores Law” Targets:

DRAM: 2x/2.5yrs; 1.05x/yr Chip Size

MPU: 2x/node = 2x/3years; FLAT

Chip Size


Key Messages• The Technology Roadmap for Semiconductors has

guided the R&D activities for the last 10 years!• 2003 marks the year of 100nm or below: Welcome to the

challenges of the Nanotechnology Era! • NO CHANGES from the 2001 Scaling targets and Chip Size

models– First Time Since 1994!– Economics (Chip Size) consistent with historical trends through 2004– Performance (Frequency) consistent with historical trends through 2005– Density (Functionality) consistent with historical trends through 2004

• …..but need “breakthroughs” after 2005!• We will continue to look for evidence of Industry Trend

Acceleration/Deceleration in 2003


Backup


Production Definition


Technology Node vs Actual Wafer Production Capacity

0.01

0.1

1

10

1995 2000 2005Year

1996 1997 1998 20011999 200420032002

W.P.C. W.P.C.W.P.C. W.P.C. W.P.C.W.P.C.

Fe

atu

re S

ize

(H

alf

Pit

ch)

(m

)

0.01

0.1

1

10

1995 2000 2005Year

1996 1997 1998 20011999 200420032002

W.P.C. W.P.C.W.P.C. W.P.C. W.P.C.W.P.C.

ITRS Technology Node

W.P.C.= Total Worldwide WaferProduction Capacity

(Relative Value)

Sources:

1995 to 1999: SICAS

2000: Yano Research Institute& SIRIJ

Fea

ture

Siz

e o

f T

ech

no

log

y >0.7 m

0.4-0.7 m

<0.4m

>0.8 m

0.5-0.8 m

0.35-0.5 m

0.25- 0.35 m

0.2 - 0.25 m

0.18 - 0.2 m

<0.18 m

For 1995-1999

For 2000




Scaling – Technology

Nodes


Half Pitch (= Pitch/2) Definition

(Typical

MPU/ASIC)(Typical

DRAM)

Poly

Pitch Metal

Pitch




Scaling Calculator + Node Cycle Time:

250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16

0.5x

0.7x

0.7x

N N+1

N+2

Node Cycle Time (T yrs):

*CARR(T) =

[(0.5)^(1/2T yrs)] - 1

CARR(3 yrs) = -10.9%

CARR(2 yrs) = -15.9%

* CARR(T) = Compound Annual Reduction Rate

(@ cycle time period, T)

Log

Hal

f-P

itch

Linear Time

1994 NTRS - .7x/3yrs

Actual - .7x/2yrs




2001 ITRS ORTC Node Tables – w/Node Cycles

Table 1a Product Generations and Chip Size Model Technology Nodes—Near-term Years

YEAR OF PRODUCTION 2001 2002 2003 2004 2005 2006 2007

DRAM ½ Pitch (nm) 130 115 100 90 80 70 65

MPU/ASIC ½ Pitch (nm) 150 130 107 90 80 70 65

MPU Printed Gate Length (nm) †† 90 75 65 53 45 40 35

MPU Physical Gate Length) (nm) 65 53 45 37 32 28 25

ASIC/Low Power Printed Gate Length (nm) †† 130 107 90 75 65 53 45

ASIC/Low Power Physical Gate Length) (nm) 90 75 65 53 45 37 32

Table 1b Product Generations and Chip Size Model Technology Nodes—Long-term years

YEAR OF PRODUCTION 2010 2013 2016

DRAM ½ Pitch (nm) 45 32 22

MPU/ASIC ½ Pitch (nm) 45 32 22

MPU Printed Gate Length (nm) †† 25 18 13

MPU Physical Gate Length) (nm) 18 13 9

ASIC/Low Power Printed Gate Length (nm) †† 32 22 16

ASIC/Low Power Physical Gate Length) (nm) 22 16 11

[3-Year Node Cycle]

[2-year cycle] [3-year cycle]

[3-year cycle]

[Node = DRAM Half-Pitch (HP)]

[MPU Gate Length Cycle (GL)]:

[MPU HP/GL Cycle]:



2001 ITRS ORTC MPU Frequency Tables – w/Node CyclesTable 4c Performance and Package Chips: Frequency On-Chip Wiring Levels— Near -Term Years

YEAR OF PRODUCTION 2001 2002 2003 2004 2005 2006 2007

DRAM ½ Pitch (nm) 130 115 100 90 80 70 65

MPU/ASIC ½ Pitch (nm) 150 130 107 90 80 70 65

MPU Printed Gate Length (nm) 90 75 65 53 45 40 35

MPU Physical Gate Length (nm) 65 53 45 37 32 28 25

Chip Frequency (MHz)

On-chip local clock 1,684 2,317 3,088 3,990 5,173 5,631 6,739

Chip-to-board (off-chip) speed (high-performance, for peripheral buses)[1] 1,684 2,317 3,088 3,990 5,173 5,631 6,739

Maximum number wiring levels—maximum 7 8 8 8 9 9 9

Maximum number wiring levels—minimum 7 7 8 8 8 9 9

Table 4d Performance and Package Chips: Frequency, On-Chip Wiring Levels—Long-term Years

YEAR OF PRODUCTION 2010 2013 2016

DRAM ½ Pitch (nm) 45 32 22

MPU/ASIC ½ Pitch (nm) 45 32 22

MPU Printed Gate Length (nm) 25 18 13

MPU Physical Gate Length (nm) 18 13 9

Chip Frequency (MHz)

On-chip local clock 11,511 19,348 28,751

Chip-to-board (off-chip) speed (high-performance, for peripheral buses)[1] 11,511 19,348 28,751

Maximum number wiring levels—maximum 10 10 10

Maximum number wiring levels—minimum 9 9 10

[2-Yr GL Cycle; then 3-Yr]

[3-year cycle]

Sources: 2001 ITRS

ORTC

[MPU Gate Length Cycle (GL)]:2002 ITRS

Update – (No Changes from 2001 ITRS)


Chip Size Trends


Chip Size Model Calculation Illustration - DRAM

(Cell Array Area / Chip Size) x 100 = Cell Array Efficiency (%):

Chip Size = (A x f 2 x Nbits)/CAE

f 2

Cell Area = Cell Area Factor (A) x f 2 ; f = technology node (half-pitch) feature size; Example: Cell Area = 2x4 x f 2 = 8 f 2

Cell Array Area = Cell Area x number of bits (2 n)


2001 ITRS DRAM Model Trend Analysis

3-yr Node Cycle vs 2-yr0.89/yr

0.95/yr

0.71/yr

0.74/yr

DRAM Historical Trends vs. ITRS [3-Year Node Cycle]

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1980 1985 1990 1995 2000 2005 2010 2015 2020

Year of First Production

Technology Node(f) (nm)

f^2 (u2)

Cell Area Factor (A)

Cell Area (CA) (u2)

Source: SEMATECH, ITRS, FEP TWG

History <= 2000 => Forecast [2001 I TRS]

CA = Cell Area =

A x f 2̂

f

f 2̂

A


[Cell Design Improvement Factor]


DRAM Cell Area History / 2001 ITRS ModelDRAM Cell Area

0.001

0.01

0.1

1

10

1986 1989 1992 1995 1998 2001 2004 2007 2010 2013 2016

Year

Cel

l Are

a (u

2)

History <-- 2000 --> F'cast

1Gb / 2Gb CAF (A) = 6

4Gb / 8Gb CAF (A) = 6 16Gb / 32Gb

CAF (A) = 4

64 Gb/128GbCAF (A) = 4

64 Mb CAF (A) = 11 =

1.3/.35^2; .71/.25^2

16->10 (per FEP)

4 Mb CAF (A) = 22 =

11/.71^226 (per FEP)

16 Mb CAF (A) = 16 =

4.0/.5^221 (per FEP)

1 Mb (est.)

CAF (A) = 31 =

31/1.0^229 (per FEP)

128/256Mb CAF (A) = 8.0 =

.35/.21^2; .26/.18^210 -> 8 (per FEP)

Actual Scaling Acceleration, Or Equivalent Scaling Innovation Needed to maintain historical trend

DRAM Cell Size Historical Trend: Half-Pitch Scaling, contributed ~ .5x / 3 years [(.7x)^2] Cell Design innovation contributed additional ~ .7x / 3 years

0.35x / 3 Years –29%/yr

Historical Actual <- > 2001 ITRS

Sources: Sematech, 2001 ITRS ORTC

512Mb



ORTC Table TWG Line Item Ownership Chk's by L. Wilson/A.Allan

ORTC Table TWG Owner TWG Table

- Table 1a-d DRAM Model FEP [DRAM Model] -no change

- Table 1f-j MPU Model Design [MPU Model] -no change

- Table 2a,b Litho Field Size Table unchgd Litho 57a,b Table not changed

Wafer Size line item unchgd FEP, FI 50a,b AA to review-done-no change

- Table 3a,b # of Chip I/O’s Table unchgd Test, Design 24a,b Table not changed

# of Package Pins Table unchgd Test, A&P 25a,b Table not changed

# of Package Balls HP updtd-NOchg to# A&P, Test 75a,b AA to confirm-done-no change

- Table 4a,b Chip Pad Pitch Flip chip area array updtd A&P 77 AA to confirm -done/updated

Cost-Per-Pin Low Cost updtd A&P 75a,b AA to confirm -done/updated

- Table4c,d Chip Frequency Design, PIDs [MPU Model] -no change

Chip-to-Board Frequency Design, A&P [MPU Model] -no change

Max # Wire Levels line item unchgd Interconnect 62a,b AA to review- done/corrections

- Table 5a,b Electrical Defects Yield Enhance.

- Table 6a,b P.Supply Volt. line item unchgd PIDs 35a,b AA to review-done-no changeMax. Power CP & HP updtd -NOchg to# A&P, Design, PIDs 75a,b AA to confirm -done-no change

- Table 7a,b Affordable Cost Economic (AA actg) n/a -no change

Test Cost Table unchgd Test 24a,b Table not changed

90, 91 only notes AA to review –done -no change

ORTC Table Line Item(s)


2002 Update vs 2001 ITRS Example: ORTC Line Item Update:

A&P Chip-to-Next-Level (ORTC Table 4a,b; A&P Table 77)


Assembly and Packaging – 2002 Update vs. 2001Table 77 Chip to Next Level Potential Solutions

Year of Production 2001 2002 2003 2004 2005 2006 2007 2010 2013 2016

DRAM ½ Pitch (nm) 130 115 100 90 80 70 65 45 32 22

MPU / ASIC ½ Pitch (nm) 150 130 107 90 80 70 65 50 35 25

MPU Printed Gate Length (nm) 90 75 65 53 45 40 35 25 18 13

MPU Physical Gate Length (nm) 65 53 45 37 32 28 25 18 13 9

Chip Interconnect Pitch (µm)

Was Wire bond—ball 45 35 30 25 20 20 20 20 20 20

I s Wire bond—ball 45 40 35 30 25 20 20 20 20 20

Was Wire bond—wedge 40 35 30 25 20 20 20 20 20 20

I s Wire bond—wedge 50 50 40 40 35 35 30 20 20 20

Was TAB*. 40 40 40 40 30 30 30 30 30 30

I s TAB* Japan TWG has the lead for Tab technologies

45 40 35 35 30 30 25 20 20 15

Was Flip chip (area array for cost-performance and high-performance)

160 160 150 150 130 130 120 90 80 70

I s Flip chip area array 200 180 150 150 100 100 80 70 70 50

Was Peripheral flip chip for hand-held, low-cost, and harsh

150 130 120 110 100 90 80 60 45 30

I s Peripheral flip chip 80 80 60 60 40 40 30 20 20 15


2002 ITRS Update versus 2001 ITRS - Assembly and Packaging Flip-Chip Peripheral Pad Pitch

(A&P Table 77; ORTC Table 4a,b)

0

20

40

60

80

100

120

140

160

2001 2002 2003 2004 2005 2006 2007 2010 2013 2016

Year

Pad

Pit

ch (

um

)

Peripheral flip chip for hand-held, lo-cost, harsh - WAS (2001) Peripheral flip chip - IS (2002)

2001 ITRS - "WAS"

2002 Update - "IS"

Chip- to- Next- Level

Potential Solution:

Conductive Adhesive

Peripheral Pad Attachment

Sources: 2001 ITRS (12/2001); 2001 ITRS Update (11/2002)

Flip- Chip Pad


2002 ITRS Update versus 2001 ITRS - Assembly and Packaging Flip-Chip Peripheral Pad Pitch

(A&P Table 77; ORTC Table 4a,b)

0

20

40

60

80

100

120

140

160

2001 2002 2003 2004 2005 2006 2007 2010 2013 2016

Year

Pad

Pit

ch (

um

)

Peripheral flip chip for hand-held, lo-cost, harsh - WAS (2001) Peripheral flip chip - IS (2002)Wire bond—ball - WAS (2001) Wire bond—ball - IS (2002)

Chip- to- Next- Level

Potential Solution:

Conductive Adhesive

Peripheral Pad Attachment

Sources: 2001 ITRS (12/2001); 2001 ITRS Update (11/2002)

2001 ITRS - "WAS"

2002 Update - "IS"

Wire Bond (Ball)

Flip- Chip Pad

Documents

4 December 2002, ITRS 2002 Update Conference The International Technology Roadmap for Semiconductors 2002 Update Summary Overall Roadmap Technology Characteristics