3 Chris Hobbs Sematech

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Text of 3 Chris Hobbs Sematech

SEMATECH Symposium June 23, 2011 Tokyo Accelerating the next technology revolution

CMOS Scaling Beyond FinFETs: Nanowires and TFETs

Chris Hobbs, Wei-Yip Loh, Kerem Akarvardar, Paul Kirsch, and Raj Jammy June 22, 2010Copyright 2009 SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. International SEMATECH Manufacturing Initiative, ISMI, Advanced Materials Research Center and AMRC are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.

Outline Advanced CMOS Scaling Overview Nanowires TFETs Summary

14 June 2011

2

Device scaling options

Id,sat

Vg14 June 2011 3

Device scaling options

Id,sat

Vg14 June 2011 4

Device scaling options

1

Very high mobility/high injection velocity SiGe, Ge, InGaAs Graphene [e ~15000 cm2/V-s at RT]

Id,sat

Vg14 June 2011 5

Device scaling options

2

1

Very high mobility/high injection velocity SiGe, Ge, InGaAs Graphene [e ~15000 cm2/V-s at RT] Better electrostatic control Multiple gates + more channel area FinFETs, nanowire FET

Id,sat

Vg14 June 2011 6

Why are Multi-Gates beneficial?Single Gate DeviceGate SourceExtension HaloChannel

Conventional MOSFET Scaling to improve performanceDrain Source

Lg

Drain

Gate cant control down here, so drain leaks to source Well

Source and drain are much closer Gate looses control of channel region

Thin Silicon Channel

Thin silicon channel with gate on both sides helps maintain channel control.FinFETn ai r

Double Gate Device

Fin GateD

4-Gate Device

Nanowire GateD n ai r

Source

Drain

Gates on both sides

ur SoSi Wafer Surface

ce

c ur So

e

14 June 2011

7

Performance and power tradeoff

Typical Ion-Ioff for CMOSFETs

Same transistor with specifications tuned for performance or power @ cost.14 June 2011 8

Al m l Fa at c er e i a Tr ls/ an ar si ch st ite or c t Sc ur a es lin /n g I ov s s el ue pr s o c (n es ee se d s) ne w

Performance and power tradeoff

Typical Ion-Ioff for CMOSFETs

Same transistor with specifications tuned for performance or power @ cost.14 June 2011 9

MOSFET scaling trendsPlanarHigh-K 32nm

New materials22nm? 16nm?

Si-Ge Device

III-V Device 12nm+

45nm

SEMATECH, VLSI 2009 (Production) Intel IEDM 2007 (Production) Intel IEDM 2009 IBM, IEDM 2009 6nm Length B. Doris IEDM 2002

Intel, IEDM 2007,9

SEMATECH, IEDM 2010

2007 2009

2009

2011

2013

2015

Past: Performance improved by scaling device dimensions. Now: Performance improved by Novel Materials and Architectures. Planar CMOS and Beyond: A continuous spectrum of devices.14 June 2011

Non planar

Intel Tri-Gate, VLSI 2006

NXP FINFET, VLSI 2007

SEMATECH, IEDM 2009

Nano-wire (LETI IEDM08)

10

Non-planar devicesMotivation: Gate wrap-around helps control short channel effects in scaled devices High mobility channels enables higher drive currents Scaling Pathwaysw and w/o 3rd gate ?

ORHigh

Heterogeneous

High

Bulk vs SOI

OR

SiN HM

Si BOX14 June 2011

HfO2 TiN

Homgeneous

11

Critical FinFET/Trigate/Nanowire ModulesSource/Drain SEG, doping and silicide Gate etch Fin Scaling and smoothness Source/Drain SEG, doping and silicide Gate etch NW Scaling and smoothness

Si SiGe Si SiGe SiSpacer etch and process schemes Processing and integration Group IV channel material

SiGe SiGe BOX SiSpacer etch and process schemes

Processing and integration

Group IV channel material

FinFET/Trigate

Nanowire

Most nanowire module issues are similar to FinFET module issues with added degree of integration complexity.14 June 2011 12

Silicon NanowiresWmask = 50 nm

suspended wires 45 source

MG

0n m

Si

HiK

drain10 nm

Single Si Nanowire Silicide Data|VD| = 1 V |VD| = 50 mV

450

ID (A/um)

Wmask = 50 nm

nm

PFET

NFETGate length = 40 nm NW width = 50 nm NW height = 20 nm

VGS (V)14 June 2011 13

Gate wraparound improves rolloffSwing (V/dec)

Omega Gate FinFET

Nanowire device has smaller rolloff compared to FinFET. Wrapping gate around channel improves short channel control.

VDS = -50 mV

PFET

Long channel SS is similar for Omega-Gate and FinFET. Vdd scaling limited by SS. Different device structure needed to reduce Vdd. TFET!

DIBL (V/V)

SiN HM

PFET

Si BOX

HfO2 TiN

Gate-All-Around (GAA) Device: Total current in nanowire limited by crossectional area. Multiple GAA nanowires to meet ITRS targets. In contrast, total current in FinFET can be increased with taller fins.14

Lmask (nm)

14 June 2011

Stacked Si nanowire formation using SiGeSiGe/Si Superlattice Fin etch Selective SiGe etch

Si Si Si

SiGe SiGe BOX

Si Si Si

SiGe SiGe

SiSiGe

Si Si

SiGe

BOX

Suspended NWs

Pt SiN

Si SiGe Si SiGe Si

BOX

Si SiGe Si SiGe Si

200 nm Si

BOX

Stacking nanowires helps increase total drive current to meet ITRS targets.14 June 2011 15

High mobility SiGe FinFETs/nanowires350 300(110)

SiGe fin SiGe {100}(Tinv= 1.8nm) Si {110}

SiGe {110}

eff (cm /V-s)

250 200 150 100 50 0 0(100)

shell/core fin (100) universal(Tinv=1.5nm)

Si {100}

2

Si fin(Tinv = 1.2nm)

Universal (100)13

1x10

2x103

13

NINV (#/cm )

Extracted by Split CV Method

SiGe PFETs have higher mobility than Si fins. Potential for performance > strained Si in non-planar devices14 June 2011 16

Outline Advanced CMOS Scaling Overview Nanowires TFETs Summary

14 June 2011

17

Device scaling options

2

1

Very high mobility/high injection velocity SiGe, Ge, InGaAs Graphene [e ~15000 cm2/V-s at RT] Better electrostatic control Multiple gates + more channel area FinFETs, nanowire FET Improve on-off ratio Tunnel FET Very steep SS 10 10 105 4 4 3

1

[1] IEDM Tech. Dig. 2009, p.949. [2] IEDM Tech. Dig. 2008, p. 947. [3] IEDM Tech. Dig. 2008, p. 163. [4] IEEE Trans, ED., vol 51(2), p. 279, 2004. [5] IEEE EDL, vol. 28(8), p. 743, 2007. [6] 40th ESSDERC 2010, p162

10 5 >10 4 >10

Ion is taken at overdrive of Vg-VBT = 2.0V except for *. Ioff taken at onset of BT-BT, VBT23

14 June 2011

Eg engineering : H-TFET Effective Eg can be engineered by using heterostructure (e.g. Ge on Si) Ge % from 25 ~ 50% Bandgap engineering to enhance tunneling Abrupt doping gradient by in-situ Bdoped SiGe and post annealingn+ Si (Drain) Gate p+Ge (Source)

i-Si Heterostructure TFETEc offset and bandgap narrowing for high tunneling g g g

g

SEMATECH-UCB DARPA Joint Project

Much lighter Hole mass14 June 2011 24

III-V tunnel FETs(InAs) Eg=0.36eV, Vd=0.2V1E03 Drain Current (A/m)1013

High DitIn0.53GaAs CB edge10

Junction Leakage3

Dit (#/cm /eV

2

1E06 -

VB edge12

Idiode (A/cm )

(Ge) Eg=0.69eV, Vd=0.5V

2

10 10 10 10 10

1

n+i-p+ In0.53GaAs Diodes

-1

1st lot 2nd lot

(Si) Eg=1.1eV, Vd=1V

10

-3

1E09 0.0 0.2 0.4 0.6 0.8 1.0

-5

p-Type

n-Type

Gate Voltage (V)

10

11

-7

-2.0 -1.5 -1.0 -0.5 0.0 0.5

-1.0

-0.5

[C. Hu et al, VLSI-TSA, pp.14-15, 2008]

Vgate (V)

Vdiode (V)

0.0

0.5

1.0

Tunneling is a strong function of bandgap. III-V has smaller bandgap and heterostructures (e.g. InAs/AlxGa1-xSb) have staggered or even zero bandgap direct tunneling. Preliminary InGaAs TFETs results indicates further optimization is needed to improve the poor SS, high Ioff, high Dit and poor Rco.25

14 June 2011

Novel design: pocket structure TFETP+ Pocket N+ S ource PBuried Oxide P+ Drain

[ C. Hu et al, VLSI-TSA, April, 2008 ]

Large field, good capacitive coupling btw gate & pocket Abrupt turn-on due to overlap of valence/conduction bands Tunable turn-on voltage14 June 2011 26

Dopant-segregated Si-pocket TFETSEMATECH-UCB VLSI Symp. 2010

NiSi Achieved sub-60 mV/dec (46mV/dec) with 30% dies showing sub60mV/dec Si TFET with high-K/MG0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 Schottky-Source P-I-N TFET Silicon

Gate

BOX100nm10 -5 10 -6 10 -7 10 -8 10 -9 10 -10 10 -11 10 -12 10 -13 10 -14 10-4

NiSiBOX

N+ Si

GateNiSi

Si

Probability

ID [A/m]

BOX N+ < Pocket >

GateNiSi

Si

20

60 100 140 180 220 Subthreshold Swing [mV/dec]

Measured Sim. w/ pocket Sim. no pocket

BOX N+ < No Pocket >

-1.5

-1.0

V G [V]

-0.5

0.0

14 June 2011

27

S-MLD pocket InGaAs pocket TFETs10 10-4 -5 -6 -7 -8 -9

Pocket

AlOx

Idrain (A/m

10 10 10 10

n+

AlOxi

ControlV g-V BT = 0.2 V to 1.5 V L g = 100 nm -0.5 in step of 0.1 V 0.0 0.513

P++ P+

i

N+

Tunneling Front

P++ P+