3 A step-down switching regulator - Farnell element14 A step-down switching regulator Datasheet -production data Features 3 A DC output current 4.5 V to 38 V input voltage Output voltage

This is information on a product in full production.

September 2014 DocID022450 Rev 6 1/43

L7986

3 A step-down switching regulator

Datasheet - production data

Features

3 A DC output current

4.5 V to 38 V input voltage

Output voltage adjustable from 0.6 V

250 KHz switching frequency, programmable up to 1 MHz

Internal soft-start and enable

Low dropout operation: 100% duty cycle

Voltage feed-forward

Zero load current operation

Overcurrent and thermal protection

VFQFPN 3 x 3 - 10L and HSOP8 package

Applications

Consumer: STB, DVD, DVD recorder, car audio, LCD TV and monitors

Industrial: PLD, PLA, FPGA, chargers

Networking: XDSL, modems, DC-DC modules

Computer: optical storage, hard disk drive, printers, audio/graphic cards

LED driving

Description

The L7986/A is a step-down switching regulator with a 3.7 A (minimum) current limited embedded power MOSFET, so it is able to deliver up to 3 A current to the load depending on the application conditions. The input voltage can range from 4.5 V to 38 V, while the output voltage can be set starting from 0.6 V to VIN. Requiring a minimum set of external components, the device includes an internal 250 kHz switching frequency oscillator that can be externally adjusted up to 1 MHz. The QFN and the HSOP packages with exposed pad allow reducing the RthJA down to 60 °C/W and 40 °C/W respectively.

Figure 1. Application circuit

VFQFPN10 3 x 3 mm HSOP8 exp. pad

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Contents L7986

2/43 DocID022450 Rev 6

Contents

1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5.1 Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5.2 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

5.3 Error amplifier and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.4 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.5 Enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.6 Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.4.1 Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.4.2 Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.5 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.6 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.7 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7 Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.1 Positive buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.2 Inverting buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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L7986 Contents

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8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Pin settings L7986

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1 Pin settings

1.1 Pin connection

Figure 2. Pin connection (top view)

1.2 Pin description

OUT

SYNCH

EN

COMP

VCC

GND

FSW

FB

OUT VCC

OUT

SYNCH

EN

COMP

VCC

GND

FSW

FB

CC

VFQFPN10 HSOP8

Table 1. Pin description

No.

(VFQFPN)

No.

(HSOP)Type Description

1 - 2 1 OUT Regulator output

3 2 SYNCH

Master/slave synchronization. When it is left floating, a signal with a phase shift of half a period, with respect to the power turn-on is present at the pin. When connected to an external signal at a frequency higher than the internal one, the device is synchronized by the external signal, with zero phase shift.

Connecting together the SYNCH pin of two devices, the one with a higher frequency works as master and the other one as slave; so the two powers turn-ons have a phase shift of half a period.

4 3 ENA logical signal (active high) enables the device. With EN higher than 1.2 V the device is ON and with EN lower than 0.3 V the device is OFF.

5 4 COMPError amplifier output to be used for loop frequency compensation.

6 5 FB

Feedback input. By connecting the output voltage directly to this pin the output voltage is regulated at 0.6 V. To have higher regulated voltages an external resistor divider is required from Vout to the FB pin.

7 6 FSW

The switching frequency can be increased connecting an external resistor from the FSW pin and ground. If this pin is left floating, the device works at its free-running frequency of 250 KHz.

8 7 GND Ground

9 - 10 8 VCC Unregulated DC input voltage.

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L7986 Maximum ratings

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2 Maximum ratings

3 Thermal data

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

Vcc Input voltage 45

V

OUT Output DC voltage -0.3 to VCC

FSW, COMP, SYNCH Analog pin -0.3 to 4

EN Enable pin -0.3 to VCC

FB Feedback voltage -0.3 to 1.5

PTOT Power dissipation at TA < 60 °CVFQFPN 1.5 W

HSOP 2

TJ Junction temperature range -40 to 150 °C

Tstg Storage temperature range -55 to 150 °C

Table 3. Thermal data

Symbol Parameter Value Unit

RthJA Maximum thermal resistance junction ambient(1)VFQFPN 60

°C/WHSOP 40

1. Package mounted on demonstration board.

Electrical characteristics L7986

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4 Electrical characteristics

TJ = 25 °C, VCC = 12 V, unless otherwise specified.

Table 4. Electrical characteristics

Symbol Parameter Test conditionValues

UnitMin. Typ. Max.

VCC Operating input voltage range (1) 4.5 38

VVCCON Turn-on VCC threshold (1) 4.5

VCCHYS VCC UVLO hysteseris (1) 0.1 0.4

RDSON MOSFET on resistance200

m(1) 400

ILIM Maximum limiting current 3.7 4.2 4.7 A

Oscillator

FSW Switching frequency (1) 210 250 275 KHz

VFSW FSW pin voltage 1.254 V

D Duty cycle 0 100 %

FADJ Adjustable switching frequency RFSW = 33 k 1000 KHz

Dynamic characteristics

VFB Feedback voltage4.5 V < VCC < 38 V 0.593 0.6 0.607

V4.5 V < VCC < 38 V(1) 0.582 0.6 0.618

DC characteristics

IQ Quiescent current Duty cycle = 0, VFB = 0.8 V 2.4 mA

IQST-BY Total standby quiescent current 20 30 A

Enable

VEN EN threshold voltageDevice OFF level 0.3

VDevice ON level 1.2

IEN EN current EN = VCC 7.5 10 A

Soft start

TSS Soft-start durationFSW pin floating 7.4 8.2 9.1

msFSW = 1 MHz, RFSW = 33 k 2

Error amplifier

VCH High level output voltage VFB < 0.6 V 3V

VCL Low level output voltage VFB > 0.6 V 0.1

IO SOURCE Source COMP pin VFB = 0.5 V, VCOMP = 1 V 19 mA

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L7986 Electrical characteristics

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IO SINK Sink COMP pin VFB = 0.7 V, VCOMP = 1 V 30 mA

GV Open-loop voltage gain (2) 100 dB

Synchronization function

VS_IN,HI High input voltage 2 3.3V

VS_IN,LO Low input voltage 1

tS_IN_PW Input pulse widthVS_IN,HI = 3 V, VS_IN,LO = 0 V 100

nsVS_IN,HI = 2 V, VS_IN,LO = 1 V 300

ISYNCH,LO Slave sink current VSYNCH = 2.9 V 0.7 1 mA

VS_OUT,HI Master output amplitude ISOURCE = 4.5 mA 2 V

tS_OUT_PW Output pulse width SYNCH floating 110 ns

Protection

TSHDN

Thermal shutdown 150°C

Hystereris 30

1. Specifications referred to TJ from -40 to +125 °C. Specifications in the -40 to +125 °C temperature range are assured by design, characterization and statistical correlation.

2. Guaranteed by design.

Table 4. Electrical characteristics (continued)

Symbol Parameter Test conditionValues

UnitMin. Typ. Max.

Functional description L7986

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5 Functional description

The L7986 device is based on a “voltage mode”, constant frequency control. The output voltage VOUT is sensed by the feedback pin (FB) compared to an internal reference (0.6 V) providing an error signal that, compared to a fixed frequency sawtooth, controls the on- and off-time of the power switch.

The main internal blocks are shown in the block diagram in Figure 3. They are:

A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the synchronization signal. Its switching frequency can be adjusted by an external resistor. The voltage and frequency feed-forward are implemented.

The soft-start circuitry to limit inrush current during the startup phase.

The voltage mode error amplifier.

The pulse width modulator and the relative logic circuitry necessary to drive the internal power switch.

The high-side driver for embedded P-channel power MOSFET switch.

The peak current limit sensing block, to handle overload and short-circuit conditions.

A voltage regulator and internal reference. To supply the internal circuitry and provide a fixed internal reference.

A voltage monitor circuitry (UVLO) that checks the input and internal voltages.

A thermal shutdown block, to prevent thermal runaway.

Figure 3. Block diagram

PEAK CURRENT

LIMIT

OSCILLATOR

S

R

Q

THERMAL

SHUTDOWN

SOFT-START

EN

TRIMMING UVLO

0.6V

REGULATOR

&

BANDGAP

1.254V 3.3V

SYNCH

&

PHASE SHIFT

EN

FB

COMP

FSW GND SYNCH

OUT

VCC

DRIVER

E/APWM

PEAK CURRENT

LIMIT

OSCILLATOR

S

R

Q

THERMAL

SHUTDOWN

SOFT-START

EN

TRIMMING UVLOUVLO

0.6V

REGULATOR

&

BANDGAP

REGULATOR

&

BANDGAP

1.254V 3.3V

SYNCH

&

PHASE SHIFT

EN

FB

COMP

FSW GND SYNCH

OUT

VCC

DRIVER

E/APWM

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L7986 Functional description

43

5.1 Oscillator and synchronization

Figure 4 shows the block diagram of the oscillator circuit. The internal oscillator provides a constant frequency clock. Its frequency depends on the resistor externally connected to the FSW pin. If the FSW pin is left floating, the frequency is 250 kHz; it can be increased as shown in Figure 6 by an external resistor connected to ground.

To improve the line transient performance, keeping the PWM gain constant versus the input voltage, the voltage feed-forward is implemented by changing the slope of the sawtooth according to the input voltage change (see Figure 5.a).

The slope of the sawtooth also changes if the oscillator frequency is increased by the external resistor. In this way a frequency feed-forward is implemented (Figure 5.b) in order to keep the PWM gain constant versus the switching frequency (see Section 6.4 on page 18 for PWM gain expression).

On the SYNCH pin the synchronization signal is generated. This signal has a phase shift of 180° with respect to the clock. This delay is useful when two devices are synchronized connecting the SYNCH pins together. When SYNCH pins are connected, the device with a higher oscillator frequency typically works as a master, so the slave device switches at the frequency of the master but with a delay of half a period. This minimizes the RMS current flowing through the input capacitor (see the L5988D datasheet).

The SYNCH circuitry is also able to synchronize with a slightly lower external frequency, so the frequency pre-adjustment with the same resistor on the FSW pin, as described below, is suggested for a proper operation.

Figure 4. Oscillator circuit block diagram

The device can be synchronized to work at a higher frequency feeding an external clock signal. The synchronization changes the sawtooth amplitude, changing the PWM gain (Figure 5.c). This change must be taken into account when the loop stability is studied. To minimize the change of PWM gain, the free-running frequency should be set (with a resistor on the FSW pin) only slightly lower than the external clock frequency. This pre-adjusting of the frequency changes the sawtooth slope in order to render the truncation of sawtooth negligible, due to the external synchronization.

Clock

Generator

Ramp

Generator

FSW

Sawtooth

Clock

Synchronization SYNCHClock

Generator

Ramp

Generator

FSW

Sawtooth

ClockClock

Synchronization SYNCH


10/43 DocID022450 Rev 6

Figure 5. Sawtooth: voltage and frequency feed-forward; external synchronization

Figure 6. Oscillator frequency vs. FSW pin resistor

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43

5.2 Soft-start

The soft-start is essential to assure correct and safe startup of the step-down converter. It avoids inrush current surge and makes the output voltage increase monothonically.

The soft-start is performed by a staircase ramp on the non inverting input (VREF) of the error amplifier. So the output voltage slew rate is:

Equation 1

where SRVREF is the slew rate of the non inverting input, while R1and R2 is the resistor divider to regulate the output voltage (see Figure 7). The soft-start staircase consists of 64 steps of 9.5 mV each, from 0 V to 0.6 V. The time base of one step is of 32 clock cycles. So the soft-start time and then the output voltage slew rate depend on the switching frequency.

Figure 7. Soft-start scheme

Soft-start time results:

Equation 2

For example, with a switching frequency of 250 kHz, the SSTIME is 8 ms.

SROUT SRVREF 1R1R2--------+

=

SSTIME32 64Fsw-----------------=


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5.3 Error amplifier and compensation

The error amplifier (E/A) provides the error signal to be compared with the sawtooth to perform the pulse width modulation. Its non inverting input is internally connected to a 0.6 V voltage reference, while its inverting input (FB) and output (COMP) are externally available for feedback and frequency compensation. In this device the error amplifier is a voltage mode operational amplifier, therefore, with high DC gain and low output impedance.

The uncompensated error amplifier characteristics are the following:

In continuous conduction mode (CCM), the transfer function of the power section has two poles due to the LC filter and one zero due to the ESR of the output capacitor. Different kinds of compensation networks can be used depending on the ESR value of the output capacitor. If the zero introduced by the output capacitor helps to compensate the double pole of the LC filter, a type II compensation network can be used. Otherwise, a type III compensation network must be used (see Section 6.4 on page 18 for details of the compensation network selection).

Anyway, the methodology to compensate the loop is to introduce zeroes to obtain a safe phase margin.

5.4 Overcurrent protection

The L7986 device implements overcurrent protection by sensing current flowing through the power MOSFET. Due to the noise created by the switching activity of the power MOSFET, the current sensing is disabled during the initial phase of the conduction time. This avoids an erroneous detection of a fault condition. This interval is generally known as “masking time” or “blanking time”. The masking time is about 200 ns.

If the overcurrent limit is reached, the power MOSFET is turned off implementing pulse by pulse overcurrent protection. In the overcurrent condition, the device can skip turn-on pulses in order to keep the output current constant and equal to the current limit. If, at the end of the “masking time”, the current is higher than the overcurrent threshold, the power MOSFET is turned off and one pulse is skipped. If, at the following switching on, when the “masking time” ends, the current is still higher than the overcurrent threshold, the device skips two pulses. This mechanism is repeated and the device can skip up to seven pulses. While, if at the end of the “masking time”, the current is lower than the overcurrent threshold, the number of skipped cycles is decreased by one unit (see Figure 8).

So, the overcurrent/short-circuit protection acts by switching off the power MOSFET and reducing the switching frequency down to one eighth of the default switching frequency, in order to keep constant the output current around the current limit.

Table 5. Uncompensated error amplifier characteristics

Parameter Value

Low frequency gain 100 dB

GBWP 4.5 MHz

Slew rate 7 V/s

Output voltage swing 0 to 3.3 V

Maximum source/sink current 17 mA/25 mA

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43

This kind of overcurrent protection is effective if the output current is limited. To prevent the current from diverging, the current ripple in the inductor during the on-time must not be higher than the current ripple during the off-time. That is:

Equation 3

If the output voltage is shorted, VOUT 0, IOUT = ILIM, D / FSW = TON_MIN, (1 - D ) / FSW1 / FSW. So, from Equation 3, the maximum switching frequency that guarantees to limit the current results:

Equation 4

With RDSON = 300 m, DCR = 0.08 , the worst condition is with VIN = 38 V, ILIM = 3.7 A; the maximum frequency to keep the output current limited during the short-circuit results 88 kHz.

The pulse-by-pulse mechanism, which reduces the switching frequency down to one eighth the maximum FSW, adjusted by the FSW pin, that assures a full effective output current limitation, is 88 kHz * 8 = 706 kHz.

If, with VIN = 38 V, the switching frequency is set higher than 706 kHz, during short-circuit condition the system finds a different equilibrium with higher current. For example, with FSW = 800 kHz and the output shorted to ground, the output current is limited around:

Equation 5

where FSW* is 800 kHz divided by eight.

VIN VOUT RDSON IOUT DCR IOUT–––

L FSW------------------------------------------------------------------------------------------------------------ D

VOUT VF RDSON IOUT DCR IOUT++ +

L FSW----------------------------------------------------------------------------------------------------------- 1 D– =

FSW*

VF DCR I+LIM

VIN RDSON DCR+ ILIM– -------------------------------------------------------------------------------

1TON_MIN----------------------=

IOUT

VIN FSW* VF TON_MIN–

DCR TON_MIN RDSON DCR+ FSW*+

---------------------------------------------------------------------------------------------------------------- 4.2A= =


14/43 DocID022450 Rev 6

Figure 8. Overcurrent protection

5.5 Enable function

The enable feature allows to put the device into standby mode. With the EN pin lower than 0.3 V the device is disabled and the power consumption is reduced to less than 30 µA. With the EN pin lower than 1.2 V, the device is enabled. If the EN pin is left floating, an internal pull-down ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also VCC compatible.

5.6 Hysteretic thermal shutdown

The thermal shutdown block generates a signal that turns off the power stage if the junction temperature goes above 150 °C. Once the junction temperature returns to about 120 °C, the device restarts in normal operation. The sensing element is very close to the PDMOS area, so ensuring an accurate and fast temperature detection.

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L7986 Application information

43

6 Application information

6.1 Input capacitor selection

The capacitor connected to the input must be capable of supporting the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR, affecting the overall system efficiency.

So, the input capacitor must have an RMS current rating higher than the maximum RMS input current and an ESR value compliant with the expected efficiency.

The maximum RMS input current flowing through the capacitor can be calculated as:

Equation 6

where IO is the maximum DC output current, D is the duty cycle, is the efficiency. Considering , this function has a maximum at D = 0.5 and it is equal to IO/2.

In a specific application, the range of possible duty cycles must be considered in order to find out the maximum RMS input current. The maximum and minimum duty cycles can be calculated as:

Equation 7

and

Equation 8

where VF is the forward voltage on the freewheeling diode and VSW is the voltage drop across the internal PDMOS.

The peak-to-peak voltage across the input capacitor can be calculated as:

Equation 9

where ESR is the equivalent series resistance of the capacitor.

Given the physical dimension, ceramic capacitors can well meet the requirements of the input filter sustaining a higher input RMS current than electrolytic/tantalum types.

IRMS IO D2 D

2

---------------–D

2

2-------+=

DMAX

VOUT VF+

VINMIN VSW–-------------------------------------=

DMIN

VOUT VF+

VINMAX VSW–--------------------------------------=

VPP

IOCIN FSW------------------------- 1

D----–

DD---- 1 D– + ESR IO+=

Application information L7986

16/43 DocID022450 Rev 6

In this case the equation of CIN as a function of the target VPP can be written as follows:

Equation 10

neglecting the small ESR of ceramic capacitors.

Considering = 1, this function has its maximum in D = 0.5, therefore, given the maximum peak-to-peak input voltage (VPP_MAX), the minimum input capacitor (CIN_MIN) value is:

Equation 11

Typically CIN is dimensioned to keep the maximum peak-to-peak voltage in the order of 1% of VINMAX.

In Table 6 some multi-layer ceramic capacitors suitable for this device are reported.

A ceramic bypass capacitor, as close to the VCC and GND pins as possible, so that additional parasitic ESR and ESL are minimized, is suggested in order to prevent instability on the output voltage due to noise. The value of the bypass capacitor can go from 100 nF to 1 µF.

6.2 Inductor selection

The inductance value fixes the current ripple flowing through the output capacitor. So the minimum inductance value, in order to have the expected current ripple, must be selected. The rule to fix the current ripple value is to have a ripple at 20% - 40% of the output current.

In the continuous current mode (CCM), the inductance value can be calculated by the following equation:

Equation 12

where TON is the conduction time of the internal high-side switch and TOFF is the conduction time of the external diode [in CCM, FSW = 1 / (TON + TOFF)]. The maximum current ripple, at fixed VOUT, is obtained at maximum TOFF which is at minimum duty cycle (see Section 6.1 to calculate minimum duty). So, by fixing IL = 20% to 30% of the maximum output current, the minimum inductance value can be calculated:

Table 6. Input MLCC capacitors

Manufacture Series Cap value (F) Rated voltage (V)

Taiyo YudenUMK325BJ106MM-T 10 50

GMK325BJ106MN-T 10 35

Murata GRM32ER71H475K 4.7 50

CIN

IOVPP FSW--------------------------- 1

D----–

DD---- 1 D– +=

CIN_MIN

IO2 VPP_MAX FSW ------------------------------------------------=

ILVIN VOUT–

L------------------------------ TON

VOUT VF+

L---------------------------- TOFF= =

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Equation 13

where FSW is the switching frequency, 1 / (TON + TOFF).

For example, for VOUT = 5 V, VIN = 24 V, IO = 3 A and FSW = 250 kHz, the minimum inductance value to have IL = 30% of IO is about 18 H.

The peak current through the inductor is given by:

Equation 14

So, if the inductor value decreases, then the peak current (that must be lower than the minimum current limit of the device) increases. According to the maximum DC output current for this product family (3 A), the higher the inductor value, the higher the average output current that can be delivered, without triggering the overcurrent protection.

In Table 7 some inductor part numbers are listed.

6.3 Output capacitor selection

The current in the capacitor has a triangular waveform which generates a voltage ripple across it. This ripple is due to the capacitive component (charge or discharge of the output capacitor) and the resistive component (due to the voltage drop across its ESR). So the output capacitor must be selected in order to have a voltage ripple compliant with the application requirements.

The amount of the voltage ripple can be calculated starting from the current ripple obtained by the inductor selection.

Equation 15

Usually the resistive component of the ripple is much higher than the capacitive one, if the output capacitor adopted is not a multi-layer ceramic capacitor (MLCC) with very low ESR value.

Table 7. Inductors

Manufacturer Series Inductor value (H) Saturation current (A)

CoilcraftMSS1038 3.8 to 10 3.9 to 6.5

MSS1048 12 to 22 3.84 to 5.34

WurthPD type L 8.2 to 15 3.75 to 6.25

PD type M 2.2 to 4.7 4 to 6

SUMIDACDRH6D226/HP 1.5 to 3.3 3.6 to 5.2

CDR10D48MN 6.6 to 12 4.1 to 5.7

LMIN

VOUT VF+

IMAX----------------------------

1 DMIN–

FSW-----------------------=

IL PK IOIL2--------+=

VOUT ESR IMAXIMAX

8 COUT fSW -------------------------------------+=


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The output capacitor is important also for loop stability: it fixes the double LC filter pole and the zero due to its ESR. Section 6.4 illustrates how to consider its effect in the system stability.

For example, with VOUT = 5 V, VIN = 24 V, IL = 0.9 A (resulting from the inductor value), in order to have a VOUT = 0.01·VOUT, if the multi-layer ceramic capacitors are adopted, 10 µF are needed and the ESR effect on the output voltage ripple can be neglected. In the case of non-negligible ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into account its ESR value. So, in case of 330 µF with ESR = 30 m, the resistive component of the drop dominates and the voltage ripple is 28 mV

The output capacitor is also important to sustain the output voltage when a load transient with high slew rate is required by the load. When the load transient slew rate exceeds the system bandwidth, the output capacitor provides the current to the load. So, if the high slew rate load transient is required by the application, the output capacitor and system bandwidth must be chosen in order to sustain the load transient.

In Table 8 some capacitor series are listed.

6.4 Compensation network

The compensation network must assure stability and good dynamic performance. The loop of the L7986 is based on the voltage mode control. The error amplifier is a voltage operational amplifier with high bandwidth. So, by selecting the compensation network the E/A is considered as ideal, that is, its bandwidth is much larger than the system one.

The transfer functions of the PWM modulator and the output LC filter are studied (see Figure 10). The transfer function of the PWM modulator, from the error amplifier output (COMP pin) to the OUT pin, results:

Equation 16

where VS is the sawtooth amplitude. As seen in Section 5.1 on page 9, the voltage feed-forward generates a sawtooth amplitude directly proportional to the input voltage, that is:

Equation 17

Table 8. Output capacitors

Manufacturer Series Cap value (F) Rated voltage (V) ESR (m)

MURATAGRM32 22 to 100 6.3 to 25 < 5

GRM31 10 to 47 6.3 to 25 < 5

PANASONICECJ 10 to 22 6.3 < 5

EEFCD 10 to 68 6.3 15 to 55

SANYO TPA/B/C 100 to 470 4 to 16 40 to 80

TDK C3225 22 to 100 6.3 < 5

GPW0

VIN

Vs---------=

VS K VIN=

DocID022450 Rev 6 19/43


43

In this way the PWM modulator gain results constant and equal to:

Equation 18

The synchronization of the device with an external clock provided through the SYNCH pin can modify the PWM modulator gain (see Section 5.1 on page 9 to understand how this gain changes and how to keep it constant in spite of the external synchronization).

Figure 9. The error amplifier, the PWM modulator, and the LC output filter

The transfer function on the LC filter is given by:

Equation 19

where:

Equation 20

Equation 21

GPW0

VIN

Vs---------

1K---- 18= = =

FB COMP

VREF

E/A

PWM

VS

OUT

VCC

COUT

ESR

L

GPW0 GLC

FB COMP

VREF

E/A

PWM

VS

OUT

VCC

COUT

ESR

L

GPW0 GLC

GLC s 1

s2 fzESR--------------------------+

1s

2 Q f LC----------------------------

s2 fLC------------------- 2

+ +-------------------------------------------------------------------------=

fLC1

2 L COUT 1ESRROUT---------------+

------------------------------------------------------------------------= fzESR1

2 ESR COUT --------------------------------------------=

QROUT L COUT ROUT ESR+

L COUT ROUT E SR +------------------------------------------------------------------------------------------ ROUT

VOUT

IOUT--------------=,=


20/43 DocID022450 Rev 6

As seen in Section 5.3 on page 12, two different kinds of network can compensate the loop. In the following two paragraphs the guidelines to select the type II and type III compensation network are illustrated.

6.4.1 Type III compensation network

The methodology to stabilize the loop consists of placing two zeroes to compensate the effect of the LC double pole, therefore increasing phase margin; then, to place one pole in the origin to minimize the DC error on regulated output voltage; and finally, to place other poles far from the zero dB frequency.

If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a frequency higher than the desired bandwidth (that is: 2ESR COUT < 1 / BW), the type III compensation network is needed. Multi-layer ceramic capacitors (MLCC) have very low ESR (< 1 m), with very high frequency zero, so a type III network is adopted to compensate the loop.

In Figure 10 the type III compensation network is shown. This network introduces two zeroes (fZ1, fZ2) and three poles (fP0, fP1, fP2). They are expressed as:

Equation 22

Equation 23

Figure 10. Type III compensation network

fZ11

2 C3 R1 R3+ ------------------------------------------------= fZ2

12 R4 C4 ------------------------------=

fP0 0= fP11

2 R3 C3 ------------------------------= fP2

1

2 R4

C4 C5C4 C5+--------------------

--------------------------------------------=

DocID022450 Rev 6 21/43


43

In Figure 11 the Bode diagram of the PWM and LC filter transfer function [GPW0 · GLC(f)] and the open-loop gain [GLOOP(f) = GPW0 · GLC(f) · GTYPEIII(f)] are drawn.

Figure 11. Open-loop gain: module Bode diagram

The guidelines for positioning the poles and the zeroes and for calculating the component values can be summarized as follows:

1. Choose a value for R1, usually between 1 k and 5 k.

2. Choose a gain (R4/R1) in order to have the required bandwidth (BW), that means:

Equation 24

where K is the feed-forward constant and 1/K is equal to 18.

3. Calculate C4 by placing the zero at 50% of the output filter double pole frequency (fLC):

Equation 25

4. Calculate C5 by placing the second pole at four times the system bandwidth (BW):

Equation 26

5. Set also the first pole at four times the system bandwidth and also the second zero at the output filter double pole:

R4BWfLC---------- K R1 =

C41

R4 fLC ---------------------------=

C5

C4

2 R4 C4 4 BW 1– --------------------------------------------------------------=


22/43 DocID022450 Rev 6

Equation 27

The suggested maximum system bandwidth is equal to the switching frequency divided by 3.5 (FSW / 3.5), anyway, lower than 100 kHz if the FSW is set higher than 500 kHz.

For example, with VOUT = 5 V, VIN = 24 V, IO = 3 A, L = 18 H, COUT = 22 F, ESR < 1 m, the type III compensation network is:

In Figure 12 the module and phase of the open-loop gain is shown. The bandwidth is about 58 kHz and the phase margin is 50°.

R3

R1

4 BWfLC

----------------- 1–---------------------------= C3

12 R3 4 BW -----------------------------------------=

R1 4.99k= R2 680= R3 200= R4 2k= C3 3.3nF= C4 22nF= C5 220pF=

DocID022450 Rev 6 23/43


43

Figure 12. Open-loop gain Bode diagram with ceramic output capacitor


24/43 DocID022450 Rev 6

6.4.2 Type II compensation network

If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a frequency lower than the desired bandwidth (that is: 2ESR COUT > 1 / BW), this zerohelps stabilize the loop. Electrolytic capacitors show non-negligible ESR (> 30 m), so withthis kind of output capacitor the type II network combined with the zero of the ESR allows tostabilize the loop.

In Figure 13 the type II network is shown.

Figure 13. Type II compensation network

The singularities of the network are:

Equation 28

fZ11

2 R4 C4 ------------------------------= fP0 0= fP1

1

2 R4

C4 C5C4 C5+--------------------

--------------------------------------------=

DocID022450 Rev 6 25/43


43

In Figure 14 the Bode diagram of the PWM and LC filter transfer function [GPW0 · GLC(f)] and the open-loop gain [GLOOP(f) = GPW0 · GLC(f) · GTYPEII(f)] are drawn.

Figure 14. Open-loop gain: module Bode diagram

The guidelines for positioning the poles and the zeroes and for calculating the component values can be summarized as follows:

1. Choose a value for R1, usually between 1 k and 5 k, in order to have values of C4 and C5 not comparable with parasitic capacitance of the board.

2. Choose a gain (R4/R1) in order to have the required bandwidth (BW), that means:

Equation 29

where fESR is the ESR zero:

Equation 30

and VS is the sawtooth amplitude. The voltage feed-forward keeps the ratio VS/VIN constant.

3. Calculate C4 by placing the zero one decade below the output filter double pole:

Equation 31

4. Then calculate C3 in order to place the second pole at four times the system bandwidth (BW):

Equation 32

R4

fESR

fLC------------

2 BWfESR------------

VS

VIN--------- R1 =

fESR1

2 ESR COUT --------------------------------------------=

C410

2 R4 fLC -------------------------------=

C5

C4

2 R4 C4 4 BW 1– --------------------------------------------------------------=


26/43 DocID022450 Rev 6

For example with VOUT = 5 V, VIN = 24 V, IO = 3 A, L = 18 H, COUT = 330 F, ESR = 35 m the type II compensation network is:

In Figure 15 the module and phase of the open-loop gain is shown. The bandwidth is about 21 kHz and the phase margin is 45°.

Figure 15. Open-loop gain Bode diagram with electrolytic/tantalum output capacitor

R1 1.1k= R2 150= R4 4.99k= C4 82nF= C5 68pF=

DocID022450 Rev 6 27/43


43

6.5 Thermal considerations

The thermal design is important to prevent the thermal shutdown of device if junction temperature goes above 150 °C. The three different sources of losses within the device are:

a) conduction losses due to the non-negligible RDSON of the power switch; these are equal to:

Equation 33

where D is the duty cycle of the application and the maximum RDSON overtemperature is 220 m. Note that the duty cycle is theoretically given by the ratio between VOUT and VIN, but actually it is quite higher to compensate the losses of the regulator. So the conduction losses increase compared with the ideal case.

b) switching losses due to power MOSFET turn ON and OFF; these can be calculated as:

Equation 34

where TRISE and TFALL are the overlap times of the voltage across the power switch (VDS) and the current flowing into it during turn ON and turn OFF phases, as shown in Figure 16. TSW is the equivalent switching time. For this device the typical value for the equivalent switching time is 40 ns.

c) Quiescent current losses, calculated as:

Equation 35

where IQ is the quiescent current (IQ = 2.4 mA).

The junction temperature TJ can be calculated as:

Equation 36

where TA is the ambient temperature and PTOT is the sum of the power losses just seen.

RthJA is the equivalent thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient. For this device the path through the exposed pad is the one conducting the largest amount of heat. The RthJA, measured on the demonstration board described in the following paragraph, is about 60 °C/W for the VFQFPN package and about 40 °C/W for the HSOP package.

PON RDSON IOUT 2 D =

PSW VIN IOUT

TRISE TFALL+ 2

------------------------------------------- Fsw VIN IOUT TSW FSW = =

PQ VIN IQ=

TJ TA RthJA PTOT+=


28/43 DocID022450 Rev 6

Figure 16. Switching losses

6.6 Layout considerations

The PC board layout of the switching the DC/DC regulator is very important to minimize the noise injected in high impedance nodes and interference generated by the high switching current loops.

In a step-down converter the input loop (including the input capacitor, the power MOSFET and the freewheeling diode) is the most critical one. This is due to the fact that the high value pulsed currents are flowing through it. In order to minimize the EMI, this loop must be as short as possible.

The feedback pin (FB) connection to the external resistor divider is a high impedance node, so the interference can be minimized by placing the routing of the feedback node as far as possible from the high current paths. To reduce the pick-up noise, the resistor divider must be placed very close to the device.

To filter the high frequency noise, a small bypass capacitor (220 nF - 1 µF) can be added as close as possible to the input voltage pin of the device.

Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal resistance junction to ambient; so a large ground plane enhances the thermal performance of the converter allowing high power conversion.

DocID022450 Rev 6 29/43


43

In Figure 17 a layout example is shown.

Figure 17. Layout example


30/43 DocID022450 Rev 6

6.7 Application circuit

In Figure 18 the demonstration board application circuit is shown.

Figure 18. Demonstration board application circuit

Table 9. Component list

Reference Part number Description Manufacturer

C1 UMK325BJ106MM-T 10 F, 50V Taiyo Yuden

C2 GRM32ER61E226KE15 22 F, 25V Murata

C3 3.3 nF, 50V

C4 33 nF, 50V

C5 100 pF, 50V

C6 470 nF, 50V

R1 4.99 k, 1%, 0.1 W 0603

R2 1.1 k, 1%, 0.1 W 0603

R3 330 , 1%, 0.1 W 0603

R4 1.5 k, 1%, 0.1 W 0603

R5 180 k1%, 0.1 W 0603

D1 STPS3L40 3A DC, 40 V STMicroelectronics

L1 MSS1038-103NL10 H, 30%, 3.9 A, DCRMAX=35 m

Coilcraft

DocID022450 Rev 6 31/43


43

Figure 19. PCB layout: L7986 and L7986A (component side)

Figure 20. PCB layout: L7986 and L7986A (bottom side)

Figure 21. PCB layout: L7986 and L7986A (front side)


32/43 DocID022450 Rev 6

Figure 22. Junction temperature vs. output current VIN = 24 V


VOUT=1.8V

VOUT=3.3V

VOUT=5V

HSOPVQFN

VIN=24VFSW=250KHzTAMB=25 C

VOUT=1.8V

VOUT=3.3V

VOUT=5V

HSOPVQFN



Figure 25. Efficiency vs. output current VO = 1.8 V

VOUT=1.2V

VOUT=1.8V

VOUT=3.3V

HSOPVQFN


40

45

50

55

60

65

70

75

80

85

0.100 0.600 1.100 1.600 2.100 2.600 3.100

Io [A]

Eff

[%

]

Vin=5V

Vin=12V

Vin=24V

Vo=1.8VFSW=250kHz

Figure 26. Efficiency vs.output current VO = 5.0 V

Figure 27. Efficiency vs.output current VO = 3.3 V

60

65

70

75

80

85

90

95

0.100 0.600 1.100 1.600 2.100 2.600 3.100

Io [A]

Eff

[%

]

Vin=12V

Vin=18V

Vin=24V

Vo=5.0VFSW=250kHz

50

55

60

65

70

75

80

85

90

95

0.100 0.600 1.100 1.600 2.100 2.600 3.100

Io [A]

Eff

[%

]

Vin=5V

Vin=12V

Vin=24V

Vo=3.3VFSW=250kHz

DocID022450 Rev 6 33/43


43

Figure 28. Load regulation Figure 29. Line regulation

3.305

3.310

3.315

3.320

3.325

3.330

3.335

3.340

3.345

3.350

0.00 0.50 1.00 1.50 2.00 2.50 3.00

VO

UT

[V]

Io [A]

Vin=5V

Vin=12V

Vin=24V

3.3200

3.3250

3.3300

3.3350

3.3400

3.3450

3.3500

3.3550

3.3600

5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0

VO

UT

[V]

VIN [V]

Io=1A

Io=2A

Io=3A

Figure 30. Load transient: from 0.4 A to 2 A Figure 31. Soft-start

VOUT

200mV/divAC coupled

IL 1A/div

Time base 200us/div

VIN=24VVOUT=3.3VCOUT=47uFL=10uHFSW=520k

IL 1A/div

VOUT 1V/div

Time base 1ms/div

IL 0.5A/div

VOUT 0.5V/div

Time base 1ms/div

IL 1A/div

VOUT 1V/div

Time base 1ms/div

IL 0.5A/div

VOUT 0.5V/div

Time base 1ms/div

Figure 32. Short-circuit behavior VIN = 12 V Figure 33. Short-circuit behavior VIN = 24 V

OUT5V/div

IL1A/div

VOUT1V/div

SYNCH5V/div

Timebase 10us/div

OUT5V/div

IL1A/div

VOUT1V/div

SYNCH5V/div

Timebase 10us/div

OUT5V/div

IL1A/div

VOUT1V/div

SYNCH5V/div

Timebase 10us/div

OUT5V/div

IL1A/div

VOUT1V/div

SYNCH5V/div

OUT5V/div

IL1A/div

VOUT1V/div

SYNCH5V/div

OUT5V/div

IL1A/div

VOUT1V/div

SYNCH5V/div

Timebase 10us/div

Application ideas L7986

34/43 DocID022450 Rev 6

7 Application ideas

7.1 Positive buck-boost

The L7986 device can implement the step-up/down converter with a positive output voltage.

Figure 34 shows the schematic: one power MOSFET and one Schottky diode are added to the standard buck topology to provide 12 V output voltage with input voltage from 4.5 V to 38 V.

Figure 34. Positive buck-boost regulator

The relationship between input and output voltage is:

Equation 37

so the duty cycle is:

Equation 38

The output voltage isn’t limited by the maximum operating voltage of the device (38 V), because the output voltage is sensed only through the resistor divider. The external power MOSFET maximum drain to the source voltage, must be higher than the output voltage; the maximum gate to source voltage must be higher than the input voltage (in Figure 34, if VIN is higher than 16 V, the gate must be protected through the Zener diode and resistor).

The current flowing through the internal power MOSFET is transferred to the load only during the off-time, so according to the maximum DC switch current (3.0 A), the maximum output current for the buck-boost topology can be calculated from Equation 39.

VOUT VIND

1 D–-------------=

DVOUT

VOUT VIN+------------------------------=

DocID022450 Rev 6 35/43

L7986 Application ideas

43

Equation 39

where ISW is the average current in the embedded power MOSFET in the on-time.

To chose the right value of the inductor and to manage transient output current, that for a short time can exceed the maximum output current calculated by Equation 39, also the peak current in the power MOSFET must be calculated. The peak current, shown in Equation 40, must be lower than the minimum current limit (3.7 A).

Equation 40

where r is defined as the ratio between the inductor current ripple and the inductor DC current:

So, in the buck-boost topology the maximum output current depends on the application conditions (firstly input and output voltage, secondly switching frequency and inductor value).

In Figure 35 the maximum output current for the above configuration is depicted varying the input voltage from 4.5 V to 38 V.

The dashed line considers a more accurate estimation of the duty cycles given by Equation 41, where power losses across diodes, external power MOSFET, and internal power MOSFET are taken into account.

Figure 35. Maximum output current according to max DC switch current (3.0 A): VO = 12 V

ISW

IOUT

1 D–------------- 3 A=

ISW,PK

IOUT

1 D–------------- 1

r2---+ 3.7A=

Application ideas L7986

36/43 DocID022450 Rev 6

Equation 41

where VD is the voltage drop across the diodes, VSW and VSWE across the internal and external power MOSFET.

7.2 Inverting buck-boost

The L7986 can implement the step-up/down converter with a negative output voltage.

Figure 34. shows the schematic to regulate -5 V: no further external components are added to the standard buck topology.

The relationship between input and output voltage is:

Equation 42

so the duty cycle is:

Equation 43

As in the positive one, in the inverting buck-boost the current flowing through the power MOSFET is transferred to the load only during the off-time. So according to the maximum DC switch current (3.0 A), the maximum output current can be calculated from Equation 39, where the duty cycle is given by Equation 43.

Figure 36. Inverting buck-boost regulator

The GND pin of the device is connected to the output voltage so, given the output voltage, the input voltage range is limited by the maximum voltage the device can withstand across VCC and GND (38 V). Therefore, if the output is -5 V the input voltage can range from 4.5 V to 33 V.

DVOUT 2 VD+

VIN VSW VSWE VOUT 2 V D+ +––--------------------------------------------------------------------------------------------=

VOUT VIN–D

1 D–-------------=

DVOUT

VOUT VIN–------------------------------=

DocID022450 Rev 6 37/43

L7986 Application ideas

43

As in the positive buck-boost, the maximum output current according to application conditions is shown in Figure 37. The dashed line considers a more accurate estimation of the duty cycles given by Equation 44, where power losses across diodes and the internal power MOSFET are taken into account.

Equation 44

Figure 37. Maximum output current according to switch max. peak current (3.0 A): VO = - 5 V

DVOUT VD–

V– IN VSW VOUT VD–+–-----------------------------------------------------------------=

Package information L7986

38/43 DocID022450 Rev 6

8 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

Figure 38. VFQFPN10 (3 x 3 x 1.08 mm) package dimensions

7

DocID022450 Rev 6 39/43

L7986 Package information

43

Table 10. VFQFPN10 (3 x 3 x 1.08 mm) package mechanical data

SymbolDimensions (mm)

Min. Typ. Max.

A 0.80 0.90 1.00

A1 0.02 0.05

A2 0.70

A3 0.20

b 0.18 0.23 0.30

D 2.95 3.00 3.05

D2 2.21 2.26 2.31

E 2.95 3.00 3.05

E2 1.49 1.64 1.74

e 0.50

L 0.3 0.40 0.5

M 0.75

m 0.25

Package information L7986

40/43 DocID022450 Rev 6

Figure 39. HSOP8 package outline

Table 11. HSOP8 package mechanical data

SymbolDimensions (mm)

Min. Typ. Max.

A 1.70

A1 0.00 0.150

A2 1.25

b 0.31 0.51

c 0.17 0.25

D 4.80 4.90 5.00

E 5.80 6.00 6.20

E1 3.80 3.90 4.00

e 1.27

h 0.25 0.50

L 0.40 1.27

k 0.00 8.00

ccc 0.10

DocID022450 Rev 6 41/43

L7986 Ordering information

43

9 Ordering information

Table 12. Order codes

Order code Package Packaging

L7986A HSOP8 Tube

L7986TR VFQFPN10 Tape and reel

L7986ATR HSOP8 Tape and reel

Revision history L7986

42/43 DocID022450 Rev 6

10 Revision history

Table 13. Document revision history

Date Revision Changes

07-Nov-2011 1 Initial release.

01-Mar-2012 2 Section 8: Package information has been updated.

15-Oct-2012 3 In Section 5.6 changed temperature value from 130 to 120 °C.

19-Mar-2014 4

Updated text below Equation 4 on page 13 and in Equation 5 on page 13 (replaced “DRC” by “DCR”).

Updated Figure 34: Positive buck-boost regulator on page 34 (replaced by new figure).

Updated Section 8: Package information on page 38 (reversed order of Figure 38 and Table 10, and Figure 39 and Table 11, minor modifications).

Updated cross-references throughout document.

Minor modifications throughout document.

05-May-2014 5Updated Table 12: Order codes on page 41 (removed the L7986 order code related to the VFQFPN10 in tube, added the L7986ATR order code).

05-Sep-2014 6

Updated Figure 1: Application circuit on page 1 (replaced by new figure).

Updated Section 5.1 on page 9 (added “typically” between “frequency” and “works”, added “The SYNCH circuitry is also able to synchronize with a slightly lower external frequency, so the frequency pre-adjustment with the same resistor on the FSW pin, as described below, is suggested for a proper operation.”).

Minor modifications throughout document.

DocID022450 Rev 6 43/43

L7986

43

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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

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