2.9 Problems Solved

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FPGA Assignment # 3Reference: FPGA – Based System Design

Author: Wayne Wolf

Prepared by Farida Memon

2.9 Problems

Use the technology parameters for transistors, wires and other elements given in this

chapter where appropriate.

Q2-1. Assume that Vgs = 1V, compute the drain current through n-type transistorsof these sizes at Vds values of 0.5 V, 0.75 V, and 1 V:

a. W/L = 5/2b. W/L = 8/2c. W/L = 12/2d. W/L = 25/2

Sol:For 90nm, Vt= 0.14 V, k`=13µA/V2

a. at Vds=0.5 V, W/L=5/2

Vds = Vgs – Vt

0.5 < 1 – 0.14

0.5 < 0.86 ……… Hence transistor will operate in linear region

−−= dsdsgsd V V Vt V

L

W k I

2

2

1)(`

−−=

− 26 )5.0(2

1)5.0)(14.01()

2

5)(1013( x I d

[ ]125.0)5.0)(86.0()1025.3( 5−=

−

x I d

[ ]305.0)1025.3( 5−= x I d

uA I d 9125.9=

at Vds=0.75 V, W/L=5/2

Vds = Vgs – Vt

0.75 < 1 – 0.14





L

W k I 2

2

1)(`

−−=

− 26

)75.0(2

1

)75.0)(14.01()2

5

)(1013( x I d

[ ]36375.0)1025.3( 5−= x I d

uA I d 821.11=

at Vds=1 V, W/L=5/2

Vds = Vgs – Vt

1 > 1 – 0.14

1 > 0.86 ……… Hence transistor will operate in saturation region

[ ]2)(`2

1Vt V

L

W k I gsd −=

[ ]26 )14.01(2

5)1013(

2

1−=

− x I d

[ ]7396.010625.1 5−= x I d

uA I d 01.12=

b. at Vds=0.5 V, W/L=8/2

Vds = Vgs – Vt

0.5 < 1 – 0.14



L

W k I

2

2

1)(`

−−=− 26 )5.0(

21)5.0)(14.01()

28)(1013( x I d

[ ]125.0)5.0)(86.0()102.5( 5−=

−

x I d

[ ]305.0)102.5( 5−= x I d

uA I d 86.15=



at Vds=0.75 V, W/L=8/2

Vds = Vgs – Vt

0.75 < 1 – 0.14



L

W k I

2

2

1)(`

−−=

− 26 )75.0(2

1)75.0)(14.01()

2

8)(1013( x I d

[ ]36375.0)102.5( 5−= x I d

uA I d 915.18=

at Vds=1 V, W/L=8/2

Vds = Vgs – Vt

1 > 1 – 0.14


[ ]2)(`2

1Vt V

L

W k I gsd −=

[ ]26 )14.01(

28)1013(

21 −=

−

x I d

[ ]7396.0106.2 5−= x I d

uA I d 22.19=

c. at Vds=0.5 V, W/L=12/2

Vds = Vgs – Vt

0.5 < 1 – 0.140.5 < 0.86 ……… Hence transistor will operate in linear region


L

W k I

2

2

1)(`

−−=

− 26 )5.0(2

1)5.0)(14.01()

2

12)(1013( x I d



[ ]125.0)5.0)(86.0()108.7( 5−=

−

x I d

[ ]305.0)108.7( 5−= x I d

uA I d 79.23=

at Vds=0.75 V, W/L=12/2

Vds = Vgs – Vt

0.75 < 1 – 0.14



L

W k I

2

2

1)(`

−−=− 26 )75.0(

21)75.0)(14.01()

212)(1013( x I d

[ ]36375.0)108.7( 5−= x I d

uA I d 3725.28=

at Vds=1 V, W/L=12/2

Vds = Vgs – Vt

1 > 1 – 0.141 > 0.86 ……… Hence transistor will operate in saturation region

[ ]2)(`2

1Vt V

L

W k I gsd −=

[ ]26 )14.01(2

12)1013(

2

1−=

−

x I d

[ ]7396.0109.3 5−= x I d

uA I d 84.28=

d. at Vds=0.5 V, W/L=25/2

Vds = Vgs – Vt

0.5 < 1 – 0.14





L

W k I 2

2

1)(`

−−=

− 26 )5.0(2

1)5.0)(14.01()

2

25)(1013( x I d

[ ]125.0)5.0)(86.0()10625.1( 4−=

−

x I d

[ ]305.0)10625.1( 4−= x I d

uA I d 56.49=

at Vds=0.75 V, W/L=25/2

Vds = Vgs – Vt

0.75 < 1 – 0.140.75 < 0.86 ……… Hence transistor will operate in linear region


L

W k I

2

2

1)(`

−−=

− 26 )75.0(2

1)75.0)(14.01()

2

25)(1013( x I d

[ ]36375.0)10625.1( 4−= x I d

uA I d 109.59=

at Vds=1 V, W/L=25/2

Vds = Vgs – Vt

1 > 1 – 0.14


[ ]2)(`2

1Vt V

L

W k I gsd −=

[ ]26 )14.01(2

25)1013(

2

1−=

−

x I d

[ ]7396.010125.8 5−= x I d

uA I d 09.60=



VSS

VDD

Vout

A

B

C

Q2-2. Design the static complementary pullup and pulldown networks for theselogic expressions:

a. (a + b + c)`b. [(a + b)c]`

c.

(a+b)(c+d)

Sol:a. (a + b + c)`

= a`b`c` ………. For Pullup Network

= a+b+c ……..... For Pulldown Network

b. [(a + b)c]`

= (a + b)` + c`

= a`b` + c` ……………….For pullup network = (a + b)c ………………. For pulldown network

a

b

c

a b

c

VDD

Vss

Vout



c. (a+b)(c+d)

= a(c + d) + b(c + d) ………. For pullup network = [(a + b)(c + d)]`

= [(a + b)` + (c + d)`]

= [a`b` + c`d`] ……………… For pulldown network

Y

Q2-3. Write the defining logic equation for each complex gate below:

a. AOI-22b. OAI-22c. AOI-212d. OAI-321e. AOI-2222

Sol:

a) AOI-22

VSS

VDD

a b

c d

a

b

c

d



b) OAI-22

c) AOI-212

d) OAI-321

e) AOI-2222

Q2-6. What is the difference in the fall time of a two input, static complementary NOR

gate (assuming a minimum-size load capacitance), when one pulldown and when twopulldowns are activated?

Sol:

Expression for NOR gate is: (a + b)`= a`b` …………… For pullup network

= (a + b) ………… For pulldown network

Vdd

a



We know that discharging time of capacitor is given by:

Dt

eV v−

= max -------------------------- (1)

where v=vout

Vmax=VDD

λ=RC

t=tf

eq(1) becomes

RC

tf

eVdd Vout

−

= . ------------------------ (2)

Replacing Internal Resistance of n-MOS Transistor, when any one of

pulldowns are activated.

Here total resistance is:

R=(Rn + RL) & C=CL

eq(2) becomes

L L

R

C R Rn

t

eVdd Vout )(

.+

−

= -------------------- (3)

Considering the falling edge, the falling time is considered to be from 90%

of Vmax (i.e. VDD) to 10% of Vmax, hence we have to calculate Time

required for (10% - 90%) of Vdd (i.e. 80% of Vdd).

Hence Vout = 0.1 VDD – 0.9

VDD



= (0.1 – 0.9) VDD

eq(3) becomes

L Ln

L LPn

C R Rtf

C R R

tf

e

eVdd Vdd

)(

)(

9.01.0

.)9.01.0(

+

−

+

−

=−

=−

Taking ln both sides:

L Ln C R R

tf

)()9.0ln()1.0ln(

+

=−

f L Ln t C R R =+ ))(9.0

1.0ln(

L LPF C R Rt )(2.2 +−=−

Assuming CL = minimum =1

Now when both pulldowns are activated, considering equation (ii):

RC

tf

eVdd Vout −

= . ------------------------ (2)

Replacing Internal Resistance of n-MOS Transistor, when any both of

pulldowns are

activated:

As both transistors

are same (i.e. n-

MOS) having same characteristics and internal structure, hence both

have same internal resistance

R = Rn || Rn

)(2.2 LnF R Rt +=



Rn R

Rn R

Rn Rn R

5.0

21

111

=

=

+=

Here total resistance is:

R=(R + RL) & C=CL

eq(2) becomes

L L

R

C R Rn

t

eVdd Vout )5.0(. +

−

= -------------------- (3)

Considering the falling edge, the falling time is considered to be from 90%

of Vmax (i.e. VDD) to 10% of Vmax, hence we have to calculate Time

required for (10% - 90%) of Vdd (i.e. 80% of Vdd).

Hence Vout = 0.1 VDD – 0.9

VDD

= (0.1 – 0.9) VDD

eq(3) becomes

L Ln

L LPn

C R R

tf

C R R

tf

e

eVdd Vdd

)5.0(

)5.0(

9.01.0

.)9.01.0(

+

−

+

−

=−

=−

Taking ln both sides:

L Ln C R R

tf

)5.0()9.0ln()1.0ln(

+

=−

f L Ln t C R R =+ )5.0)(

9.0

1.0ln(

L LnF C R Rt )5.0(2.2 +−=−

Assuming CL = minimum = no effect



Problem Statement2-3:

If the input to an inverter is a ramp and not a step is the fall time calculation of

tf =2.2(Rn+RL) CL optimistic or pessimistic? Explain your answer.

Solution:

Since ramp is a constantly increasing test input which means it cannot give anyinformation about delay measurement. And moreover the linearly increasing input

voltage may destroy the inverter at some voltage level. Therefore from these aspects the

result of above equation may lead us to pessimistic result.

)5.0(2.2 LnF R Rt +=

)2(1.1

)

2

2(2.2

)2

(2.2

LnF

n

F

L

n

F

R Rt

RL Rt

R R

t

+=

+=

+=

)2(1.1 LnF R Rt +=

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2.9 Problems Solved