2007 EDITION - Semiconductor Industry Association international technology roadmap for semiconductors

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  • INTERNATIONAL TECHNOLOGY ROADMAP

    FOR SEMICONDUCTORS

    2007 EDITION

    ASSEMBLY AND PACKAGING

    THE ITRS IS DEVISED AND INTENDED FOR TECHNOLOGY ASSESSMENT ONLY AND IS WITHOUT REGARD TO ANY COMMERCIAL CONSIDERATIONS PERTAINING TO INDIVIDUAL PRODUCTS OR EQUIPMENT.

  • THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2007

    TABLE OF CONTENTS Assembly and Packaging ..................................................................................................... 1

    Scope...............................................................................................................................................1 Difficult Challenges ..........................................................................................................................1 Single Chip Packaging.....................................................................................................................4

    Overall Packaging Requirements ................................................................................................................4 Electrical Requirements ...............................................................................................................................8 Thermal Requirements.................................................................................................................................8 Mechanical Requirements............................................................................................................................9 Cost ..............................................................................................................................................................9 Reliability ....................................................................................................................................................10 Chip to Package Substrate ........................................................................................................................11 Package Substrate to Board Interconnect .................................................................................................16 Package Substrates ...................................................................................................................................18

    Wafer Level Packaging..................................................................................................................23 Wafer Level Package Developments and Trends .....................................................................................31 Difficult Challenges for WLP ......................................................................................................................32 Examples for Emerging Wafer Level Package Technologies:...................................................................32

    System in Package ........................................................................................................................35 Definition of SiP..........................................................................................................................................36 SiP versus SoC ..........................................................................................................................................37 System Level Requirements ......................................................................................................................38 SiP Reliability Challenges ..........................................................................................................................42 Thermal Management ................................................................................................................................45 The Need for Co-Design Tools ..................................................................................................................46 Wire and Die Bonding for SiP ....................................................................................................................48 Testing of SiP.............................................................................................................................................50

    Packaging for Specialized functions ..............................................................................................51 Optoelectronic Packaging ..........................................................................................................................51 RF and Millimeter Wave Packaging...........................................................................................................56 Medical and Bio Chip Packaging ...............................................................................................................57 MEMS Device Packaging...........................................................................................................................58 Electronics in Textiles and Wearable Electronics ......................................................................................60 Automotives Electronics.............................................................................................................................61 Solar Cell Packaging..................................................................................................................................62

    Advanced Packaging Elements .....................................................................................................63 Embedded and Integrated Active and Passive Devices ............................................................................63 Wafer Thinning and Singulation.................................................................................................................65 Packaging Materials Requirements ...........................................................................................................65 Environmental issues .................................................................................................................................70

    Equipment Requirements for Emerging Package Types...............................................................70 Cross-Cut ITWG Issues.................................................................................................................71

    Design ........................................................................................................................................................71 Interconnect ...............................................................................................................................................71 RF/AMS Wireless.......................................................................................................................................71 Environment, Safety & Health....................................................................................................................72 Modeling & Simulation ...............................................................................................................................72

  • Test.............................................................................................................................................................72 Glossary.........................................................................................................................................73 References ....................................................................................................................................74 Appendix A: Consortia Engaged in Packaging..............................................................................75

    LIST OF FIGURES Figure AP1 The Use of Compliant/Flexible Electrical I/O Can Potentially Eliminate the Need for Underfill.........................................................................................11 Figure AP2 Micro Bump and Pillar Bump Structures for High Reliable Chip-to-substrate Interconnects ........................................................................11 Figure AP3 Examples of Forward Bond Loop ......................................................................13 Figure AP4 Example of Die- to- die Wire Bonding ...............................................................13 Figure AP5 Example of Cascade Bonding ...........................................................................14 Figure AP6 Bonding Overhang Die ......................................................................................14 Figure AP7 Wire Bond on Both Sides of Lead Frame Substrate..........................................14 Figure AP8 Examples of Copper Pillar Bumps (a) and Assembled Copper Pillar (b)...........15 Figure AP9 Example of Copper Pillar Bumps with Solder Tips ............................................15 Figure AP10 Examples of Wafer Level Packaging Types ......................................................24 Figure AP11 Basic Process Flow Via-first versus Via Last.....................................................33 Figure AP12 Roadmap for 3D Integration using TSV.............................................................34 Figure AP13 Example of a Side-by-side Solution of an Fanout WLP (a) and a Reconstituted Wafer (b).....................................................................................35 Figure AP14 Beyond CMOS Scaling......................................................................................36 Figure AP15 Categories of SiP...............................................................................................37 Figure AP16 Examples of Heat Sink Technologies and Integration of Fluidic Interconnections with CMOS Chips.......

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