2000 Test RoadmapUpdate

Don Edenfeld

Mike Rodgers

ITRS Test TWG

December 6, 2000 2

Test TWG MembershipUS Members

Name CompanyMark Baber LucentBill Ortner LucentYi Cai LucentRichard Antley TIMarc Mydill TIAnne Gattiker IBMDon Wheater IBM Phil Nigh IBMAtul Goel AgilentPeter Maxwell AgilentTim Sheen TeradyneLee Song TeradynePaul Roddy MotorolaJay Bedsole MotorolaDon Edenfeld Intel Roger Barth IntelMichael RogersIntelRochit Rajsuman AdvantestYervant Zorian LogicVision

International Members

NameCompany

Peter MuhmenthalerInfineon

Rene Segers PhilipsKazumi Hatayama

HitachiMr. Ohta

MatsushitaMr. Satou

HitachiKang Chil Lee Hyundai

December 6, 2000 3

2000 Test Chapter Update DFT Tester Table

The DFT Tester Table debuted in the 1999 edition The 2000 update represents the trends that were described

in the 1999 edition Significant changes are intended to clarify the requirements

based on the significant industry confusion evident in 2000 This table will receive significant focus for the 2001 edition

Commodity Flash Table In 2000 minor adjustments were made to the trends that

were described in the 1999 edition Requirements for a scan vector capability were added to

address a growing trend towards integration of logic on flash devices

December 6, 2000 4

Industry Trend - CostManufacturing cost continues to be the

dominant factor in test Test represents an increasing percentage of

overall device manufacturing cost 1999 edition cost targets begin to trend cost in the

right direction Cost of Silicon Mfg and Test

0.0000001

0.000001

0.00001

0.0001

0.001

0.01

0.11

1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012

cost: cents /transistor

Fab capital / transistor

Test capital / transistor

Based on ‘97 SIA Roadmap Data & ‘99 ITRS Roadmap

1999 Roadmap

December 6, 2000 5

Industry Trend - SoCDemand for small form factors and low power

solutions drive increased integration

Increasing levels of design integration drive new test challenges

Integration of logic, analog, RF, RAM, ROM, and/or Flash on a single chip is on the horizon

How to test highly integrated components at a cost consistent with the market for these devices?

Flash

SRAM

DSP

uController

RF An

alog

December 6, 2000 6

Industry Trend - Wireless

Dramatic growth in the consumer wireless market segment over the foreseeable future requires cost effective solutions for RF testing

2.4GHz and 5.2GHz bands are targeted for a large number of products in many applications (Bluetooth, 802.11x, …)

December 6, 2000 7

Industry Trend - HSS

High speed serial (HSS) technologies are not just for long range communication anymore Serial communication is becoming the technology

of choice for peripheral connectivity Slow parallel bus architectures are being replaced

by Firewire, Infiniband, and other HSS solutions Traditional rack and stack approach to test of high

speed ports is too expensive

December 6, 2000 8

Industry Trend – Burn-in

Shrinking fab process feature sizes and increasing transistor performance challenge device burn-in infrastructure and capability

Capability Exists

Technology Exists $$

Technology Development Required $$$$

Die Size (mils)

BI

Po

wer

(W

)

Mean Power in Burn-In Increased transistor

performance leads to increasing power and thermal demand in burn-in

Burn-in cost trend is increasing faster than other parameters as a component of overall test cost

December 6, 2000 9

Industry Trend - Power

Once an afterthought, precise power delivery is crucial for high performance designs Voltage droop during test has

a direct impact on manufacturing yield

High current power delivery requires accurate modeling and simulation of the entire power path

High precision analog circuits require very stable references

0A

IDD

VCC

Time

DUT Current Load Step

Voltage as Seen by DUT

December 6, 2000 10

Industry Trend - Diagnosis Validation and debug of complex designs require an

increased level of interactivity between design automation and test equipment Correlation must be established between a device failure

and the actual failing circuit node Automation tools are needed to shorten the process of

tracing failures to the failing circuit as a direct impact to time to market

Emerging packaging technologies compromise existing failure analysis techniques Flip-chip and multi-chip packaging require new approaches

to probing for diagnosis and failure analysis

December 6, 2000 11

Industry Challenge

The ATE business model must change to adapt to evolving market directions The high performance functional tester market

segment is declining Low performance functional tester and DFT tester

market segments are growing The industry must come together to define

common requirements for DFT tester capability

December 6, 2000 12

Manufacturing Cost Initiatives Technologies are emerging to lower equipment

capital cost and increase test module throughput The industry is driving toward DFT technology to move test

complexity onto the die and away from the test equipment Reduction in test equipment complexity should result in a

significant decrease in tester cost over the 5 year horizon

DFT will be used to enable lower performance functional testers to test high performance designs

DFT techniques that reduce device pin count requirements for test enable increased parallelism and module throughput

Wafer level burn-in and test exploits high parallelism to increase throughput and decrease unit cost

December 6, 2000 13

System-on-a-Chip

Solutions must emerge to solve Big D / Big A test challenges Today’s environment is structured for Little D / Big

A or Big D / Little A

SoC testing requires a disciplined DFT approach Fundamental research is needed to define and prove

Analog BIST and DFT techniques Extensive digital DFT techniques must be applied Embedded flash and PROM test time threatens test

module throughput

Test cost is a primary concern

December 6, 2000 14

High Speed Serial

High performance digital interfaces are approaching the analog domain for testability High speed serial digital interfaces must be

characterized and tested in the analog domain Analog compliance

testing is time consuming

Trade-off between increased tester resources, test time, and test effectiveness

December 6, 2000 15

2001 Edition Test Chapter Plans Iddq Testing High Frequency Serial Communications High Performance ASIC High Performance Microprocessor Low-end Microcontrollers Mixed Signal Commodity DRAM Commodity Flash Embedded DRAM and Embedded Flash DFT Test Equipment Design-for-Test Automation Tools System-on-a-Chip Failure Analysis ATE Software

Proposed for 2001