1.8-GHz, LOW DISTORTION, CURRENT-FEEDBACK AMPLIFIER · 1.8-GHz, LOW DISTORTION, CURRENT-FEEDBACK AMPLIFIER 23 ... OPA695 ±5-V, 1.7-GHz Low Distortion CFB Amplifier 1 Please be aware

��

1FEATURES DESCRIPTION

APPLICATIONS

_

+

768 Ω

+7.5 V

49.9 ΩVI

-7.5 V

50 Ω Source

Low-Noise, Low-Distortion, Wideband Application Circuit

NOTE: Power supply decoupling capacitors not shown

768 Ω

50 Ω

THS320149.9 Ω

50 Ω

0

1

2

3

4

5

6

7

8

100 k 1 M 10 M 100 M 1 G 10 G

f - Frequency - Hz

No

nin

vert

ing

Gai

n -

dB

NONINVERTING SMALL SIGNALFREQUENCY RESPONSE

RF = 768 Ω

Gain = 2.RL = 100 Ω,VO = 0.2 VPP.VS = ±7.5 V

THS3201

www.ti.com ............................................................................................................................................................. SLOS416C–JUNE 2003–REVISED JUNE 2009

1.8-GHz, LOW DISTORTION, CURRENT-FEEDBACK AMPLIFIER

23• Unity-Gain Bandwidth: 1.8 GHz The THS3201 is a wideband, high-speedcurrent-feedback amplifier, designed to operate over• High Slew Rate: 6700 V/µs (G = 2 V/V,a wide supply range of ±3.3 V to ±7.5 V for today'sRL = 100 Ω, 10-V Step) high performance applications.• IMD3: –78 dBc at 20 MHz: (G = 10 V/V,The wide supply range, combined with low distortionRL = 100 Ω, 2-VPP Envelope) and high slew rate, makes the THS3201 ideally• Noise Figure: 11 dB (G = 10 V/V, RG = 28 Ω, suited for arbitrary waveform driver applications. The

RF = 255 Ω) distortion performance also enables drivinghigh-resolution and high-sampling rate• Input-Referred Noise (f >10 MHz)analog-to-digital converters (ADCs).– Voltage Noise: 1.65 nV/√HzIts high voltage operation capabilities make the– Noninverting Current Noise: 13.4 pA/√HzTHS3201 especially suitable for many test,– Inverting Current Noise: 20 pA/√Hz measurement, and ATE applications where lower

• Output Drive: 100 mA voltage devices do not offer enough voltage swingcapability. Output rise and fall times are nearly• Power-Supply Voltage Range: ±3.3 V to ±7.5 Vindependent of step size (to first-orderapproximation), making the THS3201 ideal forbuffering small to large step pulses with excellent• Test and Measurement linearity in high dynamic systems.

• ATEThe THS3201 is offered in a 5-pin SOT-23, 8-pin• High-Resolution, High-Sampling Rate ADCSOIC, and an 8-pin MSOP with PowerPAD™Driverspackages.• High-Resolution, High-Sampling Rate DAC

Output Buffers RELATED DEVICES AND DESCRIPTIONSDEVICE DESCRIPTION

THS3202 ±7.5-V, 2-GHz Dual Low Distortion CFB AmplifierTHS3001 ±15-V, 420-MHz Low Distortion CFB AmplifierTHS3061/2 ±15-V, 300-MHz Low Distortion CFB AmplifierTHS3122 ±15-V, Dual CFB Amplifier With 350 mA DriveOPA695 ±5-V, 1.7-GHz Low Distortion CFB Amplifier

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright © 2003–2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

http://focus.ti.com/docs/prod/folders/print/ths3201.htmlhttp://focus.ti.com/docs/prod/folders/print/ths3202.htmlhttp://focus.ti.com/docs/prod/folders/print/ths3001.htmlhttp://focus.ti.com/docs/prod/folders/print/ths3061.htmlhttp://focus.ti.com/docs/prod/folders/print/ths3062.htmlhttp://focus.ti.com/docs/prod/folders/print/ths3122.htmlhttp://focus.ti.com/docs/prod/folders/print/opa695.html

ABSOLUTE MAXIMUM RATINGS

PACKAGE DISSIPATION RATINGS (1)

RECOMMENDED OPERATING CONDITIONS

THS3201

SLOS416C–JUNE 2003–REVISED JUNE 2009 ............................................................................................................................................................. www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

Over operating free-air temperature range unless otherwise noted. (1)

UNIT

VS Supply voltage 16.5 V

VI Input voltage ±VSIO Output current 175 mA

VID Differential input voltage ±3 V

Continuous power dissipation See Dissipation Rating Table

TJ Maximum junction temperature (2) +150°C

TJ Maximum junction temperature, continuous operation, long term reliability (3) +125°C

TA Operating free-air temperature range –40°C to +85°C

TSTG Storage temperature range –65°C to +150°C

HBM 3000 V

ESD ratings CDM 1500 V

MM 100 V

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods maydegrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyondthose specified is not implied.

(2) The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings maycause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These arestress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.

(3) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature mayresult in reduced reliability and/or lifetime of the device.

POWER RATING (3)θJC θJA(2) (TJ = +125°C)PACKAGE (°C/W) (°C/W)

TA ≤ +25°C TA= +85°C

DBV (5) 55 255.4 391 mW 156 mW

D (8) 38.3 97.5 1.02 W 410 mW

DGN (8) (1) 4.7 58.4 1.71 W 685 mW

DGK (8 pin) 54.2 260 385 mW 154 mW

(1) The THS3201 may incorporate a PowerPAD™ on the underside of the chip. This acts as a heat sinkand must be connected to a thermally dissipative plane for proper power dissipation. Failure to do somay result in exceeding the maximum junction temperature which could permanently damage thedevice. See TI technical briefs SLMA002 and SLMA004 for more information about utilizing thePowerPAD thermally enhanced package.

(2) This data was taken using the JEDEC standard High-K test PCB.(3) Power rating is determined with a junction temperature of +125°C. This is the point where distortion

starts to substantially increase. Thermal management of the final PCB should strive to keep thejunction temperature at or below +125°C for best performance and long term reliability.

MIN MAX UNITDual supply ±3.3 ±7.5

Supply voltage VSingle supply 6.6 15

TA Operating free-air temperature range –40 +85 °C

2 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated

Product Folder Link(s): THS3201

http://focus.ti.com/docs/prod/folders/print/ths3201.htmlhttp://www-s.ti.com/sc/techlit/SLMA002 http://www-s.ti.com/sc/techlit/SLMA0024http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SLOS416C&partnum=THS3201http://focus.ti.com/docs/prod/folders/print/ths3201.html

PIN ASSIGNMENTS

VOUT

VS-

IN+

VS+

IN-3

2

4

51

VOUT-

VS-

VIN-

VS+

VIN+

NC = No internal connection.

See Note A.

1

2

3

4

8

7

6

5

NC

NC

NC

THS3201


PACKAGE/ORDERING INFORMATION (1)

PART NUMBER PACKAGE TYPE PACKAGE MARKING TRANSPORT MEDIA, QUANTITYTHS3201D Rails, 75

SOIC-8 —THS3201DR Tape and Reel, 2500

THS3201DBVT Tape and Reel, 250SOT-23 BEO

THS3201DBVR Tape and Reel, 3000THS3201DGN Rails, 80

MSOP-8-PP BENTHS3201DGNR Tape and Reel, 2500THS3201DGK Rails, 80

MSOP-8 BGPTHS3201DGKR Tape and Reel, 2500

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com.

DBV PACKAGE D, DGN, DGK PACKAGESSOT23-5 SOIC-8, MSOP-8

(TOP VIEW) (TOP VIEW)

A. If a PowerPAD is used, it is electricallyisolated from the active circuitry.

Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 3


http://focus.ti.com/docs/prod/folders/print/ths3201.htmlhttp://www.ti.comhttp://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SLOS416C&partnum=THS3201http://focus.ti.com/docs/prod/folders/print/ths3201.html

ELECTRICAL CHARACTERISTICS: VS = ±7.5 V

THS3201


At RF = 768 Ω, RL = 100 Ω, and G = +2, unless otherwise noted.THS3201

TYP OVER TEMPERATUREPARAMETER TEST CONDITIONS MIN/0°C to –40°C to+25°C +25°C UNITS TYP/+70°C +85°C MAX

AC PERFORMANCE

G = +1, RF = 1.2 kΩ 1.8 GHz

G = +2, RF = 768 Ω 850Small-signal bandwidth, –3 dB Typ(VO = 200 mVPP) G = +5, RF = 619 Ω 565 MHz

G = +10, RF = 487 Ω 520

Bandwidth for 0.1 dB flatness G = +2, VO = 200 mVpp 380 MHz Typ

Large-signal bandwidth G = +2, VO = 2 Vpp 880 MHz Typ

G = +2, VO = 5-V step, Rise/Fall 5400/4000Slew rate V/µs Typ

G = +2, VO = 10-V step, Rise/Fall 9800/6700

Rise and fall time G = +2, VO = 4-V step, Rise/Fall 0.7/0.9 ns Typ

Settling time to 0.1% 20G = –2, VO = 2-V step ns Typ

Settling time to 0.01% 60

Harmonic distortion

RL = 100 Ω –64 dBc Typ2nd-order harmonic G = +5, f = 10 MHz,VO = 2 Vpp RL = 100 Ω –73 dBc Typ3rd-order harmonic

G = +10, fc = 20 MHz, Δf = 1 MHz,Third-order intermodulation distortion (IMD3) –78 dBc TypVO(envelope) = 2 VppG = +10, fc = 100 MHz, RF = 255 Ω,Noise figure 11 dB TypRG = 28

Input voltage noise f > 10 MHz 1.65 nV/√Hz Typ

Input current noise (noninverting) 13.4 pA/√Hz Typf > 10 MHz

Input current noise (inverting) 20 pA/√Hz Typ

NTSC 0.008% TypDifferential gain

PAL 0.004% TypG = +2, RL = 150 Ω,RF = 768 Ω NTSC 0.007° Typ

Differential phasePAL 0.011° Typ

DC PERFORMANCE

Open-loop transimpedance gain VO = ±1 V, RL = 1 kΩ 300 200 140 120 kΩ Min

Input offset voltage ±0.7 ±3 ±3.8 ±4 mV Max

Average offset voltage drift ±10 ±13 µV/°C Typ

Input bias current (inverting) ±13 ±60 ±80 ±85 µA MaxVCM = 0 V

Average bias current drift (–) ±300 ±400 nA/°C Typ

Input bias current (noninverting) ±14 ±35 ±45 ±50 µA Max

Average bias current drift (+) ±300 ±400 nA/°C Typ



http://focus.ti.com/docs/prod/folders/print/ths3201.htmlhttp://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SLOS416C&partnum=THS3201http://focus.ti.com/docs/prod/folders/print/ths3201.html

THS3201


ELECTRICAL CHARACTERISTICS: VS = ±7.5 V (continued)At RF = 768 Ω, RL = 100 Ω, and G = +2, unless otherwise noted.

THS3201


INPUT

Common-mode input range ±5.1 ±5 ±5 ±5 V Min

Common-mode rejection ratio VCM = ±3.75 V 71 60 58 58 dB Min

Inverting input impedance, Zin Open loop 16 Ω Typ

Noninverting 780 kΩ TypInput resistance

Inverting 11 Ω Typ

Input capacitance Noninverting 1 pF Typ

OUTPUT

RL = 1 kΩ ±6 ±5.9 ±5.8 ±5.8 V MinVoltage output swing

RL = 100 Ω ±5.8 ±5.7 ±5.5 ±5.5 V Min

Current output, sourcing 115 105 100 100 mA MinRL = 20 Ω

Current output, sinking 100 85 80 80 mA Min

Closed-loop output impedance G = +1, f = 1 MHz 0.01 Ω Typ

POWER SUPPLY

Minimum operating voltage Absolute minimum ±3.3 ±3.3 ±3.3 V Min

Maximum operating voltage Absolute maximum ±8.25 ±8.25 ±8.25 V Max

Maximum quiescent current 14 18 21 21 mA Max

Power-supply rejection (+PSRR) VS+ = 7 V to 8 V 69 63 60 60 dB Min

Power-supply rejection (–PSRR) VS– = –7 V to –8 V 65 58 55 55 dB Min




ELECTRICAL CHARACTERISTICS: VS = ±5 V

THS3201


At RF = 715 Ω, RL = 100 Ω, and G = +2, unless otherwise noted.THS3201


AC PERFORMANCE

G = +1, RF= 1.2 kΩ 1.3 GHz

G = +2, RF = 715 Ω 725Small-signal bandwidth, –3dB Typ(VO = 200 mVPP) G = +5, RF = 576 Ω 540 MHz

G = +10, RF = 464 Ω 480

Bandwidth for 0.1 dB flatness G = +2, VO = 200 mVPP 170 MHz Typ

Large-signal bandwidth G = +2, VO = 2 VPP 900 MHz Typ

Slew rate G = +2, VO = 5-V step, Rise/Fall 5200/4000 V/µs Typ

Rise and fall time G = +2, VO = 4-V step, Rise/Fall 0.7/0.9 ns Typ

Settling time to 0.1% 20 ns TypG = –2, VO = 2-V step

Settling time to 0.01% 60 ns Typ

Harmonic distortion

RL = 100 Ω –69 dBc Typ2nd-order harmonic G = +5, f = 10 MHz,VO = 2 Vpp RL = 100 Ω –75 dBc Typ3rd-order harmonic

G = +10, fc = 20 MHz, Δf = 1 MHz,Third-order intermodulation distortion (IMD3) –81 dBc TypVO(envelope) = 2 VPPG = +10, fc = 100 MHz, RF = 255 Ω,Noise figure 11 dB TypRG = 28

Input voltage noise f > 10 MHz 1.65 nV/√Hz Typ

Input current noise (noninverting) 13.4 pA/√Hz Typf > 10 MHz

Input current noise (inverting) 20 pA/√Hz Typ

NTSC 0.006% TypDifferential gain

PAL 0.004% TypG = +2, RL = 150 Ω,RF = 768 Ω NTSC 0.03° Typ

Differential phasePAL 0.04° Typ

DC PERFORMANCE

Open-loop transimpedance gain VO = +1 V, RL = 1 kΩ 300 200 140 120 kΩ Min

Input offset voltage ±0.7 ±3 ±3.8 ±4 mV Max

Average offset voltage drift ±10 ±13 ±V/°C Typ

Input bias current (inverting) ±13 ±60 ±80 ±85 µA MaxVCM = 0 V

Average bias current drift (–) ±300 ±400 nA/°C Typ

Input bias current (noninverting) ±14 ±35 ±45 ±50 µA Max

Average bias current drift (+) ±300 ±400 nA/°C Typ




THS3201


ELECTRICAL CHARACTERISTICS: VS = ±5 V (continued)At RF = 715 Ω, RL = 100 Ω, and G = +2, unless otherwise noted.

THS3201


INPUT

Common-mode input range ±2.6 ±2.5 ±2.5 ±2.5 V Min

Common-mode rejection ratio VCM = ±2.5 V 71 60 58 58 dB Min

Inverting input impedance, ZIN Open loop 17.5 Ω Typ

Noninverting 780 kΩ TypInput resistance

Inverting 11 Ω Typ

Input capacitance Noninverting 1 pF Typ

OUTPUT

RL = 1 kΩ ±3.65 ±3.5 ±3.45 ±3.4Voltage output swing V Min

RL = 100 Ω ±3.45 ±3.33 ±3.25 ±3.2

Current output, sourcing 115 105 100 100 mA MinRL = 20 Ω

Current output, sinking 100 85 80 80 mA Min

Closed-loop output impedance G = +1, f = 1 MHz 0.01 Ω Typ

POWER SUPPLY

Minimum operating voltage Absolute minimum ±3.3 ±3.3 ±3.3 V Min

Maximum operating voltage Absolute maximum ±8.25 ±8.25 ±8.25 V Max

Maximum quiescent current 14 16.8 19 20 mA Max

Power-supply rejection (+PSRR) VS+ = 4.5 V to 5.5 V 69 63 60 60 dB Min

Power-supply rejection (–PSRR) VS– = –4.5 V to –5.5 V 65 58 55 55 dB Min




TYPICAL CHARACTERISTICS

Table of Graphs (VS = ±7.5 V)

THS3201


FIGURENoninverting small-signal frequency response 1, 2Inverting small-signal frequency response 3Noninverting large-signal frequency response 4Inverting large-signal frequency response 50.1 dB gain flatness frequency response 6Capacitive load frequency response 7Recommended switching resistance vs Capacitive Load 82nd harmonic distortion vs Frequency 93rd harmonic distortion vs Frequency 102nd harmonic distortion, G = 2 vs Output voltage 113rd harmonic distortion, G = 2 vs Output voltage 122nd harmonic distortion, G = 5 vs Output voltage 133rd harmonic distortion, G = 5 vs Output voltage 142nd harmonic distortion, G = 10 vs Output voltage 153rd harmonic distortion, G = 10 vs Output voltage 16Third-order intermodulation distortion (IMD3) vs Frequency 17S-Parameter vs Frequency 18, 19Input voltage and current noise vs Frequency 20Noise figure vs Frequency 21Transimpedance vs Frequency 22Input offset voltage vs Case Temperature 23Input bias and offset current vs Case Temperature 24Slew rate vs Output voltage step 25Settling time 26, 27Quiescent current vs Supply voltage 28Output voltage vs Load resistance 29Rejection ratio vs Frequency 30Noninverting small-signal transient response 31Inverting large-signal transient response 32Overdrive recovery time 33Differential gain vs Number of loads 34Differential phase vs Number of loads 35Closed-loop output impedance vs Frequency 36




Table of Graphs (VS = ±5 V)

THS3201


FIGURENoninverting small-signal frequency response 37Inverting small-signal frequency response 380.1 dB gain flatness frequency response 392nd harmonic distortion vs Frequency 403rd harmonic distortion vs Frequency 412nd harmonic distortion, G = 2 vs Output voltage 423rd harmonic distortion, G = 2 vs Output voltage 432nd harmonic distortion, G = 5 vs Output voltage 443rd harmonic distortion, G = 5 vs Output voltage 452nd harmonic distortion, G = 10 vs Output voltage 463rd harmonic distortion, G = 10 vs Output voltage 47Third-order intermodulation distortion (IMD3) vs Frequency 48S-Parameter vs Frequency 49, 50Slew rate vs Output voltage step 51Noninverting small-signal transient response 52Inverting large-signal transient response 53Overdrive recovery time 54




VS = ±7.5 V Graphs

0

1

2

3

4

5

6

7

8

100 k 1 M 10 M 100 M 1 G 10 G

f - Frequency - Hz

No

nin

vert

ing

Gai

n -

dB

RF = 619 Ω

RF = 768 Ω

RF = 1 kΩ

Gain = 2.RL = 100 Ω,VO = 0.2 VPP.VS = ±7.5 V

-4-2

0

246

8

10

12

14

161820

2224

100 k 1 M 10 M 100 M 1 G 10 G

f - Frequency - Hz

RL = 100 Ω,VO = 0.2 VPP.VS = ±7.5 V

G = 10, RF = 487 Ω

G = 5, RF = 619 Ω

G = 2, RF = 768 Ω

G =1, RF = 1.2 kΩ

No

nin

vert

ing

Gai

n -

dB

-4-2

02

46

810

12

1416

18

20

22

24

100 k 1 M 10 M 100 M 1 G 10 G

f - Frequency - Hz

RL = 100 Ω,VO = 0.2 VPP.VS = ±7.5 V

G = -10, RF = 499 Ω

G = -5, RF = 549 Ω

G = -2, RF = 576 Ω

G = -1, RF = 619 Ω

No

nin

vert

ing

Gai

n -

dB

5.6

5.7

5.8

5.9

6.1

6.2

6.3

6.4

100 k 10 M 100 M 1 G 10 G

6

f - Frequency - Hz

Gain = 2,RF = 768 Ω,RL = 100 Ω,VO = 0.2 VPP,VS = ±7.5 V

1 M

No

nin

vert

ing

Gai

n -

dB

-4

-2

0

2

4

6

8

10

12

14

16

100 k 1 M 10 M 100 M 1 G

f - Frequency - Hz

G =-5, RF = 549 Ω

G = -1, RF = 576 Ω

RL = 100 Ω,VO = 2 VPP.VS = ±7.5 V

Inve

rtin

g G

ain

- d

B

0

2

4

6

8

10

12

14

16

100 k 1 M 10 M 100 M 1 G

f - Frequency - Hz

Inve

rtin

g G

ain

- d

B

G =-5, RF = 576 Ω

G = 2, RF = 715 Ω

RL = 100 Ω,VO = 2 VPP.VS = ±7.5 V

-2

0

2

4

6

8

10

12

14

16

0 100 200 300 400 500

f - Frequency - MHz

Gai

n -

dB

R(ISO) = 30 Ω, CL = 22 pF

R(ISO) = 20 Ω,CL = 47 pF

Gain = 5RF = 619 ΩRL = 100 ΩVS = ±7.5 V

R(ISO) = 20 Ω,CL = 50 pF

R(ISO) = 15 Ω,CL = 100 pF

0

10

20

30

40

50

60

10 100

CL - Capacitive Load - pF

Rec

om

men

ded

RIS

OΩ

Gain = 5,RF = 619 ΩRL = 100 Ω,VS = ±7.5 V-

_

+

RISO

CL

-100

-90

-80

-70

-60

-50

-40

1 100

f - Frequency - MHz

2n

d O

rde

r H

arm

on

ic D

isto

rtio

n -

dB

c

Vs = 5VV = 2V

R = 100

out PP

L W

±7.

G = 10

R = 499 , R = 54.9F GW W

G = 5

R = 619 ,

R = 154

F

G

W

W

G = 2

R = 768 , R = 768F GW W

10

THS3201


NONINVERTING SMALL-SIGNAL NONINVERTING SMALL-SIGNAL INVERTING SMALL-SIGNALFREQUENCY RESPONSE FREQUENCY RESPONSE FREQUENCY RESPONSE

Figure 1. Figure 2. Figure 3.

INVERTING LARGE-SIGNAL INVERTING LARGE-SIGNAL 0.1 dB GAIN FLATNESSFREQUENCY RESPONSE FREQUENCY RESPONSE FREQUENCY RESPONSE


RECOMMENDED RISO 2nd HARMONIC DISTORTIONCAPACITIVE LOAD vs vs

FREQUENCY RESPONSE CAPACITIVE LOAD FREQUENCY





-100

-95

-90

-85

-80

-75

-70

-65

-60

1 10 100

f - Frequency - MHz

3rd

Ord

er

Ha

rmo

nic

Dis

tort

ion

- d

Bc

Vs = 5VV = 2V

R = 100

out PP

L W

±7.

G = 10

R = 499 , R = 54.9F GW W

G = 2

R = 768 , R = 768F GW W

G = 5

R = 619 , R = 154F GW W

-110

-100

-90

-80

-70

-60

-50

-40

-30

0 1 2 3 4 5 6

V Output Voltage - Vout PP-

2n

d O

rde

r H

arm

on

ic D

isto

rtio

n -

dB

c Vs = 5V

F G

L

G = 2

R = 768 , R = 768

R = 100 W

±7.

W W

1MHz

2MHz8MHz

4MHz

64MHz

32MHz

16MHz

-110

-100

-90

-80

-70

-60

-50

-40

-30

0 1 2 3 4 5 6


3rd

Ord

er

Ha

rmo

nic

Dis

tort

ion

- d

Bc

Vs = 5V

F G

L

G = 2

R = 768 , R = 768

R = 100 W

±7.

W W

1MHz

8MHz 4MHz

64MHz32MHz

16MHz 2MHz

-110

-100

-90

-80

-70

-60

-50

-40

-30

0 1 2 3 4 5 6


2n

d O

rde

r H

arm

on

ic D

isto

rtio

n -

dB

c

Vs = 5V

F G

L

G = 5

R = 619 , R = 154

R = 100 W

±7.

W W

1MHz

2MHz8MHz

4MHz

64MHz

32MHz

16MHz

-110

-100

-90

-80

-70

-60

-50

-40

-30

0 1 2 3 4 5 6


3rd

Ord

er

Ha

rmo

nic

Dis

tort

ion

- d

Bc

Vs = 5V

F G

L

G = 5

R = 649 , R = 154

R = 100 W

±7.

W W

1MHz

8MHz4MHz

64MHz

32MHz

16MHz 2MHz

-110

-100

-90

-80

-70

-60

-50

-40

-30

0 1 2 3 4 5 6


2n

d O

rde

r H

arm

on

ic D

isto

rtio

n -

dB

c

Vs = 5V, G = 10

R = 499 , R = 54.9

R = 100

F G

L W

±7.

W W

1MHz

4MHz

64MHz32MHz

16MHz2MHz

8MHz

-100

-80

-60

-40

-20

1 M 10 M 100 M 10 Gf - Frequency - Hz

0

S-P

aram

eter

- d

B

1 G

S12

S11

S22

Source

C

50 Ω

50 Ω

50 Ω50 Ω

RFRG

VS = ±7.5 VGain = +10C = 0 pF

+-

-110

-100

-90

-80

-70

-60

-50

-40

-30

0 1 2 3 4 5 6


3rd

Ord

er

Ha

rmo

nic

Dis

tort

ion

- d

Bc

Vs = 5V

F G

L

G = 10

R = 499 , R = 54.9

R = 100 W

±7.

W W

1MHz

8MHz4MHz

64MHz

32MHz

16MHz 2MHz

-100

-90

-70

-50

-40

10 30 40 60 70 90 100

f - Frequency - MHz

3rd

Ord

er

Inte

rmo

du

lati

on

Dis

tort

ion

- d

Bc

-80

-60

20 50 80

Vs = 5VV = 2V

R = 100

out PP

L W

±7.

G2

R = 768 , R = 768F GW W

G10

R = 499 , R = 54.9F GW W

G5

R = 619 , R = 154F GW W

THS3201


VS = ±7.5 V Graphs (continued)

2nd HARMONIC DISTORTION 3rd HARMONIC DISTORTION3rd HARMONIC DISTORTION G = 2 G = 2

vs vs vsFREQUENCY OUTPUT VOLTAGE OUTPUT VOLTAGE


2nd HARMONIC DISTORTION 3rd HARMONIC DISTORTION 2nd ORDER HARMONIC DISTORTIONG = 5 G = 5 G = 10

vs vs vsOUTPUT VOLTAGE OUTPUT VOLTAGE OUTPUT VOLTAGE


3rd ORDER HARMONIC DISTORTION 3rd ORDER INTERMODULATIONG = 10 DISTORTION S-PARAMETER

vs vs vsOUTPUT VOLTAGE FREQUENCY FREQUENCY





10

15

20

25

30

40

45

50

100 k 1 M 10 M 100 M

InvertingNoise Current

NoninvertingCurrent Noise

VS = ±7.5 V and ±5 VTA = 25°C

f - Frequency - Hz

35

0

0.5

1.5

2.5

3

4

Vo

ltag

e N

ois

e D

ensi

ty -

n

V/

Hz

Inp

ut

Cu

rren

t N

ois

e D

ensi

ty -

pA

Hz

I n-

Vn

-

Vn

3.5

-100

-80

-60

-40

-20


0

S-P

aram

eter

- d

B

1 G

Source

C

50 Ω

50 Ω

50 Ω50 Ω

RFRG

VS = ±7.5 VGain = +10C = 3.3 pF

S22

S11

S12

+-

6

7

8

9

10

11

12

13

14

0 50 100 150 200 250 300 350 400

No

ise

Fig

ure

- d

B

f - Frequency - MHz

Gain = +10RG = 28 ΩRF = 255 ΩVS = ±7.5 V & ±5 V

0

20

40

60

80

100

120VS = ±5 and ±7.5V

f - Frequency - Hz

100 k 10 M 1 G100 M1 M

Tran

sim

ped

ance

Gai

n -

dB

Ω

_

+

Gain ��VOIIB

10 Ω

_+

0

0.5

1

1.5

2

2.5

3

-40-30-20 -10 0 10 20 30 40 50 60 70 80 90

TC - Case Temperature - °C

- In

pu

t O

ffse

t Vo

ltag

e -

mV

VO

S

VS = ±5 V

VS = ±7.5 V

10

11

12

13

14

15

16

17

-40-30 -20-10 0 10 20 30 40 50 60 70 80 900

1

2

3

4

5

6

7

TC - Case Temperature - °C

- In

pu

t B

ias

Cu

rren

ts -

I IB

I OS

- In

pu

t O

ffse

t C

urr

ents

-

Aµ

Aµ

IOS

IIB-

IIB+

VS = ±7.5 V

-3

-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.52

2.5

3

0 2.5 7.5 12.5

t - Time - ns

- O

utp

ut

Volt

age

- V

V O

Rising Edge

Gain = -2RL = 100 ΩRF = 576 Ωf= 1 MHzVS = ±7.5 V

Falling Edge

5 10-1.5

-1

-0.5

0

0.5

1

1.5

0 2 4 6 8 10

Gain = -2RL = 100 ΩRF = 576 Ωf= 1 MHzVS = ±7.5 V

Rising Edge

Falling Edge

t - Time - ns

- O

utp

ut

Volt

age

- V

V O

0

2000

4000

6000

8000

9000

10000

1 2 4 10

V Output Voltage - Vstepout -

SR

- V

/s

m-

Sle

w R

ate

±

9

SR+

SR-

1000

3000

5000

7000

5 73 6 8

THS3201



INPUT VOLTAGE ANDS-PARAMETER CURRENT NOISE NOISE FIGURE

vs vs vsFREQUENCY FREQUENCY FREQUENCY


TRANSIMPEDANCE INPUT OFFSET VOLTAGE INPUT BIAS AND OFFSET CURRENTvs vs vs

FREQUENCY CASE TEMPERATURE CASE TEMPERATURE


SLEW RATEvs

OUTPUT VOLTAGE SETTLING TIME SETTLING TIME





-7-6

-5-4-3

-2-1

0

12

345

67

10 100 1000

RL - Load Resistance - Ω

- O

utp

ut

Volt

age

- V

V O

VS = ±7.5 VTA = -40 to 85°C

0

10

20

30

40

50

60

70

80

100 k 1 M 10 M 100 M

CMRR

PSRR+

VS = ±7.5 V

Rej

ecti

on

Rat

ios

- d

B

f - Frequency - Hz

0

2

4

6

8

10

12

14

16

18

20

2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5

VS - Supply Voltage - ±V

Qu

iesc

ent

Cu

rren

t -

mA

TA = 85°C

TA = 25°C

TA = -40°C

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8t - Time - µs

- O

utp

ut

Volt

age

- V

V O

Output

Input

Gain = 2RL = 100 ΩRF = 715 ΩVS = ±7.5 V

-6

-5

-4

-3

-2

-1

0

1

2

3

4

5

6

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

t - Time - µs

- O

utp

ut

Volt

age

- V

V O

Output

Input

Gain = -5RL = 100 ΩRF = 549 ΩVS = ±7.5 V

-10

-8

-6

-4

-2

0

2

4

6

8

10

0 0.2 0.4 0.6 0.8 1-5

-4

-3

-2

-1

0

1

2

3

4

5

t - Time - µs

- O

utp

ut

Volt

age

- V

- In

pu

t Vo

ltag

e -

VV

I

V O

G = 2,RF = 768 Ω,VS = ±7.5 V

0

0.005

0.010

0.015

0.020

0.025

0.030

0 1 2 3 4 5 6 7 8

Number of Loads - 150 Ω

Dif

fere

nti

al G

ain

- %

Gain = 2RF = 768 ΩVS = ±7.5 V40 IRE - NTSC and PalWorst Case ±100 IRE Ramp

NTSC

PAL

0

0.005

0.010

0.015

0.020

0.025

0.030

0.035

0.040

0 1 2 3 4 5 6 7 8

Number of Loads - 150 Ω

Dif

fere

nti

al P

has

e -

Gain = 2RF = 768 kΩVS = ±7.5 V40 IRE - NTSC and PalWorst Case ±100 IRE Ramp

NTSC

PAL

°

0.001

0.01

0.1

1

10

100

1000

100 k 1 M 10 M 1 M 1 G

f - Frequency - Hz

Clo

sed

-Lo

op

Ou

tpu

t Im

ped

ance

-Ω Gain = 2

RF = 715 ΩRL = 100 ΩVS = ±7.5 V

THS3201



QUIESCENT CURRENT OUTPUT VOLTAGE REJECTION RATIOvs vs vs

SUPPLY VOLTAGE LOAD RESISTANCE FREQUENCY


NONINVERTING SMALL-SIGNAL INVERTING LARGE-SIGNALTRANSIENT RESPONSE TRANSIENT RESPONSE OVERDRIVE RECOVERY TIME


DIFFERENTIAL GAIN DIFFERENTIAL PHASE CLOSED-LOOP OUTPUT IMPEDANCEvs vs vs

NUMBER OF LOADS NUMBER OF LOADS FREQUENCY





VS = ±5 V Graphs

5.6

5.7

5.8

5.9

6.1

6.2

6.3

6.4

100 k 1 M 10 M 100 M 1 G 10 G

6

f - Frequency - Hz

Gain = 2,RF = 715 Ω,RL = 100 Ω,VO = 0.2 VPP,VS = ±5 V

No

nin

vert

ing

Gai

n -

dB

-4

-202

46

8

10

1214

1618

2022

24

100 k 1 M 10 M 100 M 1 G 10 G

f - Frequency - Hz

RL = 100 Ω,VO = 0.2 VPP.VS = ±5 V

G = 10, RF = 464 Ω

G = 5, RF = 576 Ω

G = 2, RF = 715 Ω

G =1, RF = 1.2 kΩ

No

nin

vert

ing

Gai

n -

dB

-4-2

0

24

68

10

12141618

2022

24

100 k 1 M 10 M 100 M 1 G 10 G

f - Frequency - Hz

RL = 100 Ω,VO = 0.2 VPP.VS = ±5 V

G = -10, RF = 499 Ω

G = -5, RF = 549 Ω

G = -2, RF = 576 Ω

G =-1, RF = 576 ΩIn

vert

ing

Gai

n -

dB

-100

-95

-90

-85

-80

-75

-70

-65

-60

1 10 100

f - Frequency - MHz

3rd

Ord

er

Ha

rmo

nic

Dis

tort

ion

- d

Bc

Vs = 5VV = 2V

R = 100

out PP

L W

±

G = 10

R = 464 , R = 51.1F GW W

G = 2

R = 715 , R = 715F GW W

G = 5

R = 576 , R = 143F GW W

-110

-100

-90

-80

-70

-60

-50

-40

-30

0 1 2 3 4 5 6


2n

d O

rde

r H

arm

on

ic D

isto

rtio

n -

dB

c Vs = 5V

L

G = 2

RF = 715 , RG = 715

R = 100 W

±

W W

1MHz

2MHz

8MHz4MHz

64MHz

32MHz

16MHz

-100

-90

-80

-70

-60

-50

-40

1 100

f - Frequency - MHz

2n

d O

rde

r H

arm

on

ic D

isto

rtio

n -

dB

c

Vs = 5VV = 2V

R = 100

out PP

L W

±

G = 10

R = 464 , R = 51.1F GW W

G = 5

R = 576 ,

R = 143

F

G

W

W

G = 2

R = 715 , R = 715F GW W

10

-110

-100

-90

-80

-70

-60

-50

-40

-30

0 1 2 3 4 5 6


3rd

Ord

er

Ha

rmo

nic

Dis

tort

ion

- d

Bc Vs = 5V

F G

L

G = 2

R = 715 , R = 715

R = 100 W

±

W W

1MHz

2MHz

8MHz

4MHz

64MHz

32MHz

16MHz

-110

-100

-90

-80

-70

-60

-50

-40

-30

0 1 2 3 4 5 6


2n

d O

rde

r H

arm

on

ic D

isto

rtio

n -

dB

c

Vs = 5V

F G

L

G = 5

R = 576 , R = 143

R = 100 W

±

W W

1MHz

2MHz

8MHz 4MHz

64MHz

32MHz

16MHz

-110

-100

-90

-80

-70

-60

-50

-40

-30

0 1 2 3 4 5 6


3rd

Ord

er

Ha

rmo

nic

Dis

tort

ion

- d

Bc Vs = 5V

F G

L

G = 5

R = 576 , R = 143

R = 100 W

±

W W

1MHz

2MHz

8MHz

4MHz

64MHz

32MHz

16MHz

THS3201


NONINVERTING SMALL-SIGNAL INVERTING SMALL-SIGNAL 0.1 dB GAIN FLATNESSFREQUENCY RESPONSE FREQUENCY RESPONSE FREQUENCY RESPONSE


2nd ORDER HARMONIC DISTORTION2nd HARMONIC DISTORTION 3rd ORDER HARMONIC DISTORTION G = 2

vs vs vsFREQUENCY FREQUENCY OUTPUT VOLTAGE


3rd ORDER HARMONIC 2nd ORDER HARMONIC 3rd ORDER HARMONICDISTORTION, G = 2 DISTORTION, G = 5 DISTORTION, G = 5

vs vs vsOUTPUT VOLTAGE OUTPUT VOLTAGE OUTPUT VOLTAGE





-110

-100

-90

-80

-70

-60

-50

-40

-30

0 1 2 3 4 5 6


2n

d O

rde

r H

arm

on

ic D

isto

rtio

n -

dB

c

Vs = 5V, G = 10

R = 464 , R = 51.1

R = 100

F G

L W

±

W W

1MHz

2MHz

8MHz 4MHz

64MHz32MHz

16MHz

-110

-100

-90

-80

-70

-60

-50

-40

-30

0 1 2 3 4 5 6


3rd

Ord

er

Ha

rmo

nic

Dis

tort

ion

- d

Bc Vs = 5V

F G

L

G = 10

R = 464 , R = 51.1

R = 100

W W

W

±

1MHz

2MHz

8MHz

4MHz

64MHz

32MHz

16MHz

-100

-95

-90

-85

-75

-70

-60

-55

-50

10 30 40 60 70 90 100

f - Frequency - MHz

3rd

Ord

er

Inte

rmo

du

lati

on

Dis

tort

ion

- d

Bc

Vs = 5VV = 2V

R = 100

out PP

L W

±

G2

R = 715 , R = 715F GW W

G10

R = 464 ,

R = 51.1

F

G

W

W

G5

R = 576 ,

R = 143

F

G

W

W

-80

-65

20 50 80

-100

-80

-60

-40

-20


0

S-P

aram

eter

- d

B

1 G

S12

S22

S11

VS = ±5 VGain = +10C = 0 pF

Source

C

50 Ω

50 Ω

50 Ω50 Ω

RFRG

+-

-100

-80

-60

-40

-20


0

S-P

aram

eter

- d

B

1 G

S12

VS = ±5 VGain = +10C = 3.3 pF

S22

S11

Source

C

50 Ω

50 Ω

50 Ω50 Ω

RFRG

+-

0

1000

2000

3000

4000

5000

6000

1 2 3 5

V Output Voltage - Vstepout -

SR

- V

/s

m-

Sle

w R

ate

±

4

SR+

SR-

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

t - Time - µs

- O

utp

ut

Volt

age

- V

V O

Output

Input

Gain = 2RL = 100 ΩRF = 715 ΩVS = ±5 V

-3

-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5

3

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

t - Time -µs

- O

utp

ut

Volt

age

- V

V O

Output

Input

Gain = -5RL = 100 ΩRF = 549 ΩVS = ±5 V

-6

-4

-2

0

2

4

6

0 0.2 0.4 0.6 0.8 1-3

-2

-1

0

1

2

3

t - Time - µs

- O

utp

ut

Volt

age

- V

- In

pu

t Vo

ltag

e -

VV

I

V O

G = 2,RF = 715 Ω,VS = ±5 V

THS3201


VS = ±5 V Graphs (continued)

2nd ORDER HARMONIC 3rd ORDER HARMONIC 3rd ORDER INTERMODULATIONDISTORTION, G = 10 DISTORTION, G = 10 DISTORTION

vs vs vsOUTPUT VOLTAGE OUTPUT VOLTAGE FREQUENCY


S-PARAMETER S-PARAMETER SLEW RATEvs vs vs

FREQUENCY FREQUENCY OUTPUT VOLTAGE


NONINVERTING SMALL-SIGNAL INVERTING LARGE-SIGNALTRANSIENT RESPONSE TRANSIENT RESPONSE OVERDRIVE RECOVERY TIME





APPLICATION INFORMATION

WIDEBAND, NONINVERTING OPERATION

WIDEBAND, INVERTING GAIN OPERATION

_

+

THS3201

RF

768 Ω

49.9 Ω

100 pF

0.1 µF 6.8 µF

-VS-7.5 V

RG

50 Ω Source

+

VI

100 pF 0.1 µF 6.8 µF

+

+VS7.5 V

50 Ω

768 Ω

49.9 Ω

_

+

THS3201

RG

287 Ω

100 pF

0.1 µF 6.8 µF

-VS-7.5 V

50 Ω Source

+

VI

100 pF 0.1 µF 6.8 µF

+

+VS7.5 V

RF

576 ΩRM60.4 Ω

50 Ω

49.9 Ω

THS3201


Table 1. Recommended Resistor Values forOptimum Frequency Response

The THS3201 is a unity-gain stable, 1.8-GHzTHS3201 RF for AC When RLOAD = 100 Ωcurrent-feedback operational amplifier, designed to

Gain Supply Voltage RG RFoperate from a ±3.3-V to ±7.5-V power supply.(V/V) (V) (Ω) (Ω)

Figure 55 shows the THS3201 in a noninverting gain ±7.5 — 1.2 k1of 2-V/V configuration typically used to generate the

±5 — 1.2 kperformance curves. Most of the curves were±7.5 768 768characterized using signal sources with 50-Ω source 2±5 715 715impedance, and with measurement equipment

presenting a 50-Ω load impedance. The 49.9-Ω shunt ±7.5 154.9 6195resistor at the VI terminal in Figure 55 matches the ±5 143 576

source impedance of the test generator.±7.5 54.9 487

10±5 51.1 464

±7.5 619 619–1

±5 576 576–2 ±7.5 and ±5 287 576–5 ±7.5 and ±5 110 549–10 ±7.5 and ±5 49.9 499

Figure 56 shows the THS3201 in a typical invertinggain configuration where the input and outputimpedances and signal gain from Figure 55 areretained in an inverting circuit configuration.

Figure 55. Wideband, NoninvertingGain Configuration

Unlike voltage-feedback amplifiers, current-feedbackamplifiers are highly dependent on the feedbackresistor RF for maximum performance and stability.Table 1 shows the optimal gain setting resistors RFand RG at different gains to give maximum bandwidthwith minimal peaking in the frequency response.Higher bandwidths can be achieved, at the expenseof added peaking in the frequency response, by usingeven lower values for RF. Conversely, increasing RFdecreases the bandwidth, but stability is improved.

Figure 56. Wideband, Inverting GainConfiguration




SINGLE-SUPPLY OPERATION

+-

75 Ω75 Ω

75 Ω

75 Ω

75 Ω

n Lines

VO(1)

VO(n)

THS3201

75-Ω Transmission Line

VI

768 Ω 768 Ω

±7.5 V

±7.5 V

ADC DRIVER APPLICATION

_

+

THS320149.9 Ω

50 Ω Source

VI

+VS

RF

768 ΩRG768 Ω

+VS2

+VS2

_

+THS3201287 Ω

50 Ω Source

VI

VS

RF

576 Ω

+VS2

+VS2

60.4 Ω

RG

50 Ω

RT

50 ΩRT

49.9 Ω

49.9 Ω

VIDEO HDTV DRIVERS

THS3201

47pFCM

ADC47pF

1:n 24.9 Ω

VS+

RF

VS-

VIN

RG

0.1 µF

0.1 µF

24.9 Ω

ROUT

0.1 µF

RT

THS3201


The THS3201 has the capability to operate from asingle supply voltage ranging from 6.6 V to 15 V.When operating from a single power supply, caremust be taken to ensure the input signal and amplifierare biased appropriately to allow for the maximumoutput voltage swing. The circuits shown in Figure 57demonstrate methods to configure an amplifier in amanner conducive for single-supply operation.

Figure 58. Video Distribution AmplifierApplication

The THS3201 can be used as a high-performanceADC driver in applications like radio receiver IFstages, and test and measurement devices. Allhigh-performance ADCs have differential inputs. TheTHS3201 can be used in conjunction with atransformer as a drive amplifier in these applications.Figure 59 and Figure 60 show two differentapproaches.

In Figure 59, a transformer is used after the amplifierto convert the signal to differential. The advantage ofthis approach is fewer components are required.ROUT and RT are required for impedance matchingthe transformer.

Figure 57. DC-Coupled Single-Supply Operation

The exceptional bandwidth and slew rate of theTHS3201 matches the demands for professionalvideo and HDTV. Most commercial HDTV standardsrequires a video passband of 30-MHz. To ensurehigh signal quality with minimal degradation ofperformance, a 0.1-dB gain flatness should be atleast 7x the passband frequency to minimize groupdelay variations—requiring 210-MHz 0.1-dBfrequency flatness from the amplifier. High slew ratesensure there is minimal distortion of the video signal.

Figure 59. Differential ADC Driver Circuit 1Component video and RGB video signals require fasttransition times and fast settling times to keep a highsignal quality. The THS8135, for example, is a In Figure 60, a transformer is used before two240-MSPS video digital-to-analog converter (DAC) amplifiers to convert the signal to differential. The twoand has a transition time approaching 4 ns. The amplifiers then amplify the differential signal. TheTHS3201 is a perfect candidate for interfacing the advantage to this approach is each amplifier isoutput of such high-performance video components. required to drive half the voltage as before. RT is

used to impedance match the transformer.



http://focus.ti.com/docs/prod/folders/print/ths3201.htmlhttp://focus.ti.com/docs/prod/folders/print/ths8135.htmlhttp://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SLOS416C&partnum=THS3201http://focus.ti.com/docs/prod/folders/print/ths3201.html

fP�1

2�RC

2� xR

THS3201

THS3201

47pF

CM

ADC47pF

1:n24.9 Ω

0.1 µF

RFRG

VS-

VS+

24.9 Ω

0.1 µF

0.1 µF

VIN

RT

RG

RF

DAC DRIVER APPLICATION

IOUT2

DAC

IOUT1THS3201

THS320147pF

47pF

24.9 Ω

VS+

RFRG

0.1 µF

ROUTVOUT1

VOUT2ROUT

VS-

0.1 µF

RFRG

24.9 Ω

AVDD

AVDD

RPU

RPU

0.1 µF

THS3201


Typically, a low value resistor in the range of 10 Ω to100 Ω provides the required isolation. Together, theR and C form a real pole in the s-plane located at thefrequency:

Placing this pole at about 10x the highest frequencyof interest ensures it has no impact on the signal.Since the resistor is typically a small value, it is verybad practice to place the pole at (or very near)frequencies of interest. At the pole frequency, theamplifiers sees a load with a magnitude of:

If R is only 10 Ω, the amplifier is very heavily loadedabove the pole frequency, and generates excessivedistortion.

Figure 60. Differential ADC Driver Circuit 2The THS3201 can be used as a high-performanceDAC output driver in applications like radio transmitter

It is almost universally recommended to use a stages and arbitrary waveform generators. Allresistor and capacitor between the op amp output high-performance DACs have differential currentand the ADC input as shown in both figures. outputs. Two THS3201s can be used as a differential

drive amplifier in these applications, as shown inThis resistor-capacitor (RC) combination has multipleFigure 61.functions:

• The capacitor is a local charge reservoir for ADC RPU on the DAC output is used to convert the outputcurrent to voltage. The 24.9-Ω resistor and 47-pF• The resistor isolates the amplifier from the ADCcapacitor between each DAC output and the op amp• In conjunction, they form a low-pass noise filterinput is used to reduce the images generated at

During the sampling phase, current is required to multiples of the sampling rate. The values showncharge the ADC input sampling capacitors. By placing form a pole at 136 MHz. ROUT sets the outputexternal capacitors directly at the input pins, most of impedance of each amplifier.the current is drawn from them. They are seen as avery low impedance source. They can be thought ofas serving much the same purpose as apower-supply bypass capacitor to supply transientcurrent, with the amplifier then providing the bulkcharge.

Typically, a low-value capacitor in the range of 10 pFto 100 pF provides the required transient chargereservoir.

The capacitance and the switching action of the ADCis one of the worst loading scenarios that ahigh-speed amplifier encounters. The resistorprovides a simple means of isolating the associatedphase shift from the feedback network andmaintaining the phase margin of the amplifier.

Figure 61. Differential DAC Driver Circuit




PRINTED CIRCUIT BOARD LAYOUT

THS3201


with a low parasitic capacitance shunting theTECHNIQUES FOR OPTIMAL external resistors, excessively high resistor valuesPERFORMANCE can create significant time constants that can

degrade performance. Good axial metal-film orAchieving optimum performance with high frequency surface-mount resistors have approximatelyamplifier-like devices in the THS3201 requires careful 0.2 pF in shunt with the resistor. For resistorattention to board layout parasitic and external values >2.0 kΩ this parasitic capacitance can addcomponent types. a pole and/or a zero that can affect circuitoperation. Keep resistor values as low asRecommendations that optimize performance include:possible, consistent with load driving• Minimize parasitic capacitance to any power orconsiderations.ground plane for the negative input and output

• Connections to other wideband devices on thepins by voiding the area directly below these pinsboard may be made with short direct traces orand connecting traces and the feedback path.through onboard transmission lines. For shortParasitic capacitance on the output and negativeconnections, consider the trace and the input toinput pins can cause instability. To reducethe next device as a lumped capacitive load.unwanted capacitance, a window around theRelatively wide traces (50 mils to 100 mils) shouldsignal I/O pins should be opened in all of thebe used, preferably with ground and power planesground and power planes around those pins andopened up around them. Estimate the totalthe feedback path. Otherwise, ground and powercapacitive load and determine if isolation resistorsplanes should be unbroken elsewhere on theon the outputs are necessary. Low parasiticboard.capacitive loads (< 4 pF) may not need an RS• Minimize the distance (

PowerPAD DESIGN CONSIDERATIONS

0.060

0.040

0.075 0.025

0.205

0.010vias

Pin 1

Top View

0.017

0.035

0.0940.030

0.013

PowerPAD PCB LAYOUT CONSIDERATIONS

DIE

Side View (a)

DIE

End View (b)

ThermalPad

Bottom View (c)

THS3201


• Socketing a high-speed part like the THS3201 isnot recommended. The additional lead length andpin-to-pin capacitance introduced by the socketcan create an extremely troublesome parasiticnetwork which can make it almost impossible toachieve a smooth, stable frequency response.Best results are obtained by soldering theTHS3201 parts directly onto the board.

The THS3201 is available in a thermally-enhancedPowerPAD family of packages. These packages areconstructed using a downset leadframe upon whichthe die is mounted [see Figure 62(a) andFigure 62(b)]. This arrangement results in the leadframe being exposed as a thermal pad on theunderside of the package [see Figure 62(c)]. Because Figure 63. DGN PowerPAD PCB Etch andthis thermal pad has direct thermal contact with the Via Patterndie, excellent thermal performance can be achievedby providing a good thermal path away from thethermal pad.

The PowerPAD package allows for both assembly1. Prepare the PCB with a top side etch pattern asand thermal management in one manufacturing

shown in Figure 63. There should be etch for theoperation. During the surface-mount solder operationleads as well as etch for the thermal pad.(when the leads are being soldered), the thermal pad

can also be soldered to a copper area underneath the 2. Place five holes in the area of the thermal pad.package. Through the use of thermal paths within this These holes should be 10 mils in diameter. Keepcopper area, heat can be conducted away from the them small so that solder wicking through thepackage into either a ground plane or other heat holes is not a problem during reflow.dissipating device. 3. Additional vias may be placed anywhere along

the thermal plane outside of the thermal padThe PowerPAD package represents a breakthrougharea. This helps dissipate the heat generated byin combining the small area and ease of assembly ofthe THS3201 IC. These additional vias may besurface-mount with the, heretofore, awkwardlarger than the 10-mil diameter vias directly undermechanical methods of heatsinking.the thermal pad. They can be larger becausethey are not in the thermal pad area to besoldered so that wicking is not a problem.

4. Connect all holes to the internal ground plane.5. When connecting these holes to the ground

plane, do not use the typical web or spoke viaconnection methodology. Web connections havea high thermal resistance connection that is

Figure 62. Views of Thermally-Enhanced Package useful for slowing the heat transfer duringsoldering operations. This makes the soldering ofvias that have plane connections easier. In thisAlthough there are many ways to properly heatsinkapplication, however, low thermal resistance isthe PowerPAD package, the following steps illustratedesired for the most efficient heat transfer.the recommended approach.Therefore, the holes under the THS3201PowerPAD package should make theirconnection to the internal ground plane with acomplete connection around the entirecircumference of the plated-through hole.

6. The top-side solder mask should leave theterminals of the package and the thermal padarea with its five holes exposed. The bottom-sidesolder mask should cover the five holes of thethermal pad area. This prevents solder from




POWER DISSIPATION AND THERMAL

P =DMax

T TMax

-A

qJA

θJA = 58.4°C/W for 8-Pin MSOP w/PowerPad (DGN)θJA = 98°C/W for 8-Pin SOIC High Test PCB (D)θJA = 158°C/W for 8-Pin MSOP w/PowerPad w/o Solder

Results are With No Air Flow and PCB Size = 3”x3”

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

-40 -20 0 20 40 60 80 100

PD

- M

axim

um

Po

wer

Dis

sip

atio

n -

W

TA - Free-Air Temperature - °C

θJA = 98°C/W

θJA = 158°C/W

TJ = 125°C

θJA = 58.4°C/W

THS3201


being pulled away from the thermal pad area For systems where heat dissipation is more critical,during the reflow process. the THS3201 is offered in an 8-pin MSOP with

PowerPAD and also available in the SOIC-87. Apply solder paste to the exposed thermal padPowerPAD package, offering even better thermalarea and all of the IC terminals.performance. The thermal coefficients for the8. With these preparatory steps in place, the IC is PowerPAD packages are substantially improved oversimply placed in position and run through the the traditional SOIC. Maximum power dissipationsolder reflow operation as any standard levels are depicted in the graph for the availablesurface-mount component. This results in a part packages. The data for the PowerPAD packagesthat is properly installed. assume a board layout that follows the PowerPADlayout guidelines referenced above and detailed inthe PowerPAD application note number SLMA002.CONSIDERATIONS The following graph also illustrates the effect of notsoldering the PowerPAD to a PCB. The thermalTo maintain maximum output capabilities, theimpedance increases substantially which may causeTHS3201 does not incorporate automatic thermalserious heat and performance issues. Be sure toshutoff protection. The designer must take care toalways solder the PowerPAD to the PCB for optimumensure that the design does not violate the absoluteperformance.maximum junction temperature of the device. Failure

may result if the absolute maximum junctiontemperature of +150°C is exceeded. For bestperformance, design for a maximum junctiontemperature of +125°C. Between +125°C and+150°C, damage does not occur, but theperformance of the amplifier begins to degrade.

The thermal characteristics of the device are dictatedby the package and the PCB. Maximum powerdissipation for a given package can be calculatedusing the following formula.

Where:• PDMax is the maximum power dissipation in the

amplifier (W)• TMax is the absolute maximum junction

temperature (°C)Figure 64. Maximum Power Dissipation• TA is the ambient temperature (°C) vs Ambient Temperature• θJA = θJC + θCA

• θJC is the thermal coefficient from the silicon When determining whether or not the device satisfiesjunctions to the case (°C/W)the maximum power dissipation requirement, it is• θCA is the thermal coefficient from the case to the important to not only consider quiescent powerambient air (°C/W)dissipation, but also dynamic power dissipation. Oftentimes, this is difficult to quantify because the signalpattern is inconsistent, but an estimate of the RMSpower dissipation can provide visibility into a possibleproblem.



http://focus.ti.com/docs/prod/folders/print/ths3201.htmlhttp://www-s.ti.com/sc/techlit/SLMA002http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SLOS416C&partnum=THS3201http://focus.ti.com/docs/prod/folders/print/ths3201.html

DESIGN TOOLS

Evaluation Fixture, Spice Models, and

R5

J2Vin+

R6U1

2

36

7

4 1

8

J8*

Vs+

C8*

R4

R7

C7*

J9*

R2

J4Vout

Vs -

R3J1

Vin-

TP1

+C1

VS-

J7

C6 C5 C2

VS+J5

+

FB2

C4 C3

FB1VS-

GND

VS+

J6

_

+

*Does Not Apply to the THS3201

PD

768 Ω

768 Ω49.9 Ω0 Ω

PD Ref

49.9 Ω

Not Populated

0.1 µF22 µF 100 pF 100 pF 0.1 µF 22 µF

THS3201


Applications SupportTexas Instruments is committed to providing itscustomers with the highest quality of applicationssupport. To support this goal an evaluation board hasbeen developed for the THS3201 operationalamplifier. The board is easy to use, allowing forstraightforward evaluation of the device. Theevaluation board can be ordered through the TexasInstruments web site at www.ti.com, or through yourlocal Texas Instruments sales representative. Theschematic diagram, board layers, and bill of materialsof the evaluation boards are provided below.

Figure 65. THS3201 EVM Circuit Configuration



http://focus.ti.com/docs/prod/folders/print/ths3201.htmlhttp://www.ti.com/http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SLOS416C&partnum=THS3201http://focus.ti.com/docs/prod/folders/print/ths3201.html

THS3201


Figure 66. THS3201 EVM Board Layout Figure 68. THS3201 EVM Board Layout(Top Layer) (Third Layer, Power)

Figure 67. THS3201 EVM Board Layout Figure 69. THS3201 EVM Board Layout(Second Layer, Ground) (Bottom Layer)




ADDITIONAL REFERENCE MATERIAL

THS3201


Table 2. Bill of Materials (1)

THS3201DGN EVMPCB MANUFACTURER'SITEM DESCRIPTION SMD SIZE REF DES QUANTITY PART NUMBER

1 Bead, ferrite, 3 A, 80 Ω 1206 FB1, FB2 2 (Steward) HI1206N800R-002 Cap, 22 µF, tanatalum, 25 V, 10% D C1, C2 2 (AVX) TAJD226K025R3 Cap, 100 pF, ceramic, 5%, 150 V AQ12 C4, C5 2 (AVX) AQ12EM101JAJME4 Cap, 0.1 µF, ceramic, X7R, 50 V 0805 C3, C6 2 (AVX) 08055C104KAT2A6 Open 0805 R7 17 Resistor, 49.9 Ω, 1/8 W, 1% 0805 R6 1 (Phycomp) 9C08052A49R9FKHFT9 Resistor, 768 Ω, 1/8 W, 1% 0805 R3, R5 2 (Phycomp) 9C08052A7680FKHFT

10 Open 1206 C7, C8 211 Resistor, 0 Ω, 1/4 W, 1% 1206 R2 1 (KOA) RK73Z2BLTD12 Resistor, 49.9 Ω, 1/4 W, 1% 1206 R4 1 (Phycomp) 9C12063A49R9FKRFT13 Test point, black TP1 1 (Keystone) 500114 Open J8, J9 215 Jack, Banana Receptance, 0.25” dia. hole J5, J6, J7 3 (HH Smith) 10116 Connector, edge, SMA PCB jack J1, J2, J4 3 (Johnson) 142-0701-80117 Standoff, 4-40 hex, 0.625” length 4 (Keystone) 180418 Screw, Phillips, 4-40, .250” 4 SHR-0440-016-SN19 IC, THS3201 U1 1 (TI) THS3201DGN20 Board, printed circuit 1 (TI) Edge # 6447972 Rev.A

(1) The components shown in the BOM were used in test by TI.

blank space

Computer simulation of circuit performance usingSPICE is often useful when analyzing the • PowerPAD Made Easy, application briefperformance of analog circuits and systems. This is (SLMA004)particularly true for video and RF-amplifier circuits • PowerPAD Thermally Enhanced Package,where parasitic capacitance and inductance can have technical brief (SLMA002)a major effect on circuit performance. A SPICE model

• Voltage Feedback vs Current-Feedback Amplifiersfor the THS3201 family of devices is available(SLVA051)through the Texas Instruments web site (www.ti.com).

• Current-Feedback Analysis and CompensationThe Product Information Center (PIC) is available for(SLOA021)design assistance and detailed product information.

These models do a good job of predicting • Current-Feedback Amplifiers: Review, Stability,small-signal ac and transient performance under a and Application (SBOA081)wide variety of operating conditions. They are not • Effect of Parasitic Capacitance in Op Amp Circuitsintended to model the distortion characteristics of the (SLOA013)amplifier, nor do they attempt to distinguish betweenthe package types in their small-signal acperformance. Detailed information about what is andis not modeled is contained in the model file itself.



http://focus.ti.com/docs/prod/folders/print/ths3201.htmlhttp://www-s.ti.com/sc/techlit/SLMA004http://www-s.ti.com/sc/techlit/SLMA002http://www-s.ti.com/sc/techlit/SLVA051http://www.ti.com/http://www-s.ti.com/sc/techlit/SLOA021http://www-s.ti.com/sc/techlit/SBOA081http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SLOS416C&partnum=THS3201http://focus.ti.com/docs/prod/folders/print/ths3201.html

THS3201


EVM WARNINGS AND RESTRICTIONSIt is important to operate this EVM within the input voltage and the output voltage ranges as specified in the table below.

Input Range, VS 6.6 V (±3.3V) to 16.5V (±8.25V)Input Range, VI NOT TO EXCEED: Power-Supply Voltage AppliedOutput Range, VO NOT TO EXCEED: Power-Supply Voltage Applied

Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questionsconcerning the input range, please contact a TI field representative prior to connecting the input power.Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,please contact a TI field representative.During normal operation, some circuit components may have case temperatures greater than +125°C. The EVM is designed to operateproperly with certain components above +125°C as long as the input and output ranges are maintained. These components include but arenot limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identifiedusing the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation,please be aware that these devices may be very warm to the touch.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright 2008, Texas Instruments Incorporated




THS3201


Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (March 2008) to Revision C .................................................................................................. Page

• Changed 5-V Step to 10-V Step in second bullet of Features list ......................................................................................... 1• Deleted lead temperature row from Absolute Maximum Ratings table ................................................................................. 2

Changes from Revision A (January, 2004) to Revision B .............................................................................................. Page

• Updated document format ..................................................................................................................................................... 1• Updated Features, Applications, and Description sections ................................................................................................... 1• Updated Package/Ordering Information ................................................................................................................................ 3• Changed ±7.5-V slew rate typical values............................................................................................................................... 4• Changed ±7.5-V rise and fall time typical values................................................................................................................... 4• Changed ±7.5-V 2nd-order harmonic typical values.............................................................................................................. 4• Changed ±7.5-V 3rd-order harmonic typical values .............................................................................................................. 4• Deleted ±7.5-V 3rd-order intermodulation distortion specifications ....................................................................................... 4• Changed ±5-V slew rate typical values.................................................................................................................................. 6• Changed ±5-V rise and fall time typical values...................................................................................................................... 6• Changed ±5-V 2nd-order harmonic typical values................................................................................................................. 6• Changed ±5-V 3rd-order harmonic typical values ................................................................................................................. 6• Deleted ±5-V 3rd-order intermodulation distortion specifications .......................................................................................... 6• Added Figure 9 through Figure 17; updated Figure 25 ......................................................................................................... 8• Added Figure 40 through Figure 48; added Figure 51 .......................................................................................................... 9• Deleted Power Supply section............................................................................................................................................. 19• Updated first paragraph in Printed Circuit Board Layout section......................................................................................... 19




PACKAGING INFORMATION

Orderable Device Status (1) PackageType

PackageDrawing

Pins PackageQty

Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

THS3201D ACTIVE SOIC D 8 75 Green (RoHS &no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

THS3201DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &no Sb/Br)


THS3201DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &no Sb/Br)


THS3201DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &no Sb/Br)


THS3201DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &no Sb/Br)


THS3201DG4 ACTIVE SOIC D 8 75 Green (RoHS &no Sb/Br)


THS3201DGK ACTIVE MSOP DGK 8 80 Green (RoHS &no Sb/Br)


THS3201DGKG4 ACTIVE MSOP DGK 8 80 Green (RoHS &no Sb/Br)


THS3201DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS &no Sb/Br)


THS3201DGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS &no Sb/Br)


THS3201DGN ACTIVE MSOP-Power PAD

DGN 8 80 Green (RoHS &no Sb/Br)


THS3201DGNG4 ACTIVE MSOP-Power PAD



THS3201DGNR ACTIVE MSOP-Power PAD



THS3201DGNRG4 ACTIVE MSOP-Power PAD



THS3201DR ACTIVE SOIC D 8 2500 Green (RoHS &no Sb/Br)


THS3201DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &no Sb/Br)


(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part ina new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please checkhttp://www.ti.com/productcontent for the latest availability information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirementsfor all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be solderedat high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die andpackage, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

PACKAGE OPTION ADDENDUM

www.ti.com 29-May-2009

Addendum-Page 1

http://www.ti.com/productcontent

compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flameretardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak soldertemperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it isprovided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to theaccuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to takereasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis onincoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limitedinformation may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TIto Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF THS3201 :

• Enhanced Product: THS3201-EP

NOTE: Qualified Version Definitions:

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

PACKAGE OPTION ADDENDUM

www.ti.com 29-May-2009

Addendum-Page 2

http://focus.ti.com/docs/prod/folders/print/ths3201-ep.html

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

THS3201DBVR SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3

THS3201DBVT SOT-23 DBV 5 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3

THS3201DGKR MSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

THS3201DGNR MSOP-Power PAD

DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

THS3201DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 19-Aug-2011

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

THS3201DBVR SOT-23 DBV 5 3000 182.0 182.0 20.0

THS3201DBVT SOT-23 DBV 5 250 182.0 182.0 20.0

THS3201DGKR MSOP DGK 8 2500 358.0 335.0 35.0

THS3201DGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0

THS3201DR SOIC D 8 2500 346.0 346.0 29.0

PACKAGE MATERIALS INFORMATION

www.ti.com 19-Aug-2011

Pack Materials-Page 2

http://www.ti.com/lit/slma002http://www.ti.com/lit/slma004

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the latest relevant information before placing orders and should verify that such information is current and complete. All products aresold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standardwarranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except wheremandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products andapplications using TI components. To minimize the risks associated with customer products and applications, customers should provideadequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Informationpublished by TI regarding third-party products or services does not constitute a license from TI to use such products or services or awarranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectualproperty of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompaniedby all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptivebusiness practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additionalrestrictions.

Resale of TI products or services with statements different from or beyond the par

1.8-GHz, LOW DISTORTION, CURRENT-FEEDBACK AMPLIFIER · 1.8-GHz, LOW DISTORTION, CURRENT-FEEDBACK AMPLIFIER 23 ... OPA695 ±5-V, 1.7-GHz Low Distortion CFB Amplifier 1 Please be aware

Text of 1.8-GHz, LOW DISTORTION, CURRENT-FEEDBACK AMPLIFIER · 1.8-GHz, LOW DISTORTION, CURRENT-FEEDBACK...

Class A Headphone amplifier - AKG...Audiophile Class-A headphone amplifier Delivers exceptionally low noise and harmonic distortion, zero crossover distortion, a wide frequency response,

GaAs, pHEMT, MMIC,1 W Power Amplifier, 20 GHz to 44 GHz ... · GaAs, pHEMT, MMIC,1 W Power Amplifier, 20 GHz to 44 GHz Data Sheet ADPA7005CHIP Rev. 0 Document Feedback Information

Common Source Amplifier MOSFET Amplifier Distortionmshashmi/CMOS_2015/Lecture_Slides... · •Common Source Amplifier •MOSFET Amplifier Distortion . ECE315 / ECE515 ... g 0 RR G

5.1-5.9 GHz 802.11ac WLAN Power Amplifier

1 GHz GainMaker Broadband Amplifier Platform System Amplifier

Class A Headphone amplifier - Harman Kardon...Audiophile Class-A headphone amplifier Delivers exceptionally low noise and harmonic distortion, zero crossover distortion, a wide frequency

Low Noise Amplifier, 0.01 GHz to 10 GHz Data Sheet ... · Low Noise Amplifier, 0.01 GHz to 10 GHz Data Sheet HMC8411LP2FE Rev. A Document Feedback Information furnished by Analog

1.8-GHz, LOW DISTORTION, CURRENT-FEEDBACK AMPLIFIER · 1.8-GHz, LOW DISTORTION, CURRENT-FEEDBACK AMPLIFIER 23 •Unity-Gain Bandwidth: 1.8 GHz The THS3201 is a wideband, high-speed

Surface Mount Monolithic Amplifier DC-4 GHz

1.9 GHz Low Noise Amplifier

Modeling Amplifier Operating Manual · alistic tube sounding distortion in any modeling amplifier. By using analog distortion, the VYPYR Pro’s digital processor has the amazing

2 GHz to 28 GHz, GaAs pHEMT MMIC Low Noise Amplifier Data ... · 2 GHz to 28 GHz, GaAs pHEMT MMIC Low Noise Amplifier Data Sheet HMC7950 Rev. A Document Feedback Information furnished

GaAs pHEMT MMIC Low Noise Amplifier, 0.3 GHz to 20 GHz ......GaAs pHEMT MMIC Low Noise Amplifier, 0.3 GHz to 20 GHz Data Sheet HMC1049 FEATURES Low noise figure: 1.8 dB P1dB output

A 23-GHz BANDWIDTH AUTOMATIC GAIN CONTROL AMPLIFIER

2 GHz, Ultralow Distortion, Differential RF/IF …...2 GHz, Ultralow Distortion, Differential RF/IF Amplifier Data Sheet AD8352 Rev. C Document Feedback Information furnished by Analog

1 Watt, GaAs pHEMT MMIC Power Amplifier, 27 GHz to 32 GHz

Common Source Amplifier MOSFET Amplifier Distortionmshashmi/CMOS_2016/Lecture_Slides... · •Common Source Amplifier •MOSFET Amplifier Distortion . ... Bypass Capacitor →

10 Watt RF Power Amplifier for 2.4 GHz

0.01 GHz to 10 GHz, GaAs, pHEMT, MMIC, Low Noise Amplifier

1 GHz GainMaker Broadband Amplifier Platform Line Extender

FET-Input, Low Distortion Operational Amplifier datasheet

Modeling of Power Amplifier Distortion in MIMO Transmitters

46 dBm (40 W), 0.9 GHz to 1.6 GHz, GaN Power Amplifier

AS0102-500 1 GHz TO 2 GHz 500 WATT BROADBAND POWER AMPLIFIER … · 1 GHz TO 2 GHz 500 WATT BROADBAND POWER AMPLIFIER AS0102-500 Key RF Parameters Frequency range (instantaneous)

SMART 1.2 GHZ AMPLIFIER - Teleste Intercept

a Low Distortion Amplifier 1 GHz, 5,500 V/ AD8009pdf.dzsc.com/9AR/AD8009AR-REEL.pdf · The AD8009 is an ultrahigh speed current feedback amplifier with a phenomenal 5,500 V/ s slew

The 88-50—a Low-Distortion 50-Watt Amplifier

Brochure: CX3 1.2 GHz Universal amplifier - Teleste

2.4-2.5 GHz / 4.9-5.8 GHz Dual-Band Power Amplifier …ww1.microchip.com/downloads/en/DeviceDoc/S71318.pdfData Sheet 2.4-2.5 GHz / 4.9-5.8 GHz Dual-Band Power Amplifier SST13LP05 3

2.3 GHz to 4.0 GHz ¼ Watt RF Driver Amplifier Data Sheet

Documents

1.8-GHz, LOW DISTORTION, CURRENT-FEEDBACK AMPLIFIER · 1.8-GHz, LOW DISTORTION, CURRENT-FEEDBACK AMPLIFIER 23 ... OPA695 ±5-V, 1.7-GHz Low Distortion CFB Amplifier 1 Please be aware

Text of 1.8-GHz, LOW DISTORTION, CURRENT-FEEDBACK AMPLIFIER · 1.8-GHz, LOW DISTORTION, CURRENT-FEEDBACK...