160-W Stereo / 300-W Mono PurePath(TM) HD Digital-Input Power

PurePathTM

HDPower SupplyRef. Design

110 VAC 240 VAC®

TAS5630

25 V–50 V

ANALOG

AUDIO

INPUT

12 V

PurePathTM

HDTAS5616

(2.1 Configuration)

TAS3308Digital Audio

ProcessorWith Analog InterfaceDIGITAL

AUDIO

INPUT

+3.3V

REG.

TAS5616www.ti.com SLAS596B –JUNE 2009–REVISED JANUARY 2010

160-W STEREO / 300-W MONO PurePath™ HD DIGITAL-INPUT POWER STAGECheck for Samples: TAS5616

1FEATURES APPLICATIONS• Mini Combo System

23• PurePath™ HD Enabled Integrated FeedbackProvides: • AV Receivers

• DVD Receivers– Signal Bandwidth up to 80 kHz forHigh-Frequency Content From HD Sources • Active Speakers

– Ultralow 0.03% THD at 1 W into 8 ΩDESCRIPTION– Flat THD at All Frequencies for Natural

Sound The TAS5616 is a high-performance PWM-inputclass-D amplifier with integrated closed-loop– 80-dB PSRR (BTL, No Input Signal)feedback technology (known as PurePath™ HD– >100-dB (A-weighted) SNR technology). It has the ability to drive up to 160-W

– Click- and Pop-Free Startup (1) stereo into 8-Ω speakers from a single 50-Vsupply.– Minimal External Components Compared to

Discrete Solutions PurePath™ HD technology enables traditional• Multiple Configurations Possible on the Same AB-amplifier performance (<0.03% THD) levels while

providing the power efficiency of traditional class-DPCB With Stuffing Options:amplifiers.– Mono Parallel Bridge-Tied Load (PBTL)Ultralow 0.03% THD+N is flat across all frequencies,– Stereo Bridge-Tied Load (BTL)ensuring that the amplifier does not add uneven– 2.1 Single-Ended Stereo Pair anddistortion characteristics, and helps maintain a natural

Bridge-Tied Load Subwoofer sound.– Quad Single-Ended Outputs

The efficiency of this class-D amplifier is greater than• Total Output Power at 10% THD+N 90%. Undervoltage protection, overtemperature,

– 330 W in Mono PBTL Configuration clipping, short-circuit and overcurrent protection areall integrated, safeguarding the device and speakers– 160 W per Channel in Stereo BTLagainst fault conditions that could damage theConfigurationsystem. PurePath HD™

– 80 W per Channel in Quad Single-EndedConfiguration

• High-Efficiency Power Stage (>90%) With120-mΩ Output MOSFETs

• Two Thermally Enhanced Package Options:– PHD (64-Pin QFP)– DKD (44-Pin PSOP3)

• Self-Protection Design (IncludingUndervoltage, Overtemperature, Clipping, andShort-Circuit Protection) With Error Reporting

• EMI Compliant When Used WithRecommended System Design

(1) Achievable output power levels are dependent on the thermalconfiguration of the target application. A high performancethermal interface material between the package exposedthermal pad and the heat sink should be used to achieve highoutput power levels.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PurePath HD is a trademark of Texas Instruments.3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright © 2009–2010, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

http://focus.ti.com/docs/prod/folders/print/tas5616.html

https://commerce.ti.com/stores/servlet/SCSAMPLogon?storeId=10001&langId=-1&catalogId=10001&reLogonURL=SCSAMPLogon&URL=SCSAMPSBDResultDisplay&GPN1=tas5616

PIN ONE LOCATION PHD PACKAGE

2616

15

OC_ADJ

14

RESET

13

C_STARTUP

12

INPUT_A

11

INPUT_B

10

VI_CM

9

GND8AGND7

VREG

6

INPUT_C

5

INPUT_D

4

TEST

3

NC

2

NC

1

SD 64-pins QFP package

32

GN

D_D

31

PV

DD

_D

30

PV

DD

_D

29

OU

T_D

28

OU

T_D

27

BS

T_D

GV

DD

_D

25

GV

DD

_C

24

GN

D23

GN

D22

NC

21

NC

20

NC

19

NC

18

PS

U_R

EF

17

VD

D

33 GND_D34 GND_C35 GND_C36 OUT_C37 OUT_C38 PVDD_C39 PVDD_C40 BST_C41 BST_B42 PVDD_B43

OUT_B44

GND_B45

GND_A

464748

55

49

50

51

RE

AD

Y

52

M1

53

M2

54

M3

GN

D

56

GN

D57

GV

DD

_B

58

GV

DD

_A

59

BS

T_A

60

OU

T_A

61

OU

T_A

62

PV

DD

_A

63

PV

DD

_A

64

GN

D_A

OTW1

CLIP

PVDD_B

OUT_B

GND_B

DKD PACKAGE(TOP VIEW)

44

pins

PA

CK

AG

E(T

OP

VIE

W)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23M3

OC_ADJ

VDD

PSU_REF

M2

M1

READY

OTW

SD

NC

NC

TEST

INPUT_D

INPUT_C

VREG

AGND

GND

VI_CM

INPUT_B

INPUT_A

C_STARTUP

RESET

GND_C

OUT_A

BST_A

OUT_B

BST_B

PVDD_B

PVDD_A

BST_C

PVDD_C

OUT_C

GND_A

GND_B

OUT_D

PVDD_D

BST_D

GND_D

GVDD_AB

GVDD_CD

PVDD_A

PVDD_D

OUT_D

OUT_A

OT

W2

PHD PACKAGE(TOP VIEW)

Electrical Pin 1

Pin 1 MarkerWhite Dot

TAS5616SLAS596B –JUNE 2009–REVISED JANUARY 2010 www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

DEVICE INFORMATION

Terminal Assignment

The TAS5616 is available in two thermally enhanced packages:• 44-Pin PSOP3 package (DKD)• 64-Pin QFP (PHD) Power Package

Both package types contain a heat slug that is located on the top side of the device for convenient thermalcoupling to the heat sink.

2 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated

Product Folder Link(s) :TAS5616


http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SLAS596BB&partnum=TAS5616



MODE SELECTION PINS

MODE PINS ANALOG OUTPUTDESCRIPTION

INPUT (1) CONFIGURATIONM3 M2 M1

0 0 0 2N 2 × BTL AD mode

0 0 1 — — Reserved

0 1 0 2N 2 × BTL BD mode

0 1 1 1N 1 × BTL +2 × SE AD mode

1 0 0 1N 4 × SE AD mode

INPUT_C (2) INPUT_D (2)

1 0 1 2N 1 × PBTL 0 0 AD mode

1 0 BD mode

1 1 0Reserved

1 1 1

(1) The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode.(2) INPUT_C and D are used to select between a subset of AD and BD mode operations in PBTL mode (1=VREG and 0=AGND)..

PACKAGE HEAT DISSIPATION RATINGS (1)

PARAMETER TAS5616PHD TAS5616DKD

RqJC (°C/W) – 2 BTL or 4 SE channels 3.63 2.52

RqJC (°C/W) – 1 BTL or 2 SE channel(s) 5.95 3.22

RqJC (°C/W) – 1 SE channel 9.9 6.9

Pad Area (2) 49 mm2 80 mm2

(1) JC is junction-to-case, CH is case-to-heat sink(2) RqCH is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heat sink and

both channels active. The RqCH with this condition is 1.22°C/W for the PHD package and 1.02°C/W for the DKD package

Table 1. ORDERING INFORMATION (1)

TA PACKAGE DESCRIPTION

0°C–70°C TAS5616PHD 64 pin HTQFP

0°C–70°C TAS5616DKD 44 pin PSOP3

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com.

Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 3



http://www.ti.com




ABSOLUTE MAXIMUM RATINGSover operating free-air temperature range unless otherwise noted (1)

TAS5616 UNIT

VDD to AGND –0.3 to 13.2 V

GVDD to AGND –0.3 to 13.2 V

PVDD_X to GND_X (2) –0.3 to 69.0 V

OUT_X to GND_X (2) –0.3 to 69.0 V

BST_X to GND_X (2) –0.3 to 82.2 V

BST_X to GVDD_X (2) –0.3 to 69.0 V

VREG to AGND –0.3 to 4.2 V

GND_X to GND –0.3 to 0.3 V

GND_X to AGND –0.3 to 0.3 V

GND to AGND –0.3 to 0.3 V

OC_ADJ, M1, M2, M3, VI_CM, C_STARTUP, PSU_REF to AGND –0.3 to 4.2 V

INPUT_X –0.3 to 5.0 V

RESET, SD, OTW1, OTW2, CLIP, READY to AGND –0.3 to 7.0 V

Maximum continuous sink current (SD, OTW1, OTW2, CLIP, READY) 9 mA

Maximum operating junction temperature range, TJ 0 to 150 °C

Storage temperature, Tstg –40 to 150 °C

Human-Body Model (3) (all pins) ±2 kVElectrostatic discharge

Charged-Device Model (3) (all pins) ±500 V

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under Recommended OperatingConditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.(3) Failure to follow good anti-static ESD handling during manufacture and rework will contribute to device malfunction. Please ensure

operators handling the device are adequately grounded through the use of ground straps or alternative ESD protection.

RECOMMENDED OPERATING CONDITIONSMIN NOM MAX UNIT

Half-bridge supply 25 50 52.5PVDD_x DC supply voltage V

Half-bridge supply, BTL 4Ω load 25 38 40

Supply for logic regulators and gate-driveGVDD_x DC supply voltage 10.8 12 13.2 Vcircuitry

VDD Digital regulator supply voltage DC supply voltage 10.8 12 13.2 V

RL(BTL) 7 8Output filter according toRL(SE) Load impedance schematics in the application 3.5 4 Ω

information section.RL(PBTL) 3.5 4

LOUTPUT(BTL) 14 15Minimum output inductance underLOUTPUT(SE) Output filter inductance 14 15 mHshort-circuit condition

LOUTPUT(PBTL) 14 15

FPWM PWM frame rate 352 384 500 kHz

TJ Junction temperature 0 150 °C







TERMINAL FUNCTIONSTERMINAL

FUNCTION (1) DESCRIPTIONPHD DKDNAME NO.NO.

AGND 8 10 P Analog ground

BST_A 54 43 P HS bootstrap supply (BST), external 0.033 mF capacitor to OUT_A required.

BST_B 41 34 P HS bootstrap supply (BST), external 0.033 mF capacitor to OUT_B required.

BST_C 40 33 P HS bootstrap supply (BST), external 0.033 mF capacitor to OUT_C required.

BST_D 27 24 P HS bootstrap supply (BST), external 0.033 mF capacitor to OUT_D required.

C_STARTUP 3 5 O Startup ramp requires a charging capacitor of 4.7 nF to AGND

CLIP 18 — O Clipping warning; open drain; active low

7, 23,GND 24, 57, 9 P Ground

58

GND_A 48, 49 38 P Power ground for half-bridge A

GND_B 46, 47 37 P Power ground for half-bridge B

GND_C 34, 35 30 P Power ground for half-bridge C

GND_D 32, 33 29 P Power ground for half-bridge D

GVDD_A 55 — P Gate drive voltage supply requires 0.1 mF capacitor to AGND

GVDD_AB — 44 P Gate drive voltage supply requires 0.22 mF capacitor to AGND

GVDD_B 56 — P Gate drive voltage supply requires 0.1 mF capacitor to AGND

GVDD_C 25 — P Gate drive voltage supply requires 0.1 mF capacitor to AGND

GVDD_CD — 23 P Gate drive voltage supply requires 0.22 mF capacitor to AGND

GVDD_D 26 — P Gate drive voltage supply requires 0.1 mF capacitor to AGND

INPUT_A 4 6 I Input signal for half bridge A

INPUT_B 5 7 I Input signal for half bridge B

INPUT_C 10 12 I Input signal for half bridge C

INPUT_D 11 13 I Input signal for half bridge D

M1 20 20 I Mode selection



NC 59-62 — — No connect, pins may be grounded.

NC 13 15 — No connect, pins may be grounded.

NC 14 16 — No connect, pins may be grounded.

OC_ADJ 1 3 O Analog over current programming pin requires resistor to ground.64 pin QFP package (PHD) = 22 kΩ44 pin PSOP3 Package (DKD) = 24 kΩ

OTW — 18 O Overtemperature warning signal, open drain, active low.

OTW1 16 — O Overtemperature warning signal, open drain, active low.

OTW2 17 — O Overtemperature warning signal, open drain, active low.

OUT_A 52, 53 39, 40 O Output, half bridge A

OUT_B 44, 45 36 O Output, half bridge B

OUT_C 36, 37 31 O Output, half bridge C

OUT_D 28, 29 27, 28 O Output, half bridge D

PSU_REF 63 1 P PSU Reference requires close decoupling of 4.7 mF to AGND

PVDD_A 50, 51 41, 42 P Power supply input for half bridges A requires close decoupling of 2.2-mF capacitor to GND_A

PVDD_B 42, 43 35 P Power supply input for half bridges B requires close decoupling of 2.2-mF capacitor to GND_B

PVDD_C 38, 39 32 P Power supply input for half bridges C requires close decoupling of 2.2-mF capacitor to GND_C

PVDD_D 30, 31 25, 26 P Power supply input for half bridges D requires close decoupling of 2.2-mF capacitor to GND_D

READY 19 19 O Normal operation; open drain; active high

RESET 2 4 I Device reset Input; active low

SD 15 17 O Shutdown signal, open drain, active low

TEST 12 14 I Connect to VREG node

(1) I = Input, O = Output, P = Power






2-CHANNEL

H-BRIDGE

BTL MODE

Output

H-Bridge 2

PV

DD

_A

,B

,C

,D

GN

D_

A,

B,

C,

D

Hardwire

Over-

Current

Limit

8

GN

D

VD

D

VR

EG

AG

ND

OC

_A

DJ

PVDDPower Supply

Decoupling

GVDD, VDD,

& VREGPower Supply

Decoupling

SYSTEM

Power

Supplies

PVDD

GVDD (12V)/VDD (12V)

GND

50V

12V

GND

VAC

Bootstrap

Caps

BST_C

BST_D

2nd

Order

L-C Output

Filter for

each

H-Bridge

OUT_C

OUT_D

GV

DD

_A

,B

,C

,D

Bootstrap

Caps

BST_A

BST_B

INPUT_A 2nd

Order

L-C Output

Filter for

each

H-Bridge

OUT_A

OUT_B

8 4

Output

H-Bridge 1

Input

H-Bridge 1INPUT_B

M2

M1

M3

Hardwire

Mode

Control

Input

H-Bridge 2

INPUT_C

INPUT_D

VI_

CM

C_

ST

AR

TU

P

PS

U_

RE

F

Caps for

External

Filtering

&

Startup/Stop

/OT

W1

,/O

TW

2,

/OT

W

/CL

IP

System

microcontroller

RE

AD

Y

/SD

PWM_A

PWM_B

PWM_C

PWM_D

2

2

2

2

(2)

TAS5518/

TAS5508/

TAS5086

I2C

Left-

Channel

Output

Right-

Channel

Output

VALID/RESET

TE

ST

/AMP RESET

*NOTE1

*NOTE1: Logic AND in or outside microcontroller


TERMINAL FUNCTIONS (continued)TERMINAL

FUNCTION (1) DESCRIPTIONPHD DKDNAME NO.NO.

Power supply for digital voltage regulator requires a 10-mF capacitor in parallel with a 0.1-mFVDD 64 2 P capacitor to GND for decoupling.

VI_CM 6 8 O Analog comparator reference input requires close decoupling of 4.7 mF to AGND

VREG 9 11 P Digital regulator supply filter pin requires 0.1-mF capacitor to AGND

TYPICAL SYSTEM BLOCK DIAGRAM






M1

M2

/RESET

/SD

/OTW2

AGND

OC_ADJ

VREG

VDD

GVDD_A

M3

GND

INPUT_D

OUT_A

GND_A

PVDD_A

BST_A

GVDD_A

PWM

ACTIVITY

DETECTOR

GVDD_C

GVDD_B

INPUT_C

OUT_B

GND_B

PVDD_B

BST_B

GVDD_B GVDD_D

GVDD_C

OUT_C

GND_C

PVDD_C

BST_C

GVDD_D

OUT_D

GND_D

PVDD_D

BST_D

INPUT_B

INPUT_A

PVDD_X

OUT_X

GND_X

TIMING

CONTROLCONTROL GATE-DRIVE

TIMING


TIMING


TIMING


PWM

RECEIVER

PWM

RECEIVER

PWM

RECEIVER

PWM

RECEIVER

+

-

AN

AL

OG

CO

MP

AR

AT

OR

MU

X

+

-

+

-

+

-

PR

OT

EC

TIO

N&

I/O

LO

GIC

VI_CM

STARTUP

CONTROL

POWER-UP

RESET

TEMP

SENSE

OVER-LOAD

PROTECTION

PPSC

CB3C

UVP

CURRENT

SENSE

VREG

C_STARTUP

ANALOG

LOOP FILTER

ANALOG

LOOP FILTER

ANALOG

LOOP FILTER

ANALOG

LOOP FILTER

AN

AL

OG

INP

UT

MU

X

AGC

PSU_REF

4

4

4

PVDD_X4

GND

/OTW1

READY

/CLIP


FUNCTIONAL BLOCK DIAGRAM







AUDIO CHARACTERISTICS (BTL)Audio performance is recorded as a chipset consisting of a TAS5518 PWM Processor (modulation index limited to 97.7%)and a TAS5616 power stage. PCB and system configuration are in accordance with recommended guidelines. Audiofrequency = 1kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 4Ω, fS = 384 kHz, ROC = 24 kΩ, TC = 75°C, Output Filter: LDEM =15 mH, CDEM = 680 nF, MODE = 000, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

RL = 8 Ω, 10% THD+N 160PO Power output per channel W

RL = 8 Ω, 1% THD+N 125

Total harmonic distortion +THD+N 1 W 0.03%noise

Vn Output integrated noise A-weighted, TAS5518 Modulator 185 mV

|VOS| Output offset supply No signal 40 150 mV

SNR Signal to noise ratio (1) A-weighted, TAS5518 Modulator 103 dB

DNR Dynamic range A-weighted, input level –60 dBFS using TAS5518 modulator 103 dB

Power dissipation due to idlePidle PO = 0, 4 channels switching (2) 1.8 Wlosses (IPVDD_X)

(1) SNR is calculated relative to 1% THD+N output level.(2) Actual system idle losses also are affected by core losses of output inductors.

AUDIO SPECIFICATION (Single-Ended Output)Audio performance is recorded as a chipset consisting of a TAS5086 PWM Processor (modulation index limited to 97.7%)and a TAS5616 power stage. PCB and system configuration are in accordance with recommended guidelines. Audiofrequency = 1kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 4Ω, fS = 384 kHz, ROC_PHD = 22 kΩ, or ROC_DLD = 24 kΩ, TC =75°C, Output Filter: LDEM = 15 mH, CDEM = 330 nF, MODE = 100, unless otherwise noted.


RL = 4 Ω, 10%, THD+N 75PO Power output per channel W

RL = 4 Ω, 0 dBFS 60

THD+N Total harmonic distortion + noise 1 W 0.05%

Vn Output integrated noise A-weighted, TAS5086 modulator 170 mV

SNR Signal to noise ratio (1) A-weighted, TAS5086 modulator 98 dB

A-weighted, input level –60 dBFS using TAS5086DNR Dynamic range 98 dBmodulator

Power dissipation due to idle lossesPidle PO = 0, 4 channels switching (2) 2 W(IPVDD_X)

(1) SNR is calculated relative to 1% THD+N output level(2) Actual system idle losses are affected by core losses of output inductors.

AUDIO SPECIFICATION (PBTL)Audio performance is recorded as a chipset consisting of a TAS5518 PWM Processor (modulation index limited to 97.7%)and a TAS5616 power stage. PCB and system configuration are in accordance with recommended guidelines. Audiofrequency = 1kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 4Ω, fS = 384 kHz, ROC_PHD = 22 kΩ, ROC_DKD = 24 kΩ, TC = 75°C,Output Filter: LDEM = 15 mH, CDEM = 680 nF, MODE = 101-00, unless otherwise noted.


RL = 4 Ω, 10%, THD+N 300PO Power output per channel W

RL = 4 Ω, 1%, THD+N 210

THD+N Total harmonic distortion + noise 1 W 0.03%

Vn Output integrated noise A-weighted, TAS5518 modulator 180 mV

SNR Signal to noise ratio (1) A-weighted, TAS5518 modulator 103 dB

A-weighted, input level –60 dBFS usingDNR Dynamic range 103 dBTAS5518 modulator

Pidle Power dissipation due to idle losses (IPVDD_X) PO = 0, 4 channels switching (2) 1.8 W

(1) SNR is calculated relative to 1% THD+N output level(2) Actual system idle losses are affected by core losses of output inductors.







ELECTRICAL CHARACTERISTICSPVDD_X = 50 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 384 kHz, unless otherwise specified.


INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION

Voltage regulator, only used as referenceVREG VDD = 12 V 3 3.3 3.6 Vnode

VI_CM Analog comparator reference node 1.5 1.75 1.9 V

Operating, 50% duty cycle 22.5IVDD VDD supply current mA

Idle, reset mode 22.5

50% duty cycle 8IGVDD_x Gate-supply current per half-bridge mA

Reset mode 1.5

50% duty cycle without output filter or 9 mAloadIPVDD_x Half-bridge idle currentReset mode, No switching 610 mA

OUTPUT-STAGE MOSFETs

RDS(on),LS Drain-to-source resistance, (LS) 120 200 mΩTJ = 25°C, exclude metallizationresistance, GVDD = 12 VRDS(on),HS Drain-to-source resistance, (HS) 120 200 mΩ

I/O PROTECTION

Vuvp,G Undervoltage protection limit, GVDD_x 9.5 V

Vuvp,hyst(1) 0.6 V

OTW1 (1) Overtemperature warning 1 95 100 105 °C

OTW2 (1) Overtemperature warning 2 115 125 135 °C

Temperature drop needed below OTWOTWHYST

(1) temperature for OTW to be inactive after 25 °COTW event.

OTE (1) Overtemperature error 145 155 165 °C

OTE- OTE-OTW differential 30 °COTWdifferential(1)

A reset needs to occur for SD to be releasedOTEHYST(1) 25 °Cfollowing an OTE event

OLPC Overload protection counter fPWM = 384 kHz 2.6 ms

Resistor – programmable, nominal peakcurrent in 1Ω load, 64 pin QFP package

10 A(PHD)ROCP = 22 kΩ

IOC Overcurrent limit protectionResistor – programmable, nominal peakcurrent in 1Ω load, 44 pin PSOP3

10 Apackage (DKD)ROCP = 24 kΩResistor – programmable, nominal peakcurrent in 1Ω load,IOC_LATCHED Overcurrent limit protection 10 AROCP = 47 kΩTime from application of short condition to

IOCT Overcurrent response time 150 nsHi-Z of affected half bridge

Connected when RESET is active toIPD Output pulldown current of each half bridge provide bootstrap charge. Not used in SE 3 mA

mode.

STATIC DIGITAL SPECIFICATIONS

VIH High level input voltage 2 VINPUT_X, M1, M2, M3, RESET

VIL Low level input voltage 0.8 V

Leakage Input leakage current 100 mA

(1) Specified by design.







ELECTRICAL CHARACTERISTICS (continued)PVDD_X = 50 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 384 kHz, unless otherwise specified.


OTW/SHUTDOWN (SD)

Internal pull-up resistance, OTW1 to VREG,RINT_PU 20 26 32 kΩOTW2 to VREG, SD to VREG

Internal pull-up resistor 3 3.3 3.6VOH High level output voltage V

External pull-up of 4.7 kΩ to 5 V 4.5 5

VOL Low level output voltage IO = 4 mA 200 500 mV

Device fanout OTW1, OTW2, SD, CLIP,FANOUT No external pull-up 30 devicesREADY






20m 200100m 200m 1 2 10 20 100

P - Output Power - WO

0.005

10

0.01

0.02

0.05

0.1

0.2

0.5

1

2

5

TH

D+

N -

To

tal H

arm

on

ic D

isto

rtio

n +

No

ise -

%

T = 75°CC

8 W

25 27 29 31 33 35 37 39 41 43 45 47 49

V - Supply Voltage - VrmsCC

0

180

10

20

30

40

50

60

70

80

90

100

110

120

130

140

150

160

170

P-

Ou

tpu

t P

ow

er

- W

O

8 W

T = 75°C

THD+N at 10%C

0

100

10

20

30

40

50

60

70

80

90

0 36040 80 120 160 200 240 280 320

2 Channel Output Power - W

Eff

icie

ncy -

%

8 W

T = 25°C

THD+N at 10%C

0

150

10

20

30

40

50

60

70

80

90

100

110

120

130

140

25 27 29 31 33 35 37 39 41 43 45 47 49

P-

Ou

tpu

t P

ow

er

- W

O

V - Supply Voltage - VrmsCC

8 W

T = 75°C

THD+N at 1%C


TYPICAL CHARACTERISTICS, BTL CONFIGURATIONTOTAL HARMONIC+NOISE OUTPUT POWER

vs vsOUTPUT POWER SUPPLY VOLTAGE

Figure 1. Figure 2.

UNCLIPPED OUTPUT POWER SYSTEM EFFICIENCYvs vs

SUPPLY VOLTAGE OUTPUT POWER

Figure 3. Figure 4.






0

40

4

8

12

16

20

24

28

32

36

0 36040 80 120 160 200 240 280 320

2 Channel Output Power - W

Po

wer

Lo

ss -

W

T = 25°C

THD+N at 10%C

8 W

0

200

20

40

60

80

100

120

140

160

180

10 12020 30 40 50 60 70 80 90 100 110

T - Case Temperature - CC

P-

Ou

tpu

t P

ow

er

- W

O

8 W

THD+N at 10%

-160

0

-140

-120

-100

-80

-60

-40

-20

222 4 6 8 10 12 14 16 18 20f - Frequency - kHz

0

No

ise

Am

plitu

de -

dB

8 W

T = 75°C

V = 32.69V

Sample Rate = 48 kHzFFT Size = 16384

C

REF


TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)SYSTEM POWER LOSS OUTPUT POWER

vs vsOUTPUT POWER CASE TEMPERATURE

Figure 5. Figure 6.

NOISE AMPLITUDEvs

FREQUENCY - VREF = 32.7 V

Figure 7.






20m 100m 200m 1 2 10 20 100


0.005

10

0.01

0.02

0.05

0.1

0.2

0.5

1

2

5

TH

D -

To

tal H

arm

on

ic D

isto

rtio

n -

%

4 W

6 W

T = 75°CC

8 W

0

90

10

20

30

40

50

60

70

80

25 27 29 31 33 35 37 39 41 43 45 47 49P

- O

utp

ut

Po

wer

- W

OV - Supply Voltage - VrmsCC

4 W

6 W

8 W

T = 75°C

THD+N at 10%C

0

90

10

20

30

40

50

60

70

80

10 12020 30 40 50 60 70 80 90 100 110

T - Case Temperature - °CC

P-

Ou

tpu

t P

ow

er

- W

O

8 W

6 W

4 W

THD+N at 10%


TYPICAL CHARACTERISTICS, SE CONFIGURATIONTOTAL HARMONIC DISTORTION OUTPUT POWER


Figure 8. Figure 9.

OUTPUT POWERvs

CASE TEMPERATURE

Figure 10.






0

340

20

40

60

80

100

120

140

160

180

200

220

240

260

280

300

320

25 27 29 31 33 35 37 39 41 43 45 47 49V - Supply Voltage - VrmsCC

P-

Ou

tpu

t P

ow

er

- W

O

4 W

6 W

8 W

T = 75°C

THD+N at 10%C

0.005

10

0.01

0.02

0.1

0.2

1

2

TH

D -

To

tal H

arm

on

ic D

isto

rtio

n -

%

20m 500100m 200m 1 2 10 20 100 200


4 W

6 W

T = 75°CC

8 W

0

360

20

40

60

80

100

120

140

160

180

200

220

240

260

280

300

320

340

10 12020 30 40 50 60 70 80 90 100 110

P-

Ou

tpu

t P

ow

er

- W

O

T - Case Temperature - °CC

8 W

6 W

4 W

THD+N at 10%


TYPICAL CHARACTERISTICS, PBTL CONFIGURATIONTOTAL HARMONIC DISTORTION OUTPUT POWER


Figure 11. Figure 12.

OUTPUT POWERvs

CASE TEMPERATURE

Figure 13.







APPLICATION INFORMATION

PCB Material Recommendation

FR-4 Glass Epoxy material with 2 oz. (70 mm) is recommended for use with the TAS5616. The use of thismaterial can provide for higher power output, improved thermal performance, and better EMI margin (due tolower PCB trace inductance.

PVDD Capacitor Recommendation

The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. Thesecapacitors should be selected for proper voltage margin and adequate capacitance to support the powerrequirements. In practice, with a well designed system power supply, 1000mF, 63V will support moreapplications. The PVDD capacitors should be low ESR type because they are used in a circuit associated withhigh-speed switching.

Decoupling Capacitor Recommendations

In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits goodaudio performance, good quality decoupling capacitors should be used. In practice, X7R should be used in thisapplication.

The voltage of the decoupling capacitors should be selected in accordance with good design practices.Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in theselection of the 0.1mF that is placed on the power supply to each half-bridge. It must withstand the voltageovershoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripplecurrent created by high power output. A minimum voltage rating of 63V is required for use with a 50V powersupply.

System Design Recommendations

The following schematics and PCB layouts illustrate best practices in the use of the TAS5616.






IN_L

EFT_

N

IN_L

EFT_

P

R_R

IGH

T_N

IN_R

IGH

T_P

/RES

ET

/SD

/OTW

1

/OTW

2

/CLI

P

REA

DY

GVD

D/V

DD

(+

12

V)

PVD

D GVD

D/V

DD

(+

12

V)

PVD

D

PVD

D

GN

D

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

VREG

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

VREG

VREG

GN

D

GN

D

GN

D

GN

D

GN

DVREG

GN

D

OU

T_LE

FT_

M

OU

T_LE

FT_

P

+ -

OU

T_RIG

HT_

R

OU

T_RIG

HT_

P

+ -C7

81

0nF

C7

81

0nF

C5

36

80

nF

C5

36

80

nF

L10

15

uH

L10

15

uH

C4

2

33

nF

C4

2

33

nF

C1

8

10

0p

F

C1

8

10

0p

F

R7

43

.3R

R7

43

.3R

L11

15

uH

L11

15

uH

C5

26

80

nF

C5

26

80

nF

C4

03

3nF

C4

03

3nF

L13

15

uH

L13

15

uH

C6

92

.2uF

C6

92

.2uF

C3

2

10

0nF

C3

2

10

0nF

R1

0

10

0R

R1

0

10

0R

C6

02

.2uF

C6

02

.2uF

L12

15

uH

L12

15

uH

C7

61

0nF

C7

61

0nF

C6

22

.2uF

C6

22

.2uF

R3

3

3.3

R

R3

3

3.3

R

R1

9

47

k

R1

9

47

k

C2

51

0uF

C2

51

0uF

C5

06

80

nF

C5

06

80

nF

R7

33

.3R

R7

33

.3R

C7

71

0nF

C7

71

0nF

R7

23

.3R

R7

23

.3R

C2

0

4.7

nF

C2

0

4.7

nF

C3

3

10

0nF

C3

3

10

0nF

C3

01

00

nF

C3

01

00

nF

C6

7

10

00

uF

C6

7

10

00

uF

R2

0

22

.0k

R2

0

22

.0k

C6

12

.2uF

C6

12

.2uF

C7

21

nF

C7

21

nF

C2

1

4.7

uF

C2

1

4.7

uF

U1

0

TA

S5616P

HD

U1

0

TA

S5616P

HD

OC

_A

DJ

/RESE

T

C_ST

ARTU

P

INPU

T_A

INPU

T_B

VI_

CM

GN

D

AG

ND

VREG

INPU

T_C

INPU

T_D

TEST

NC

NC

/SD

/OTW

1

/OTW2

/CLIP

READY

M1

M2

M3

GND

GND

GVDD_C

GVDD_D

BST_D

OUT_D

OUT_D

PVDD_D

PVDD_D

GND_D

GN

D_A

GN

D_B

GN

D_B

OU

T_B

OU

T_B

PVD

D_B

PVD

D_B

BST

_B

BST

_C

PVD

D_C

PVD

D_C

OU

T_C

OU

T_C

GN

D_C

GN

D_C

GN

D_D

VDD

PSU_REF

NC

NC

NC

NC

GND

GND

GVDD_B

GVDD_A

BST_A

OUT_A

OUT_A

PVDD_A

PVDD_A

GND_A

C6

32

.2uF

C6

32

.2uF

R1

8

10

0R

R1

8

10

0R

C3

11

00

nF

C3

11

00

nF

R3

1

3.3

R

R3

1

3.3

R

C2

2

10

0nF

C2

2

10

0nF

C6

6

10

00

uF

C6

6

10

00

uF

C7

11

nF

C7

11

nF

R1

1

10

0R

R1

1

10

0R

R7

03

.3R

R7

03

.3R

C2

3

4.7

uF

C2

3

4.7

uF

C7

31

nF

C7

31

nF

R7

13

.3R

R7

13

.3R

R3

0

3.3

R

R3

0

3.3

R

C6

5

10

00

uF

C6

5

10

00

uF

R3

2

3.3

R

R3

2

3.3

R

C2

61

00

nF

C2

61

00

nF

C4

1

33

nF

C4

1

33

nF

C7

01

nF

C7

01

nF

C5

16

80

nF

C5

16

80

nF

R1

2

10

0R

R1

2

10

0R

C6

84

7uF

63

V

C6

84

7uF

63

V

R1

3

10

0R

R1

3

10

0R

C6

4

10

00

uF

C6

4

10

00

uF

C4

33

3nF

C4

33

3nF

C7

41

0nF

C7

41

0nF

C7

51

0nF

C7

51

0nF


Figure 14. Typical Differential (2N) BTL Application With BD Filters






IN_N

IN_P

/RES

ET /SD

/OTW

1

/OTW

2

/CLI

P

REA

DY

GVD

D (+

12

V)

PVD

D

GVD

D (+

12

V)

VD

D (+

12

V)

PVD

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

VREG

GN

D

GN

DG

ND

VREG

GN

DG

ND

GN

D

GN

DG

ND

GN

D

VREG

VREG

GN

D

GN

D

GN

D

GN

D

GN

D

VREG

GN

D

1 2 3 4 5 6 7 8 9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

OU

T_LE

FT_

M

OU

T_LE

FT_

P

+ -

10

0R

10

0R

2.2

uF

2.2

uF

47

uF

47

uF

3.3

R3

.3R

2.2

uF

2.2

uF

68

0nF

68

0nF

10

0nF

10

0nF

68

0nF

68

0nF

1nF

1nF

22

.0k

22

.0k

10

00

uF

10

00

uF

10

00

uF

10

00

uF

47

k4

7k

15

uH

15

uH

15

uH

15

uH

33

nF

33

nF

10

00

uF

10

00

uF

10

0nF

10

0nF

10

0nF

10

0nF

10

nF

10

nF

3.3

R3

.3R

10

0R

10

0R

10

nF

10

nF

4.7

nF

4.7

nF

10

0nF

10

0nF

4.7

uF

4.7

uF

10

0R

10

0R

2.2

uF

2.2

uF

15

uH

15

uH

15

uH

15

uH

2.2

uF

2.2

uF

10

00

uF

10

00

uF

10

0p

F1

00

pF

10

0nF

10

0nF

10

uF

10

uF

3.3

R3

.3R

33

nF

33

nF

3.3

R3

.3R

3.3

R3

.3R

33

nF

33

nF

3.3

R3

.3R

10

nF

10

nF

10

0nF

10

0nF

4.7

uF

4.7

uF

3.3

R3

.3R

33

nF

33

nF

TA

S5616P

HD

TA

S5616P

HD

OC

_A

DJ

/RESET

C_STA

RTU

P

INPU

T_A

INPU

T_B

VI_

CM

GN

D

AG

ND

VREG

INPU

T_C

INPU

T_D

TEST

NC

NC

/SD

/OTW

1

/OTW2

/CLIP

READY

M1

M2

M3

GND

GND

GVDD_C

GVDD_D

BST_D

OUT_D

OUT_D

PVDD_D

PVDD_D

GND_D

GN

D_A

GN

D_B

GN

D_B

OU

T_B

OU

T_B

PVD

D_B

PVD

D_B

BST_

B

BST_

C

PVD

D_C

PVD

D_C

OU

T_C

OU

T_C

GN

D_C

GN

D_C

GN

D_D

VDD

PSU_REF

NC

NC

NC

NC

GND

GND

GVDD_B

GVDD_A

BST_A

OUT_A

OUT_A

PVDD_A

PVDD_A

GND_A

1nF

1nF

2.2

uF

2.2

uF


Figure 15. Typical (2N) PBTL Application With AD Modulation Filters






IN_B

IN_A

IN_D

IN_C

/RES

ET

/SD

/OTW

1

/OTW

2

/CLI

P

REA

DY

PVD

D

A

PVD

D

B

PVD

D

C

PVD

D

D

A

B C D

GVD

D (+

12V)

PVD

D

GVD

D (+

12V)

VDD

(+12

V)

PVD

D

PVD

D

GN

D

GN

D

GN

D

GN

D

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

VREG

GN

D

VREG

GN

DG

ND

GN

D

GN

D

GN

D

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

DG

ND

VREG

VREG

GN

D

62

17

63 18

64

19

20

21

24

23

22

25

27

26

29

28

30

31

32

33

34

1

35

37

2

36

3

38

4

39

5 6

40

41

74

2

8 9

10

43

44

45

11

46

12

47

13

48

14

15

49

16

50

51

52

54

53

56

55

57

58

59

60

61

OU

T_B_M

OU

T_B_P

OU

T_D

_M

OU

T_D

_P

OU

T_C

_M

OU

T_C

_P

OU

T_A

_M

OU

T_A

_P

PV

DD

R_

CO

MP

50

V

49

V

48

V

<4

7 V

14

7 k

Ohm

13

0 k

Ohm

16

5 k

Ohm

18

2 k

Ohm

+ -

+ - + -

+ -

47

V

19

1 k

Ohm

15uH

15uH

2.2u

F2.

2uF

2.2u

F2.

2uF

100n

F10

0nF

3.3R

3.3R

470u

F47

0uF

470u

F47

0uF

10nF

10nF

470u

F47

0uF

470u

F47

0uF

33nF

33nF

15uH

15uH

3.3R

3.3R

100R

100R

47uF

47uF

10k

10k

3.3R

3.3R

10nF

10nF

470u

F47

0uF

3.3R

3.3R

100n

F10

0nF

330n

F33

0nF

TA

S5616P

HD

TA

S5616P

HD

OC

_A

DJ

/RESE

T

C_ST

ARTU

P

INPU

T_A

INPU

T_B

VI_

CM

GN

D

AG

ND

VREG

INPU

T_C

INPU

T_D

TEST

NC

NC

/SD

/OTW

1

/OTW2

/CLIP

READY

M1

M2

M3

GND

GND

GVDD_C

GVDD_D

BST_D

OUT_D

OUT_D

PVDD_D

PVDD_D

GND_D

GN

D_A

GN

D_B

GN

D_B

OU

T_B

OU

T_B

PVD

D_B

PVD

D_B

BST

_B

BST

_C

PVD

D_C

PVD

D_C

OU

T_C

OU

T_C

GN

D_C

GN

D_C

GN

D_D

VDD

PSU_REF

NC

NC

NC

NC

GND

GND

GVDD_B

GVDD_A

BST_A

OUT_A

OUT_A

PVDD_A

PVDD_A

GND_A

100n

F10

0nF

100R

100R

15uH

15uH

22.0

k22

.0k

100n

F10

0nF

4.7u

F4.

7uF

10uF

10uF

100n

F10

0nF

10k

10k

R_C

OM

PR_

CO

MP

R_C

OM

PR_

CO

MP

10k

10k

3.3R

3.3R

330n

F33

0nF

3.3R

3.3R 47

0uF

470u

F

100n

F10

0nF

3.3R

3.3R

10nF

10nF

3.3R

3.3R

10nF

10nF

10k

10k

100n

F10

0nF

R_C

OM

PR_

CO

MP

10k

10k

R_C

OM

PR_

CO

MP

47k

47k

4.7u

F4.

7uF

100n

F10

0nF

10k

10k

10k

10k

100R

100R

2.2u

F2.

2uF

100n

F10

0nF

100R

100R

100n

F10

0nF

10nF

10nF

330n

F33

0nF

10nF

10nF

15uH

15uH

3.3R

3.3R

10k

10k

10k

10k

10nF

10nF

100p

F10

0pF

100n

F10

0nF

2.2u

F2.

2uF

470u

F47

0uF

10k

10k

10k

10k

330n

F33

0nF

3.3R

3.3R

33nF

33nF

470u

F47

0uF

3.3R

3.3R

100n

F10

0nF

33nF

33nF

10nF

10nF

10k

10k

100n

F10

0nF

2.2u

F2.

2uF

10nF

10nF

100n

F10

0nF

100R

100R

10nF

10nF

3.3R

3.3R

33nF

33nF

3.3R

3.3R


Figure 16. Typical SE Application






IN_C

ENTE

R

IN_R

IGH

T

IN_L

EFT

/RES

ET /SD

/OTW

1

/OTW

2

/CLI

P

REA

DY

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D (+

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V)

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D

GVD

D (+

12

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VD

D (+

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PVD

D

PVD

D

PVD

D

PVD

D

GN

D

GN

D

GN

D

GN

D

GN

DG

ND

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D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

VREG

GN

D

VREG

GN

D

GN

DG

ND

VREG

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

DVREG

GN

D

VREG

62

17

63 18

64

19

20

21

24

23

22

25

27

26

29

28

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33

34

1

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74

2

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48

14

15

49

16

50

51

52

54

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56

55

57

58

59

60

61

OU

T_C

EN

TER_M

OU

T_C

EN

TER_P

OU

T_LE

FT_

P

OU

T_RIG

HT_

P

OU

T_LE

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M

OU

T_RIG

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47

V

19

1 k

Ohm

PV

DD

R_

CO

MP

50

V

49

V

48

V

<4

7 V

14

7 k

Ohm

13

0 k

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5 k

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18

2 k

Ohm

-+ -+ -+

15

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15

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10

k1

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33

nF

33

nF

3.3

R3

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4.7

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10

0R

10

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k1

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68

0nF

68

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10

0nF

10

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47

0uF

47

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47

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33

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R3

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00

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R_C

OM

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OM

P

1nF

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47

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10

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10

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10

0nF

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0nF

68

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k1

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15

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10

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10

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15

uH

3.3

R3

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3.3

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10

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10

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TA

S5616P

HD

TA

S5616P

HD

OC

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DJ

/RESET

C_STA

RTU

P

INPU

T_A

INPU

T_B

VI_

CM

GN

D

AG

ND

VREG

INPU

T_C

INPU

T_D

TEST

NC

NC

/SD

/OTW

1

/OTW2

/CLIP

READY

M1

M2

M3

GND

GND

GVDD_C

GVDD_D

BST_D

OUT_D

OUT_D

PVDD_D

PVDD_D

GND_D

GN

D_A

GN

D_B

GN

D_B

OU

T_B

OU

T_B

PVD

D_B

PVD

D_B

BST_

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BST_

C

PVD

D_C

PVD

D_C

OU

T_C

OU

T_C

GN

D_C

GN

D_C

GN

D_D

VDD

PSU_REF

NC

NC

NC

NC

GND

GND

GVDD_B

GVDD_A

BST_A

OUT_A

OUT_A

PVDD_A

PVDD_A

GND_A

10

k1

0k

22

.0k

22

.0k

10

nF

10

nF

10

nF

10

nF

10

0nF

10

0nF

47

uF

47

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10

0nF

10

0nF

10

0nF

10

0nF

10

nF

10

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10

k1

0k

33

0nF

33

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15

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15

uH

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2.2

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2.2

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10

nF

10

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nF

10

nF

47

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7k

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OM

P

10

0nF

10

0nF

10

0p

F1

00

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3.3

R3

.3R

10

0R

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33

nF

33

nF

47

0uF

47

0uF

2.2

uF

2.2

uF

3.3

R3

.3R


Figure 17. Typical 2.1 System (2N) Input BTL and (1N) Input SE Application






IN_L

EFT_

N

IN_L

EFT_

P

IN_R

IGH

T_N

IN_R

IGH

T_P /S

D

/OTW

REA

DY

GVD

D (+

12

V)

PVD

D

GVD

D (+

12

V)

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D (+

12

V)

PVD

D

PVD

D

/RES

ET

GN

DG

ND

GN

D

GN

DG

ND

GN

DG

ND

GN

D

GN

D

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

GN

D

VREG

GN

D

GN

D

GN

D

GN

D

GN

D

GN

DVREG

GN

D

GN

D

VREG

GN

D

GN

D

VREG

OU

T_LE

FT_

M

OU

T_LE

FT_

P

OU

T_RIG

HT_

M

OU

T_RIG

HT_

P

1 2 3 4 5 6 7 8 9

10

11

12

13

14

15

16

17

18

19

20

21

22

33

34

35

36

37

38

39

40

41

42

43

44

23

24

25

26

27

28

29

30

31

32

+ - + -

24

k2

4k

1.5

R1

.5R

10

0nF

10

0nF

15

uH

15

uH

33

nF

33

nF

10

nF

10

nF

15

uH

15

uH

33

nF

33

nF

1.5

R1

.5R

4.7

nF

4.7

nF

10

nF

10

nF

4.7

uF

4.7

uF

10

0nF

10

0nF

68

0nF

68

0nF

1nF

1nF

10

0nF

10

0nF

47

uF

47

uF

10

0nF

10

0nF

68

0nF

68

0nF10

00

uF

10

00

uF

3.3

R3

.3R

2.2

uF

2.2

uF

TA

S5

61

6D

KD

TA

S5

61

6D

KD

PSU

_REF

VD

D

OC

_A

DJ

/RESET

C_STA

RTU

P

INPU

T_A

INPU

T_B

VI_

CM

GN

D

AG

ND

VREG

INPU

T_C

INPU

T_D

TEST

NC

NC

/OTW

OU

T_D

OU

T_D

GN

D_D

GN

D_C

OU

T_C

PVD

D_C

BST_

C

BST_

B

PVD

D_B

OU

T_B

GN

D_B

GN

D_A

OU

T_A

OU

T_A

/SD

GVD

D_A

B

BST_

A

PVD

D_A

PVD

D_A

M1

M2

M3

GVD

D_C

D

BST_

D

PVD

D_D

REA

DY

PVD

D_D

10

0R

10

0R

1nF

1nF

10

nF

10

nF

47

k4

7k

33

nF

33

nF

10

0R

10

0R

2.2

uF

2.2

uF

2.2

uF

2.2

uF

10

00

uF

10

00

uF

10

0p

F1

00

pF

3.3

R3

.3R

2.2

uF

2.2

uF

10

uF

10

uF

3.3

R3

.3R

3.3

R3

.3R

1nF

1nF

10

0nF

10

0nF

10

0R

10

0R

10

00

uF

10

00

uF

10

nF

10

nF

68

0nF

68

0nF

10

0R

10

0R

4.7

uF

4.7

uF

15

uH

15

uH68

0nF

68

0nF

2.2

uF

2.2

uF

10

nF

10

nF

3.3

R3

.3R

10

0nF

10

0nF

10

0R

10

0R

33

nF

33

nF

15

uH

15

uH

1nF

1nF

10

00

uF

10

00

uF


Figure 18. Typical Input BTL Application and BD Modulation Filters DKD Package







THEORY OF OPERATION

POWER SUPPLIES

To facilitate system design, the TAS5616 needs only a 12V supply in addition to the (typical) 50V power-stagesupply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analogcircuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, isaccommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.

In order to provide outstanding electrical and acoustical characteristics, the PWM signal path including gate driveand output stage is designed as identical, independent half-bridges. For this reason, each half-bridge hasseparate gate drive supply (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X).Furthermore, an additional pin (VDD) is provided as supply for all common circuits. Although supplied from thesame 12V source, it is highly recommended to separate GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD onthe printed-circuit board (PCB) by RC filters (see application diagram for details). These RC filters provide therecommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors asclose to their associated pins as possible. In general, inductance between the power supply pins and decouplingcapacitors must be avoided. (See reference board documentation for additional information.)

For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor ischarged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and thebootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the outputpotential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWMswitching frequencies in the range from 300kHz to 400kHz, it is recommended to use 33nF ceramic capacitors,size 0603 or 0805, for the bootstrap supply. These 33nF capacitors ensure sufficient energy storage, even duringminimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remainingpart of the PWM cycle.

Special attention should be paid to the power-stage power supply; this includes component selection, PCBplacement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). Foroptimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin isdecoupled with a 2.2mF ceramic capacitor placed as close as possible to each supply pin. It is recommended tofollow the PCB layout of the TAS5616 reference design. For additional information on recommended powersupply and required components, see the application diagrams given previously in this data sheet.

The 12V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 50Vpower-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is notcritical as facilitated by the internal power-on-reset circuit. Moreover, the TAS5616 is fully protected againsterroneous power-stage turn on due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) arenon-critical within the specified range (see the Recommended Operating Conditions table of this data sheet).

SYSTEM POWER-UP/POWER-DOWN SEQUENCE

Powering Up

The TAS5616 does not require a power-up sequence. The outputs of the H-bridges remain in a high-impedancestate until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage protection(UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Although not specificallyrequired, it is recommended to hold RESET in a low state while powering up the device. This allows an internalcircuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output.

Powering Down

The TAS5616 does not require a power-down sequence. The device remains fully operational as long as thegate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltagethreshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is agood practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks.







ERROR REPORTING

The SD, OTW, OTW1 and OTW2 pins are active-low, open-drain outputs. Their function is for protection-modesignaling to a PWM controller or other system-control device.

Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW and OTW2 goes lowwhen the device junction temperature exceeds 125°C and OTW1 goes low when the junction temperatureexceeds 100°C (see the following table).

SD OTW1 OTW2, DESCRIPTIONOTW

0 0 0 Overtemperature (OTE) or overload (OLP) or undervoltage (UVP)

0 0 1 Overload (OLP) or undervoltage (UVP). Junction temperaturehigher than 100°C (overtemperature warning)

0 1 1 Overload (OLP) or undervoltage (UVP)

1 0 0 Junction temperature higher than 125°C (overtemperature warning)

1 0 1 Junction temperature higher than 100°C (overtemperature warning)

1 1 1 Junction temperature lower than 100°C and no OLP or UVP faults(normal operation)

Note that asserting either RESET low forces the SD signal high, independent of faults being present. TIrecommends monitoring the OTW signal using the system microcontroller and responding to an overtemperaturewarning signal by, e.g., turning down the volume to prevent further heating of the device resulting in deviceshutdown (OTE).

To reduce external component count, an internal pullup resistor to 3.3 V is provided on both SD and OTWoutputs. Level compliance for 5-V logic can be obtained by adding external pullup resistors to 5 V (see theElectrical Characteristics table of this data sheet for further specifications).

DEVICE PROTECTION SYSTEM

The TAS5616 contains advanced protection circuitry carefully designed to facilitate system integration and easeof use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such asshort circuits, overload, overtemperature, and undervoltage. The TAS5616 responds to a fault by immediatelysetting the power stage in a high-impedance (Hi-Z) state and asserting the SD pin low. In situations other thanoverload and over-temperature error (OTE), the device automatically recovers when the fault condition has beenremoved, i.e., the supply voltage has increased.

The device will function on errors, as shown in the following table.

BTL MODE PBTL MODE SE MODE

LOCAL ERROR IN TURNS OFF LOCAL ERROR IN TURNS OFF LOCAL ERROR IN TURNS OFF

A A AA+B A+B

B B BA+B+B+D

C C CB+D B+D

D D D

Bootstrap UVP does not shutdown according to the table, it shuts down the respective halfbridge.

PIN-TO-PIN SHORT CIRCUIT PROTECTION (PPSC)

The PPSC detection system protects the device from permanent damage in the case that a power output pin(OUT_X) is shorted to GND_X or PVDD_X. For comparison the OC protection system detects an over currentafter the demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection isperformed at startup i.e. when VDD is supplied, consequently a short to either GND_X or PVDD_X after systemstartup will not activate the PPSC detection system. When PPSC detection is activated by a short on the output,all half bridges are kept in a Hi-Z state until the short is removed, the device then continues the startup sequenceand starts switching. The detection is controlled globally by a two step sequence. The first step ensures thatthere are no shorts from OUT_X to GND_X, the second step tests that there are no shorts from OUT_X toPVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC filter. The







typical duration is < 15 ms/mF. While the PPSC detection is in progress, SD is kept low, and the device will notreact to changes applied to the RESET pins. If no shorts are present the PPSC detection passes, and SD isreleased. A device reset will not start a new PPSC detection. PPSC detection is enabled in BTL and PBTL outputconfigurations, the detection is not performed in SE mode. To make sure not to trip the PPSC detection system itis recommended not to insert resistive load to GND_X or PVDD_X.

OVERTEMPERATURE PROTECTION

The two different package options have individual over-temperature protection schemes.

PHD Package

The TAS5616 PHD package option has a three-level temperature-protection system that asserts an active-lowwarning signal (OTW1) when the device junction temperature exceeds 100°C (typical), (OTW2) when the devicejunction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), thedevice is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z)state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted.Thereafter, the device resumes normal operation.

DKD Package

The TAS5616 DKD package option has a two-level temperature-protection system that asserts an active-lowwarning signal (OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junctiontemperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputsbeing set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear theOTE latch, RESET must be asserted. Thereafter, the device resumes normal operation.

UNDERVOLTAGE PROTECTION (UVP) AND POWER-ON RESET (POR)

The UVP and POR circuits of the TAS5616 fully protect the device in any power-up/down and brownout situation.While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fullyoperational when the GVDD_X and VDD supply voltages reach stated in the Electrical Characteristics Table.Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold onany VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z)state and SD being asserted low. The device automatically resumes operation when all supply voltages haveincreased above the UVP threshold.

DEVICE RESET

When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance(Hi-Z) state.

In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enablesweak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high impedance state whenasserting the reset input low. Asserting reset input low removes any fault information to be signaled on the SDoutput, i.e., SD is forced high. A rising-edge transition on reset input allows the device to resume operation afteran overload fault. To ensure thermal reliability, the rising edge of reset must occur no sooner than 4 ms after thefalling edge of SD.

SYSTEM DESIGN CONSIDERATION

A rising-edge transition on reset input allows the device to execute the startup sequence and starts switching.

Apply only audio when the state of READY is high that will start and stop the amplifier without having audibleartifacts that is heard in the output transducers. If an overcurrent protection event is introduced the READY signalgoes low hence filtering is needed if the signal is intended for audio muting.

The CLIP signal is indicating that the output is approaching clipping. The signal can be used to either an audiovolume decrease or intelligent power supply controlling a low and a high rail.

The VREG pin is not recommended to be used as a voltage source for external circuitry.







PRINTED CIRCUIT BOARD RECOMMENDATION

Use an unbroken ground plane to have good low impedance and inductance return path to the power supply forpower and audio signals. PCB layout, audio performance and EMI are linked closely together. The circuitcontains high fast switching currents; therefore, care must be taken to prevent damaging voltage spikes. Routingthe audio input should be kept short and together with the accompanied audio source ground. A local groundarea underneath the device is important to keep solid to minimize ground bounce.

Netlist for this printed circuit board is generated from the schematic in Figure 14.

Note T1: PVDD decoupling bulk capacitors C60-C64 should be as close as possible to the PVDD and GND_X pins,the heat sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins andwithout going through vias. No vias or traces should be blocking the current path.

Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink andclose to the pins.

Note T3: Heat sink needs to have a good connection to PCB ground.

Note T4: Output filter capacitors must be linear in the applied voltage range preferable metal film types.

Figure 19. Printed Circuit Board - Top Layer







Note B1: It is important to have a direct low impedance return path for high current back to the power supply. Keepimpedance low from top to bottom side of PCB through a lot of ground vias.

Note B2: Bootstrap low impedance X7R ceramic capacitors placed on bottom side providing a short low inductancecurrent loop.

Note B3: Return currents from bulk capacitors and output filter capacitors.

Figure 20. Printed Circuit Board - Bottom Layer

REVISION HISTORY

Changes from Original (June 2009) to Revision A Page

• Deleted Product Preview from the PHD package ................................................................................................................. 3

Changes from Revision A (September 2009) to Revision B Page

• NC pin function changed from "I/O" to "—" .......................................................................................................................... 5

• OLPC typical value changed from 1.3 ms to 2.6 ms ............................................................................................................ 9

• Changed error-reporting bits from 010 to 011 .................................................................................................................... 22






PACKAGE OPTION ADDENDUM

www.ti.com 18-Oct-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

TAS5616DKD NRND HSSOP DKD 44 29 Green (RoHS& no Sb/Br)

CU NIPDAU | Call TI Level-4-260C-72 HR 0 to 70 TAS5616

TAS5616DKDR NRND HSSOP DKD 44 500 Green (RoHS& no Sb/Br)

CU NIPDAU | Call TI Level-4-260C-72 HR 0 to 70 TAS5616

TAS5616PHD NRND HTQFP PHD 64 90 Green (RoHS& no Sb/Br)

CU NIPDAU Level-5A-260C-24 HR 0 to 70 TAS5616

TAS5616PHDR NRND HTQFP PHD 64 1000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-5A-260C-24 HR 0 to 70 TAS5616

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

http://www.ti.com/productcontent

PACKAGE OPTION ADDENDUM

www.ti.com 18-Oct-2013

Addendum-Page 2

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

TAS5616DKDR HSSOP DKD 44 500 330.0 24.4 14.7 16.4 4.0 20.0 24.0 Q1

TAS5616PHDR HTQFP PHD 64 1000 330.0 24.4 17.0 17.0 1.5 20.0 24.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 7-May-2016

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TAS5616DKDR HSSOP DKD 44 500 367.0 367.0 45.0

TAS5616PHDR HTQFP PHD 64 1000 367.0 367.0 45.0

PACKAGE MATERIALS INFORMATION

www.ti.com 7-May-2016

Pack Materials-Page 2

http://www.ti.com/lit/slma002

http://www.ti.com/lit/slma004

www.ti.com

PACKAGE OUTLINE

C

TYP14.513.9

42X 0.65

44X 0.380.25

2X13.65

(0.28) TYP

0 - 80.30.1

12.712.6

5.95.8

3.63.1

0.35GAGE PLANE

1.10.8

A

NOTE 3

16.015.8

BNOTE 4

11.110.9

(2.95)

(0.15)EXPOSED THERMAL PAD

PowerPAD SSOP - 3.6 mm max heightDKD0044APLASTIC SMALL OUTLINE

4218846/A 07/2016

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.4. The exposed thermal pad is designed to be attached to an external heatsink.

PowerPAD is a trademark of Texas Instruments.

TM

1 44

0.12 C A B

2322

PIN 1 ID AREA

EXPOSEDTHERMAL PAD

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL ATYPICAL

SCALE 1.000

www.ti.com

EXAMPLE BOARD LAYOUT

(13.2)

0.05 MAXAROUND

0.05 MINAROUND

44X (2)

44X (0.45)

42X (0.65)

(R0.05) TYP


4218846/A 07/2016

SYMM

SYMM

SEE DETAILS

LAND PATTERN EXAMPLESCALE:6X

1

22 23

44

TM

NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METALSOLDER MASKOPENING

NON SOLDER MASKDEFINED

SOLDER MASK DETAILSNOT TO SCALE

OPENINGSOLDER MASK METAL UNDER

SOLDER MASK

SOLDER MASKDEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

44X (2)

44X (0.45)

42X (0.65)

(13.2)

(R0.05) TYP


4218846/A 07/2016

NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design.

TM

SOLDER PASTE EXAMPLEBASED ON 0.125 MM THICK STENCIL

SCALE:6X

SYMM

SYMM

1

22 23

44

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http://www.ti.com/sc/docs/sampterms.htm

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160-W Stereo / 300-W Mono PurePath(TM) HD Digital-Input Power