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07/03/22 Anue Systems, Inc. www.anuesystems.com 1 v1.0 - 20050426 D ocum entCoverSheet ProjectN um ber PN -3-3175-RV 2 D ocum entTitle N etw ork m odel forG.8261 Source A nue System s C ontact Name: Chip W ebb Com plete A ddress: 9111 Jollyville Rd A ustin, TX 78759 Phone:512-527-0453x102 Fax: Email: cwebb@ anuesystems.com D istribution TR-30.3 ForIncorporation Into TIA Publication x ForInformation Intended Purpose ofD ocum ent (Selectone) Other(describe)- The docum entto which this coverstatem entis attached is subm itted to a Form ulating G roup or sub-elem entthereofofthe Telecom m unications Industry A ssociation (TIA )in accordance with the provisionsofSections6.4.1–6.4.6 inclusive ofthe TIA EngineeringM anualdated M arch 2005,all of which provisionsare hereby incorporated by reference. A bstract Like TIA-921, ITU-T G.8261 seeksto model delay and lossin packetnetworks. Thisdocumentdescribes a model used forG.8261 and showscomparisonsbetween that model resultsand actual laboratory m easurem ents. Telecommunications Industry Association TR-30.3/08-12-016 Lake Buena Vista, FL December 8 - 9, 2008

10/11/2014Anue Systems, Inc. 1 v1.0 - 20050426 Telecommunications Industry AssociationTR-30.3/08-12-016 Lake Buena Vista, FL December

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Page 1: 10/11/2014Anue Systems, Inc.  1 v1.0 - 20050426 Telecommunications Industry AssociationTR-30.3/08-12-016 Lake Buena Vista, FL December

04/11/23 Anue Systems, Inc.

www.anuesystems.com

1

v1.0 - 20050426

Document Cover Sheet

Project Number PN-3-3175-RV2

Document Title Network model for G.8261

Source Anue Systems

Contact Name: Chip Webb Complete Address: 9111 Jollyville Rd Austin, TX 78759

Phone: 512-527-0453x102 Fax: Email: [email protected]

Distribution TR-30.3

For Incorporation Into TIA Publication x For Information

Intended Purpose of Document (Select one) Other (describe) -

The document to which this cover statement is attached is submitted to a Formulating Group or sub-element thereof of the Telecommunications Industry Association (TIA) in accordance with the provisions of Sections 6.4.1–6.4.6 inclusive of the TIA Engineering Manual dated March 2005, all of which provisions are hereby incorporated by reference.

Abstract

Like TIA-921, ITU-T G.8261 seeks to model delay and loss in packet networks. This document describes a model used for G.8261 and shows comparisons between that model results and actual laboratory measurements.

Telecommunications Industry Association TR-30.3/08-12-016Lake Buena Vista, FL December 8 - 9, 2008

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Problem statement

G.8261 currently describes a way (in Appendix VI) to test sync Interworking Functions by building a testbed.

But -- it’s not repeatable.

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Initial results matchInput profile Measured result

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A test bed Measure delay under G.8261 Appendix VI test

conditions…..

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Model-based impairment profiles

Build a bottom-up model of each network element

Construct test scenarios by connecting together various model elements and run a simulation Validate end-to-end results

Still has shortcomings As network changes, model params must also change New technologies may require new model elements Harder to make a general model than to measure one

sample

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Why create a software model?

Creating a model and validating it against real networks provides valuable insight to guide further work Which device parameters are most

important What metrics work best What’s the best way to test

(interop/conformance) Understand tradeoffs in system deployment

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Discrete event simulation of test bed..

One way to model is to use a discrete event simulator

Develop models for the switches and dummy traffic generators.

Anue is developing one such model for MEF18 testing.

This is just the beginning of modeling Further refinements are possible

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Switch model Three main blocks in the switch model

Ingress, Queuing, Egress Ingress block:

Each input port has one. Makes forwarding decisions (L2/L3) There’s no contention here. Introduces delay (store/forward or cut-through)

Queuing block: One or more queues per output port. Holds packets till sent

out. Contention can happen here. Queue has limited size (shared) Queue memory allocated in N-byte chunks. May implement congestion avoidance (e.g. WRED) Introduces queuing delay and packet loss.

Egress: Each output port has one. Services queues at the port’s bit

rate. If multiple output queues, contention can also happen here

(e.g. Strict Priority, WRR, WFQ)

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Model assumptions

Initial focus is queuing delays In the forward direction only

All switches are non-PTP capable (asynch)

No priority or congestion avoidance Wire delay is constant Assume each switch has at least one

flip-flop domain transfer Ignore oscillator noise

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Model parameters

Ten switches (based on G.8261) Dummy load is Traffic Model 2 Queue size is 64k bytes

Allocated and deallocated in 64 byte chunks All links are gigabit Measure delay 1000 times per second

Model outputs Packet delay Packet drop

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But can’t realistically simulate all packets

A 24-hour simulation of a 10 hop network built out of GE switches and operating at 50% load with 1400 byte (avg) packets represents about 40 Billion packets.

That’s half a petabit. If you watched HDTV for two years

straight, without sleeping, it would use about that many bits.

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Example model results (20% load TM2)

Reference (test bed)S/W Model Results

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Simulation Results MEF18, 6.2a

Based on G.8261 Appendix VI Test Case 3

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Simulation Results MEF18, 6.6a

Based on G.8261 Appendix VI Test Case 5 (congest 100s)