100-1000 GHz Bipolar ICs: Device and Circuit Design Principles · Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright 100-1000 GHz Bipolar ICs: Device and Circuit Design

Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright

100-1000 GHz Bipolar ICs:

Device and Circuit Design Principles

Mark Rodwell, UCSB Munkyo Seo, Teledyne Scientific

Short Course, IEEE Bipolar / BiCMOS Circuits and Technology Meeting, 9 October 2011, Atlanta, Georgia

[email protected] , [email protected]

Collaborators:

UCSB HBT Team: V. Jain, E. Lobisser, A. Baraskar, J. Rode, H.W. Chiang, A. C. Gossard , B. J. Thibeault, W. Mitchell

Teledyne HBT Team: M. Urteaga, R. Pierson, P. Rowell, B. Brar, Teledyne Scientific Company

Teledyne IC Design Team: J. Hacker, Z. Griffith, A. Young, M. J. Choe, Teledyne Scientific Company

UCSB IC Design Team: S. Danesgar, T. Reed, Eli Bloch, H-C Park, J-H Kim


Motivation /

Overview


DC to Daylight. Far-Infrared Electronics

0.3- 3 THz imaging systems

109

1010

1011

1012

1013

1014

1015

Frequency (Hz)

microwave

3-30 GHz

mm-wave

30-300 GHz

far-IR

(sub-mm)

0.3-3THz

mid-IR

3-30 THz

near-IR

30-450 THz

op

tica

l

45

0-9

00

TH

zHow high in frequency can we push electronics ?

...and what would be do with it ?

0.3-3 THz radio: vast capacity bandwidth, # channels

0.1-1 Tb/s optical fiber links


THz Transistors: Not Only For THz Circuits

THz amplifiers→ THz radios → imaging, sensing, communications

precision analog design at microwave frequencies → high-performance receivers

500 GHz digital logic → fiber optics

Higher-Resolution Microwave ADCs, DACs, DDSs


ICs to 600 GHz : Teledyne and UCSB

570 GHz fundamental VCO

340 GHz dynamic frequency divider

Vout

VEE VBB

Vtune

Vout

VEE VBB

Vtune

430 GHz low-noise amplifier M. Seo, TSC other ICs by J. Hacker

M. Seo, TSC CSIC 2010

M. Seo, TSC IEEE MWCL 2010

204 GHz static frequency divider (ECL master-slave latch)

Z. Griffith, TSC CSIC 2010

300 GHz fundamental PLL M. Seo, TSC IMS 2011

40 GHz op-amp with 54 dBm IP3 at 2 GHz

Z. Griffith, TSC IMS 2011

220 GHz 48 mW power amplifier

T. Reed, UCSB CSIC 2011

Other ICs in design: 30-40 GS/s track/hold optical PLLs coherent optical receivers 340 GHz arrays


At High Frequencies The Atmosphere Is Opaque Mark Rosker

IEEE IMS 2007


THz Bipolar Transistors: Where Next ?

array transmitters: critical for sub-mm-wave radio / radar

32 x 32 array → 60-90 dB increased SNR →vastly increased range

Rtransmitreceive

transmit

received eR

NN

P

P 2

2

16

0

20

40

60

80

100

106

107

108

109

1010

1011

1012

Sta

ge

Volta

ge

Gain

, d

B

Frequency, Hz

gain @ 100 MHzdesign frequency

)||||(

decreasing

outloadin, RRRg xm

0

20

40

60

80

100

106

107

108

109

1010

1011

1012

Sta

ge

Volta

ge

Gain

, d

B

Frequency, Hz

)/( ,,

increasing

max loadbias CIff

HBT / HEMT integration for mixed-signal III-V NFET vs. Si PFET active loads: much lower Cload/Ibias

LSI @ 128 nm node: scaled interconnects high packing density → speed, power

32 nm / 3 THz node, beyond Transition to production

340 GHz 670 GHz 1080 GHz

R&D→ pilot → foundry design tools, reliability, scaled interconnects CMOS control integration: 3-D, flip chip


Bipolar Transistors:

Models,

Scaling Laws,

State of Art,

Roadmaps


Bipolar Transistor: Structure & Models

nkTqIg Em /

)( cbmjebe gCC

mbe gR /

""

2

2/

/2/

satcc

thermalbnbb

vT

vTDT

collex

E

bc

E

jecollectorbase RRqI

nkTC

qI

nkTC

f

2

1


Base-Collector Distributed RC Parasitics

emitteremittercontactex AR /,

Eesspread LWR 12/ ELlength emitter

Egapsgap LWR 4/

Ebcscontactspread LWR 6/,

contactsbasebasecontactcontact AR _, /

cemitterecb TAC /,

cgapgapcb TAC /,

ccontactsbasecontactcb TAC /_,


RbbCcb Time Constant, Fmax , Simple Hybrid- model

where8max cbibbCRff

)(

)2/(

,,

,,

,

spreadgapcontactspreadcontactecb

gapcontactspreadcontactgapcb

contactcontactcbcbibbcb

RRRRC

RRRC

RCCR

above from fit set to ratio :

total true

resistance base totaltrue

maxfCC

CCC

R

cbxcbi

cbcbxcbi

bb

Vaidyanathan & Pulfrey IEEE Trans. Elect. Dev. Feb. 1999


Key 2nd-Order Effects in III-V HBTs: Omitted for Brevity

Betser and Ritter , IEEE Trans. Elect. Dev., April 1999 Urteaga & Rodwell, IEEE Trans. Elect. Dev., July 2003

c decreases :overshoot velocity induced-Current

.modulationvelocity collector by on cancellati Partial cbC

exR increases :base intoinjection electron Degenerate

Nakajima, Japanese Journal of Applied Physics, Feb. 1997

More detailed information regarding III-V bipolar transistor physics and design: http://www.ece.ucsb.edu/Faculty/rodwell/publications_and_presentations/publications/2009_may_IPRM_short_course_rodwell.pdf

0

0.5

1

1.5

2

2.5

0 0.5 1 1.5 2 2.5 3 3.5

tau

ec,

ps

inverse current density, 1/J,m2/mA

2

3

4

5

6

7

8

0 2.5 5 7.5 10 12.5

Ccb/A

e (

fF/

m2)

Je (mA/m

2)

-0.2 V

0.0 V

0.2 V

Vcb

= 0.6 V

10-3

10-2

10-1

100

101

102

-0.3 -0.2 -0.1 0 0.1 0.2J(m

A/u

m^2

)V

be-

Fermi-Dirac

Equivalent series

resistance approximation

Boltzmann

Rodwell, Le, Brar, Proc IEEE , February 2008 Jain & Rodwell, IEEE Electron. Dev. Lett., to be published (2011)

c increases :velocitycollector of modulation Voltage


Space Charge, Kirk Effect, Minimum Ccb charging time

)2/)(/( 2 cdsatcb TqNvJV

)2/)(( 2

min, cTqNV dcb

eff

C

CECE

LOGIC

CLOGICcCLOGICcbv

T

A

A

VV

VIVTAIVC

2/

emitter

collector

min,

collector

2

min,max/)2(2

ccbcbeffTVVvJ

cecbbe VVV )( hence , that Note

Collector capacitance charging time minimized by setting J = Jmax

...if so, charging time scales linearly with collector thickness.

Collector Field Collapse

Collector Depletion Layer Collapse

SiGe HBT InP DHBT


Space-Charge-Limited Current (Kirk effect) in BJTs

. increased with increases holdKirk thres

.high at increased, ), ( Decreased max

ce

cb

V

JCff

CEEeffective

effectivesat

c

c

ce

satce

TWLA

Av

TR

dI

dV

JV

2

is areaflux current

collector effective thewhere

2

increased with in Increase

2

chargespace

,

0

2

4

6

8

10

12

14

16

0 0.5 1 1.5 2 2.50

5

10

15

20

25

30

35

40

Je (

mA

/m

2)

Vce

(V)

Ajbe

= 0.6 x 4.3 m2

Ib step

= 180 uA

Vcb

= 0 V

Ic (mA

)

Peak ft, f

max

2

3

4

5

6

7

8

0 2.5 5 7.5 10 12.5

Ccb/A

e (

fF/

m2)

Je (mA/m

2)

-0.2 V

0.0 V

0.2 V

Vcb

= 0.6 V

100

200

300

400

500

0 2 4 6 8 10 12

f (

GH

z)

Je (mA/um

2)

f, -0.3 V

cb

0.0 Vcb

-0.2 Vcb

0.2 Vcb

0.6 Vcb

Bipolar Transistor Design eW

bcWcTbT

nbb DT 22

satcc vT 2

ELlength emitter

eex AR /contact

2

through-punchce,operatingce,max cesatc TVVAvI /)(,

contacts

contactsheet

612 AL

W

L

WR

e

bc

e

ebb

e

e

E W

L

L

PT ln1

cccb /TAC

Bipolar Transistor Design: Scaling eW

bcWcTbT

nbb DT 22

satcc vT 2

ELlength emitter cccb /TAC

eex AR /contact

2

through-punchce,operatingce,max cesatc TVVAvI /)(,

contacts

contactsheet

612 AL

W

L

WR

e

bc

e

ebb

e

e

E W

L

L

PT ln1

Breakdown is Never Less Than The Bandgap


Bipolar Transistors: Scaling Laws, Scaling Roadmap

HBT parameter change

emitter & collector junction widths decrease 4:1

current density (mA/m2) increase 4:1

current density (mA/m) constant

collector depletion thickness decrease 2:1

base thickness decrease 1.4:1

emitter & base contact resistivities decrease 4:1

scaling laws: to double bandwidth

InP HBT scaling roadmap

eW

bcWcTbT

ELlength emitter

150 nm device


Recent InP HBT Results: Urteaga et al, DRC 2011


Recent InP HBT Results: Jain et al, DRC 2011

30nm emitter, 30nm base, 100nm collector

0

4

8

12

16

20

24

28

32

109

1010

1011

1012

Gain

(d

B)

Frequency (Hz)

U

H21

f = 480 GHz

fmax

= 1.0 THz

Aje = 0.22 x 2.7 m

2

Ic = 12.1 mA

Je = 20.4 mA/m

2

P = 33.5 mW/m2

Vcb

= 0.7 V

0

5

10

15

20

25

30

0 1 2 3 4 5

Je (

mA

/m

2)

Vce

(V)

P = 30 mW/m2

Ib,step

= 200 A

BV

P = 20 mW/m2

Aje

= 0.22 x 2.7 m2

10-9

10-7

10-5

10-3

10-1

0

5

10

15

20

0 0.2 0.4 0.6 0.8 1

I c, I b

(A

)

Vbe

(V)

Solid line: Vcb

= 0.7V

Dashed: Vcb

= 0V

nc = 1.19

nb = 1.87

Ic

Ib


Can we make a 1 THz SiGe Bipolar Transistor ?

InP SiGe

emitter 64 18 nm width

2 0.6 m2 access

base 64 18 nm contact width,

2.5 0.7 m2 contact

collector 53 15 nm thick

36 125 mA/m2

2.75 1.3? V, breakdown

f 1000 1000 GHz

fmax 2000 2000 GHz

PAs 1000 1000 GHz

digital 480 480 GHz

(2:1 static divider metric)

Assumes collector junction 3:1 wider than emitter.

Assumes SiGe contacts no wider than junctions

Simple physics clearly drives scaling

transit times, Ccb/Ic

→ thinner layers, higher current density

high power density → narrow junctions

small junctions→ low resistance contacts

Key challenge: Breakdown

15 nm collector → very low breakdown

Also required:

low resistivity Ohmic contacts to Si

very high current densities: heat


Interconnects


kz

III-V MIMIC Interconnects -- Classic Substrate Microstrip

Strong coupling when substrate approaches ~d / 4 thickness

H

W

Thick Substrate

→ low skin loss

Hr

skin 2/1

1

Zero ground

inductance

in package

a

Brass carrier andassembly ground

interconnectsubstrate

IC with backsideground plane & vias

near-zeroground-groundinductance

IC viaseliminateon-wafergroundloops

High via

inductance

12 pH for 100 m substrate -- 7.5 @ 100 GHz

TM substrate

mode coupling

Line spacings must be

~3*(substrate thickness)

lines must be

widely spaced

ground vias must be

widely spaced

all factors require very thin substrates for >100 GHz ICs

→ lapping to ~50 m substrate thickness typical for 100+ GHz

No ground plane

breaks in IC


kz

Parasitic slot mode

-V 0V +V

0V

Coplanar Waveguide No ground vias

No need (???) to

thin substrate

Parasitic microstrip mode

+V +V +V

0V

Hard to ground IC

to package

substrate mode coupling

or substrate losses

ground plane breaks → loss of ground integrity

Repairing ground plane with ground straps is effective only in simple ICs

In more complex CPW ICs, ground plane rapidly vanishes

→ common-lead inductance → strong circuit-circuit coupling

40 Gb/s differential TWA modulator driver

note CPW lines, fragmented ground plane

35 GHz master-slave latch in CPW

note fragmented ground plane

175 GHz tuned amplifier in CPW

note fragmented ground plane

poor ground integrity

loss of impedance control

ground bounce

coupling, EMI, oscillation

III-V:

semi-insulating

substrate→ substrate

mode coupling

Silicon

conducting substrate

→ substrate

conductivity losses


fewer breaks in ground plane than CPW

III-V MIMIC Interconnects -- Thin-Film Microstrip

narrow line spacing → IC density

... but ground breaks at device placements

still have problem with package grounding

thin dielectrics → narrow lines

→ high line losses

→ low current capability

→ no high-Zo lines

H

W

HW

HZ

r

oo 2/1

~

...need to flip-chip bond

no substrate radiation, no substrate losses

InP 34 GHz PA

(Jon Hacker , Teledyne)


No breaks in ground plane

III-V MIMIC Interconnects -- Inverted Thin-Film Microstrip


... no ground breaks at device placements







Some substrate radiation / substrate losses

InP 150 GHz master-slave latch

InP 8 GHz clock rate delta-sigma ADC


If It Has Breaks, It Is Not A Ground Plane !

signal line

signal line

ground plane

line 1

“ground”

line 2

“ground”

common-lead inductance

coupling / EMI due to poor ground system integrity is common in high-frequency systems

whether on PC boards

...or on ICs.


No clean ground return ? → interconnects can't be modeled !

35 GHz static divider

interconnects have no clear local ground return

interconnect inductance is non-local

interconnect inductance has no compact model

InP 8 GHz clock rate delta-sigma ADC

8 GHz clock-rate delta-sigma ADC

thin-film microstrip wiring

every interconnect can be modeled as microstrip

some interconnects are terminated in their Zo

some interconnects are not terminated

...but ALL are precisely modeled


VLSI mm-wave interconnects with ground integrity

negligible breaks in ground plane


negligible ground breaks @ device placements







no substrate radiation, no substrate losses

Also:

Ground plane at *intermediate level* permits

critical signal paths to cross supply lines, or other

interconnects without coupling.

(critical signal line is placed above ground,

other lines and supplies are placed below ground)


Modeling Interconnects, Passives in Tuned ( RF ) IC's

Interconnects are tuning elements

Narrow bandwidths→ precision is critical

Initial IC simulation uses CAD-systems' library of passive element models.

Final design: 2.5-Dimensional electromagnetic simulation of: lines, junctions, stubs, capacitors, resistors, pads.

150-200 GHz HBT amplifier, Urteaga et al, IEEE JSSCC , Sept. 2003

185GHz HBT amplifier, Urteaga et al, IEEE IMS, May. 2001

1-180GHz HBT amplifier, Agarwal et al, IEEE Trans MTT , Dec.. 1998


Modeling Interconnects: Digital & Mixed-Signal IC's

longer interconnects: lines terminated in Zo → no reflections.

Shorter interconnects: lines NOT terminated in Zo . But they are *still* transmission-lines. Ignore their effect at your peril !

vl

ZC

ZL

/

,/

,

0

0

If length << wavelength, or line delay<<risetime, short interconnects behave as lumped L and C.


Design Flow: Digital & Mixed-Signal IC's

All interconnects: thin-film microstrip environment. Continuous ground on one plane.

2.5-D simulations run on representative lines. various widths, various planes same reference (ground) plane.

Simulation data manually fit to CAD line model effective substrate r , effective line-ground spacing.

Width, length, substrate of each line entered on CAD schematic. rapid data entry, rapid simulation.

Resistors and capacitors: 2.5-D simulation→ RLC fit RLC model used in simulation.


Network analyzer

Calibration...

on-wafer LRL


On-Wafer Through-Reflect-Line (TRL) Calibration

Through

Reflect

Line

Device Under Test

225um

reference plane

ΔL ΔL= 90 deg @center frequency. /8<ΔL<3/8

DUT

open short Either open or short needed. Standards need not be accurate. "Open" must have G closer to that of open than that of short. Ports 1 & 2 must be symmetric.

Through line should be long for large probe separation. Minimizes probe-probe coupling. Measurements normalized to the line characteristic impedance.

225um

225um 225um

225um

225um Please see also: http://www.ece.ucsb.edu/Faculty/rodwell/publications_and_presentations/publications/204vg.ppt

http://www.ece.ucsb.edu/Faculty/rodwell/publications_and_presentations/publications/204vg.ppt


On-Wafer TRL: Ongoing Issues

High-fmax transistors have very small ( Ccb → Y12 → S12 )

Measurements show small background Y12. ...even with extended reference planes. Particular difficulty in extracting Mason's Unilateral gain. → Corrupts fmax measurement, model extraction.

Measurements normalized to line Z0. ...line impedance is complex at lower frequencies. → must correct for complex Zo in measurements. excessive line resistance degrades precision.

TRL precision greatly impaired if lines couple to substrate; CPW line standards do not work well.

Cj

LjjRZO

)(


Verification of 140-220GHz TRL Calibration

freq (140.0GHz to 200.0GHz)

S(1

,1)

S(2

,2)

150 160 170 180 190140 200

-0.4

-0.2

0.0

0.2

-0.6

0.4

freq, GHz

dB

(S(2

,1))

dB

(S(1

,2))

Through


S(1

,1)

S(2

,2)

150 160 170 180 190140 200

-45

-40

-35

-30

-50

-25

freq, GHz

dB

(S(2

,1))

dB

(S(1

,2))

Open Line


S(1

,1)

S(2

,2)

150 160 170 180 190140 200

-0.8

-0.6

-0.4

-1.0

-0.2

freq, GHz

dB

(S(2

,1))

dB

(S(1

,2))

150 160 170 180 190140 200

-120

-100

-140

-80

freq, GHz

ph

ase

(S(2

,1))

Readout

m10 m10freq=phase(S(2,1))=-91.553

150.0GHz

M. Seo


Difficulties with 140-220GHz TRL Calibration

Data on two layouts of 65 nm MOSFET

2E

11

3E

11

4E

11

5E

11

6E

11

7E

11

8E

11

9E

11

1E

11

1E

12

1

2

3

4

5

6

7

8

9

0

10

freq, Hz

MS

GM

AG

_d

B_

ibm

MS

GM

AG

_d

B_

pfg

MA

G/M

SG

, dB

2E

11

3E

11

4E

11

5E

11

6E

11

7E

11

8E

11

9E

11

1E

11

1E

12

2

4

6

8

10

12

14

16

18

0

20

freq, Hz

Um

_ib

m_

dB

Um

_p

fg_

dB

150 160 170 180 190140 200

-15

-10

-5

0

5

10

15

-20

20

freq, GHz

Um

_ib

mU

m_

pfg

U < 0 (!)

10*log10|U| (?)

"Un

ilate

ral g

ain

", d

B

"Un

ilate

ral g

ain

", lin

ea

r

Measured Y-parameters correlate reasonably with expected device model. Small errors in measured 2-port parameters result in large changes in Unilateral gain and Rollet's stability factor; neither measurement is credible.

Y12 appears to be the key problem. IC Sij measurements are fine. Transistor fmax measurements are hard.

12212211

2

1221

4 GGGG

YYU

( K<1 )


50+ GHz

Mixed-Signal

& ECL design:

Principles &

Examples


High Speed ECL Design

Followers associated with inputs, not outputs Emitters never drive long wires. (instability with capacitive load)

Double termination for least ringing, send or receive termination for moderate-length lines, high-Z loading saves power but kills speed.

Current mirror biasing is more compact. Mirror capacitance→ ringing, instability. Resistors provide follower damping.


High Speed ECL Design

Layout: short signal paths at gate centers, bias sources surround core. Inverted thin film microstrip wiring.

Example: 8:1 205 GHz static divider in 256 nm InP HBT.

Key: transistors in on-state operate at Kirk limited-current. → minimizes Ccb/Ic delay.

205 GHz divider, Griffith et al, IEEE CSIC, Oct. 2010

Key: transistors designed for minimum ECL gate delay*, not peak (f, fmax). *hand expression, charge-control analysis


mm-wave Op-Amps for Linear Microwave Amplification

0

10

20

30

40

50

108

109

1010

1011

Feedback F

acto

r, d

B

Frequency, Hz

bandwidth loop

increasing

Even for 2 GHz operation,

loop bandwidths must 20-40 GHz.

need very fast transistors

physically small feedback loop;

bias components surround active core.

Griffith et al, IEEE IMS, June. 2011

input power, dBm

ou

tpu

t po

wer

, dB

m

linear response

2-tone intermodulation

increasing feedback

Reduce distortion with strong negative feedback

R. Eden


mm-wave Op-Amps for Linear Microwave Amplification

Virtual-ground input stage, Miller feedback

around output stage, makes feedback

insensitive to generator & load impedances.

current-mode analog design

...node impedances kept low

with transimpedance loading

→ high bandwidth

Zt-stage and loop nesting for high gain

even with fast resistor-loaded circuits

...critical for stability in a 50 GHz loop !

(what will the op-amp be connected to ?)

Griffith et al, IEEE IMS, June. 2011


mm-wave Op-Amps for Linear Microwave Amplification Griffith et al, IEEE IMS, June. 2011 Griffith et al, IEEE IPRM, May. 2008


40 GSample/s Sample/Hold *Design*

master-slave track-hold target 40 GS/s, 6 b (??) 256 nm InP HBT

Saeid Daneshgar

Bias and transmission-line design strongly follows controlled-impedance ECL examples.

layout: ECL buffer. layout: TASTIS.

ECL

ECL TASTIS

ECL


RF-IC design

Principles &

Examples


RF-IC Design: Simple & Well-Known Procedures

1: (over)stabilize at the design frequency

guided by stability circles

3: Tune remaining port for maximum gain

2: Tune input for Fmin (LNAs) or output for Psat (PAs)

4: Add out-of-band stabilization.

There are many ways to tune port impedances: microstrip lines, MIM capacitors, transformers

Choice guided by tuning losses. No particular preferences.

0

5

10

15

20

25

30

10 100 1000

MS

G/M

AG

, dB

Frequency, GHz

Common base

Common Collector

Common emitter

U

For BJT's, MAG/MSG usually highest for common-base.

→ preferred topology.

Common-base gain is however reduced by:

base (layout) inductance

emitter-collector layout capacitance.


parasitic C's and R's represented

by external elements...

Power Amplifier Design (Cripps method)

0

20

40

60

80

100

0 1 2 3 4 5 6 7 8

Curr

ent, m

A

Vce

or Vds

(V)

breakdown

100 mW

200 mW

maxminmaxmax 81 IVVP For maximum saturated output power,

& maximum efficiency

device intrinsic output must see

optimum loadline set by:

breakdown, maximum current, maximum power density.

ammeter monitors intrinsic

junction current

without including

capacitive currents

...(Vcollector-Vemitter )

measures voltage

internal to series parasitic

resistances...


3-stage 150-GHz Amplifier; IBM 65 nm CMOS

-20

-15

-10

-5

0

5

10

140 150 160 170 180 190 200

Frequency (GHz)

S21(meas)

S21(sim)

S21 (measured using power sensor)

S11 (meas)

S11 (sim)

S22 (meas)

S22 (sim)

Frequency (GHz)

S21

S22

S11 (meas)

S11 (sim)

-20

-15

-10

-5

0

5

10

140 150 160 170 180 190 200

Frequency (GHz)

S21(meas)

S21(sim)

S21 (measured using power sensor)

S11 (meas)

S11 (sim)

S22 (meas)

S22 (sim)

140 160 180Frequency (GHz)

K-factor

0

1

2

3


Stability

factor (K)


K-factor

0

1

2

3


Stability

factor (K)

S-p

ara

me

ter

(dB

)

-15

-10

-5

0

5

10

-20 -15 -10 -5 0 5

Input power (dBm)

Ou

tpu

t p

ow

er

(dB

m)

0

5

10

15

20

25

Po

wer

Ad

ded

Eff

icie

ncy (

%)

153 GHz

153 GHz

158.4 GHz

158.4 GHz

153 GHz

158.4 GHz

Outp

ut po

we

r (d

Bm

), G

ain

(d

B)

Input power (dBm)

Po

we

r A

dde

d E

ffic

iency (

%)

PAE

Pout

Gain

-15

-10

-5

0

5

10

-20 -15 -10 -5 0 5

Input power (dBm)

Ou

tpu

t p

ow

er (

dB

m)

0

5

10

15

20

25P

ow

er A

dd

ed E

ffic

ien

cy (

%)

153 GHz

153 GHz

158.4 GHz

158.4 GHz

153 GHz

158.4 GHz

153.0GHz

158.4GHz

-15

-10

-5

0

5

10

-20 -15 -10 -5 0 5

Input power (dBm)

Ou

tpu

t p

ow

er (

dB

m)

0

5

10

15

20

25P

ow

er A

dd

ed E

ffic

ien

cy (

%)

153 GHz

153 GHz

158.4 GHz

158.4 GHz

153 GHz

158.4 GHz

153.0GHz

158.4GHz

Acknowledgement: IBM

M. Seo, B. Jagannathan, J. Pekarik, M. Rodwell, IEEE JSSCC, Dec. 2009

Dummy-prefilled microstrip lines


220 GHz, 48 mW HBT Power Amplifier

4-cell design: Psat >48 mW @ 220 GHz

schematic of single cell

T. Reed et al, IEEE CSIC, Oct. 2011, to be presented.

8-cell design: not yet fully tested: Psat = ?

Technology: Teledyne 250 nm InP HBT Right-side-up thin-film microstrip wiring. Breaks in ground plane minimized.


High Frequency Bipolar IC Design

Digital, mixed-signal, RF-IC (tuned) IC designs----at very high frequencies

Even at 670 GHz, design procedures differ little from that at lower frequencies: classic IC design extends readily to the far-infrared.

Key considerations: Tuned ("RF") ICs Rigorous E&M modeling of all interconnects & passive elements Continuous ground plane → required for predicable interconnect models. Higher frequencies→ close conductor planes→ higher loss, lower current

Key considerations: digital & mixed-signal : Transmission-line modeling of all interconnects Continuous ground plane → required for predicable interconnect models. Unterminated lines within blocks; terminated lines interconnecting blocks. Analog & digital blocks design to naturally interface to 50 or 75.

Next: TMIC designs for 340 GHz, 670 GHz transceivers.

Documents

100-1000 GHz Bipolar ICs: Device and Circuit Design Principles · Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright 100-1000 GHz Bipolar ICs: Device and Circuit Design