1

Virtual Memory

• Main memory can act as a cache for the secondary storage (disk)

• Advantages:– illusion of having more physical memory– program relocation – protection

Physical addresses

Disk addresses

Virtual addresses

Address translation

Virtual address Physical address

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Q1: Where can a page be placed in main memory.

A1: Anywhere with minor restrictions. This means that the placement is fully associative. Recall that a fully associative cache is the most desirable; however, it is also the most difficult to implement. The ratio of miss to hit times for cache is less that 10. For virtual memory it is probably grater than 10,000. Hence, the placement scheme can be implemented by the operating system and can be more complex than a fast hardware placement scheme.

 Q2: How is data found?

A2: Virtual address is translated to a Physical address.

 Q3: Which page should be replaced?

A3: LRU

Q4: What happens on a write?

A4: Write back (Virtual page is updated only when page in physical memory is replaced). Write through is too expensive in time since this would involve updating page in both physical and virtual memory.

 

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Pages: virtual memory blocks

• Page faults: the data is not in memory, retrieve it from disk

– huge miss penalty, thus pages should be fairly large (e.g., 4KB)

– reducing page faults is important (LRU is worth the price)

– can handle the faults in software instead of hardware

– using write-through is too expensive so we use writeback

3 2 1 011 10 9 815 14 13 1231 30 29 28 27

Page offsetVirtual page number

Virtual address

3 2 1 011 10 9 815 14 13 1229 28 27

Page offsetPhysical page number

Physical address

Translation

Page size = 212 = 4 KB, Number of pages in memory = 229-11 = 218 250K. 4K x 250K 1 GB

Virtual address space = 232 = 4 GB

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Page Tables

Physical memory

Disk storage

Valid

1

1

1

1

0

1

1

0

1

1

0

1

Page table

Virtual pagenumber

Physical page ordisk address

Virtual page #

5

Page Tables

Page offsetVirtual page number

Virtual address

Page offsetPhysical page number

Physical address

Physical page numberValid

If 0 then page is notpresent in memory

Page table register

Page table

20 12

18

31 30 29 28 27 15 14 13 12 11 10 9 8 3 2 1 0

29 28 27 15 14 13 12 11 10 9 8 3 2 1 0

Register in processor.

Page table in main memory.

Physical address

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Example: Let page size be 4K bytes i.e. 12 bits of address.

Let the virtual and physical address be 32 bits.

232/212 = 220 pages. 32 bits or 4 bytes would be used in each page entry (but not all bits are needed). Therefore, 222 bytes of main memory would be required for the page table!

Let’s look at one of the ways Intel addressed this problem.

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        One of the many modes available in the Intel IA-32 architecture. 220 pages or 232 = 4 Gbytes. Can be extended to support 36-bit address.        The Directory Entry and Page-Table Entry are 32 bits = 4 bytes.o       Only the upper 20 bits are required to specify the page address.o       The lower 12 bits are available for statistical control information. Such as         Present – Page is present. Same as our Valid bit.          Dirty – Indicating that the page has been written to and will have to be written back to disk.         Accessed – Indicating that the page has been accessed. The operating system will occasionally read and reset these bits to gather information to determine which pages should be used for replacement. etc.

Note that Page directory and each page table are also pages. Unused pages can reside on hard disk.

4 KB4 KB

8

Making Address Translation Fast• A cache for address translations: translation lookaside buffer

Valid

1

1

1

1

0

1

1

0

1

1

0

1

Page table

Physical pageaddressValid

TLB

1

1

1

1

0

1

TagVirtual page

number

Physical pageor disk address

Physical memory

Disk storage

        The TLB is a special cache (internal to the processor).

        Stores recent virtual to physical address translations.

        Holds only page table mappings.

        Tag part contains high bits of virtual address.

Data part contains high order physical address bits to specify page physical address

9

10

TLBs and caches

Yes

Deliver datato the CPU

Write?

Try to read datafrom cache

Write data into cache,update the tag, and put

the data and the addressinto the write buffer

Cache hit?Cache miss stall

TLB hit?

TLB access

Virtual address

TLB missexception

No

YesNo

YesNo

Write accessbit on?

YesNo

Write protectionexception

Physical address

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Modern Systems

• Very complicated memory systems:Characteristic Intel Pentium Pro PowerPC 604

Virtual address 32 bits 52 bitsPhysical address 32 bits 32 bitsPage size 4 KB, 4 MB 4 KB, selectable, and 256 MBTLB organization A TLB for instructions and a TLB for data A TLB for instructions and a TLB for data

Both four-way set associative Both two-way set associativePseudo-LRU replacement LRU replacementInstruction TLB: 32 entries Instruction TLB: 128 entriesData TLB: 64 entries Data TLB: 128 entriesTLB misses handled in hardware TLB misses handled in hardware

Characteristic Intel Pentium Pro PowerPC 604Cache organization Split instruction and data caches Split intruction and data cachesCache size 8 KB each for instructions/data 16 KB each for instructions/dataCache associativity Four-way set associative Four-way set associativeReplacement Approximated LRU replacement LRU replacementBlock size 32 bytes 32 bytesWrite policy Write-back Write-back or write-through

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13

14

15

• Processor speeds continue to increase very fast— much faster than either DRAM or disk access times

• Design challenge: dealing with this growing disparity

• Trends:

– synchronous SRAMs (provide a burst of data)

– redesign DRAM chips to provide higher bandwidth or processing

– restructure code to increase locality

– use prefetching (make cache visible to ISA)

Some Issues