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Pulsar firmware statusMarch 12th, 2004

Overall firmware status

Pulsar Slink formatter

Slink merger

Muon

Reces

SVT

L2toTS

Transmitters

How to keep firmware versions in order

Sakari Pitkänen, Tomi Mansikkala

2

PC

SLINK

Pulsar pre-processors

L1 muon

L1 XTRPL1 trigger

TS

L2 CAL(CLIST/Iso)

PreFred

ShowMax

(RECES)

SVT

Muon

Cluster

Electron

Merger

Merger

SVT

T2toTS

Overall firmware status

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Pulsar Slink formatter

• Slink flow control• Handles Slink flow control (link full, link down, user reset)• Creates control words (Beginning Of Fragment, End Of Fragment)

• Pulsar Slink frame format• Creates Header and Trailer

• Internal Spy FIFO• Saves all data words• Saves Slink control signals and formatter status for each word sent out• Can be read and enabled through VME

• Data word counter• Counts number of data words, stamp in the trailer

• Send empty package on demand (useful if upstream is unavailable) • Can send out an empty package (no data words, only Header and Trailer)

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Slink merger

DataIO FPGA 1

DataIO FPGA 2

Control FPGAP3

• Receives data from four Slink mezzanine cards• Saves data to input DAQ buffers• Merges data and checks mismatch errors and stamps in the trailer• Creates one Slink package for merged data• Saves Slink formatted data to output DAQ buffers• Sends data out from P3 - AUX card - Slink

AUXCard

SlinkLSC

SlinkLSC

Slink LDC

Slink LDC

Slink LDC

Slink LDC

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Buffer 0

Buffer 1

Buffer 2

Buffer 3

Slink merger

Slinkformatter

Slink dataflowSlink input FIFO Output FIFO

Input DAQ RAM

DataIO FPGA 1

Buffer 0

Buffer 1

Buffer 2

Buffer 3

Slink input FIFO Output FIFOInput DAQ RAM

Buffer 0

Control FPGA

Merger

Buffer 1

Buffer 2

Buffer 3

Merger

DataIO 1 input FIFO

DataIO 2 input FIFO

Output FIFO

Output DAQ RAM

…

…

…

…

…

…

…

L1A FIFO

L1A FIFO

L1A FIFO

Buffer 0

Buffer 1

Buffer 2

Buffer 3

Slink input FIFO Output FIFOInput DAQ RAM

DataIO FPGA 2

Buffer 0

Buffer 1

Buffer 2

Buffer 3

Slink input FIFO Output FIFOInput DAQ RAM

Merger

…

…

…

…

L1A FIFO

L1A FIFO

B#

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Slink mergerPulsar Slink frame format

Merger header

Merger trailer

Input 1 header

Input 1 trailer

Input 2 header

Input 2 trailer

Input 3 header

Input 3 trailer

Input 4 header

Input 4 trailer

Slink input 1

data

Slink input 2

data

Slink input 3

data

Slink input 4

data

• Merger creates it’s own header and trailer

• Data is not modified just merged (Headers and trailers are kept)

Now lower 8 bits for Bunch counter

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Muon

HotlinkRX

HotlinkRX

HotlinkRX

HotlinkRX

DataIO FPGA 1

DataIO FPGA 2

Control FPGA

AUXCard

SlinkLSC

P3

L1T input

SlinkLSC

• Receives data from four Hotlink mezzanine cards, XTRP input and L1 trigger input• Saves data to input DAQ buffers• Zero suppresses Muon data• Merges data and saves it to output DAQ buffer• Creates one Slink package for merged data• Sends data out from P3 - AUX card - Slink

XTRP input

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Reces

TaxiRX

TaxiRX

TaxiRX

TaxiRX

DataIO FPGA 1

DataIO FPGA 2

Control FPGA

AUXCard

P3

SlinkLSC

SlinkLSC

• Receives data from four Taxi mezzanine cards• Saves data to input DAQ buffers• Zero suppresses Reces data (Phase I: no zero suppresion)• Merges data• Creates one Slink package for merged data• Saves Slink formatted data to output DAQ buffer• Sends data out from P3 - AUX card - Slink

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SVT

Control FPGA

AUXCard

SlinkLSC

P3

SlinkLSC

• Receives SVT data• Saves data to input DAQ buffer• Creates one Slink fragment for SVT data needed for L2 algorithm• Saves Slink formatted data to output DAQ buffer• Sends data out from P3 - AUX card - Slink

SVT input

10

L2toTS

Control FPGA

TS

CDF control signalsL1ABuffer numberL2A

L2R

• Waits for L1A and data from L1 trigger input or CPU decision• Adjustable delay for L2 decision to TS • Sends L2A or L2R to TS• Finish handshake with TS and rearm for next event

For “sparky” trigger (Teststand use)

L1T input

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Transmitter firmwaresGeneral transmitter

• Divided to four buffers• Each output channel has its own RAM• Four control bits

Latency(delay before first word sent out)

Output FIFOOutput interface

• Output interface varies between different transmitter firmwares

(Hotlink, Taxi)

Gap (delay between data words)

Empty event

End of event

…

• After L1A a statemachine starts to transfer data from RAM to FIFO

…

RAM

Data bits(In case of Gap or Latency word, used fordelay value)

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How to keep firmware versions in order

• One directory for files to configure FPGAs; another for archiving stable versions• Pulsar firmware configuration keeps all development versions and latest stable version• Pulsar firmware archive keeps all stable versions

• Files kept• VHDL source code• Files necessary for recreating this version• Readme with revision history• FPGA configuration files the FPGAs

• Source code under CVS control

File structure

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Procedure now carefully followed for every new version

How to keep firmware versions in orderNew version procedure