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Monolithic Pixel Sensor in SOI Technology - First Test Results

H. Niemiec, M. Koziel, T. Klatka, W. Kucewicz, S. Kuta, W. Machowski, M. SaporUniversity of Mining and Metallurgy, Krakow

K. Domanski, P. Grabiec, M. Grodner, B. Jaroszewicz, A. Kociubinski, K. Kucharski, J. Marczewski, D. Tomaszewski

Institute of Electron Technology, Warszawa

M. Caccia University of Insubria, Como

Presented by Halina Niemiec

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At Prague

The concept of SOI active pixel sensor realized in wafer-bonded SOI substrate was presented

The technology development: technological challenges, test structures and experiments were described

Detector handle wafer

High resistive 300 m thick

Electronics active layer

Low resistive 1.5 m thick

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Progress of the project

Fabrication of SOI test structure (TS - SOI) was completed

First run – only standard CMOS devices produced

Second run – cavities for pixel junction created

Prototype readout circuits in commercial technology were delivered

First measurements of TS-SOI and prototype chips performed

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SOI Test StructuresTS-SOI chip

General technological test structures for parameters extraction, investigation of device mismatches, process control, reliability test

Examples of analogue and digital circuits for comparison simulation and measurements results

Specific test structures for SOI detector applicationsFirst two runs were performed

on low resistive SOI substrates and no pixel junctions were produced.

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TS-SOI – Results

Reliability test structures

Chain of contact windows to the detectors

Metal1 serpentine over deep detector cavities

The measurements indicated continuous

electrical paths

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TS-SOI – Results

Examples of measured MOS characteristics

-1,25E-04

-1,00E-04

-7,50E-05

-5,00E-05

-2,50E-05

0,00E+00

-5,00 -4,00 -3,00 -2,00 -1,00 0,00VGS [V]

ID

[A]

Vds=-0.3V

Vds=-4.5V-9,00E-05

-7,50E-05

-6,00E-05

-4,50E-05

-3,00E-05

-1,50E-05

0,00E+00

-5,00 -4,00 -3,00 -2,00 -1,00 0,00VDS [V]

ID

[A]

Vgs=-1.3V

Vgs=-4.3V

0,00E+00

7,00E-05

1,40E-04

2,10E-04

2,80E-04

3,50E-04

4,20E-04

0,00 1,00 2,00 3,00 4,00 5,00VGS [V]

ID [

A]

Vds=0.3V

Vds=4.5V

0,00E+00

5,00E-05

1,00E-04

1,50E-04

2,00E-04

2,50E-04

3,00E-04

0,00 1,00 2,00 3,00 4,00 5,00

VDS [V]

ID [

A]

Vgs=1.3V

Vgs=4.3V

PMOSW/L=20m/

10m

NMOSW/L=20m/

10m

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TS-SOI – Results

Measurements of test structure consisting of

current mirrors with exactly the same dimensions –

neighbouring and distant devices investigated

Technological mismatch studies

Iinj Iout1

nj

Iout2 Ioutn Ioutn Ioutn-1

1 2 3 4

6 7 8 9 10 5

13 14 15 16 17 12 18 11

21 22 23 24 25 20 26 19 27

31 32 33 34 35 30 36 29 37 28

41 42 43 44 45 40 46 39 47 38

51 52 53 54 55 50 56 49 57 48

60 61 62 63 64 59 65 58

67 68 69 70 71 66 72

73 74 75 76

Detailed measurements performed for left side of a wafer with 1.5 m

thick active layer

Left and right side of the wafer differs by implantation dose.

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0,8

0,9

0,9

1,0

1,0

1,1

1,1

1,2

1,2

str5 str12 str20 str21 str29 str30 str31 str40 str41 str49 str50 str51 str60

Measured v alue/Avarage v alue

Input current = 10 uA

`

0,0E+00

2,0E+05

4,0E+05

6,0E+05

8,0E+05

1,0E+06

1,2E+06

7,50E-06 8,00E-06 8,50E-06 9,00E-06 9,50E-06 1,00E-05 1,05E-05

Current [A]

Avarage current=8.97 uAStddev=373 nA

Max mismatch = 13.9%For neighbours = 7.1%

0,8

0,9

0,9

1,0

1,0

1,1

1,1

1,2

1,2

str5 str12 str20 str21 str29 str30 str31 str40 str41 str49 str50 str51 str60

Measured value/Average value

Input current = 10 uA

TS-SOI – ResultsNMOS transistors

W/L=50m/10 m

W/L=15m/3 m15m/3 m

0,0E+00

1,0E+06

2,0E+06

3,0E+06

4,0E+06

5,0E+06

6,0E+06

7,0E+06

8,0E+06

9,0E+06

4,75E-06 4,81E-06 4,87E-06 4,93E-06 4,99E-06 5,05E-06

Current [A]

Average current=4.91 AStddev=50.4 nA

Max mismatch = 3.2%For neighbours = 1.8%

50m/10 m

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0,8

0,9

0,9

1,0

1,0

1,1

1,1

1,2

1,2

str5 str12 str20 str21 str29 str30 str31 str40 str41 str49 str50 str51 str60

Measured value/Average value

Input current = -10 uA

0,0E+00

1,0E+05

2,0E+05

3,0E+05

4,0E+05

5,0E+05

6,0E+05

7,0E+05

-1,30E-05 -1,20E-05 -1,10E-05 -1,00E-05 -9,00E-06 -8,00E-06Current [A]

Average current=-10.7 A

Stddev=647 nA Max mismatch = 15.9%For neighbours = 9.8%

0,0E+00

1,0E+06

2,0E+06

3,0E+06

4,0E+06

5,0E+06

6,0E+06

7,0E+06

8,0E+06

9,0E+06

1,0E+07

-5,20E-06 -5,10E-06 -5,00E-06 -4,90E-06 -4,80E-06 -4,70E-06 -4,60E-06Current [A]

Average current=-4.92 AStddev=46.1 nA

Max mismatch = 2.4%For neighbours = 1.3 %

0,8

0,9

0,9

1,0

1,0

1,1

1,1

1,2

1,2

str5 str12 str20 str21 str29 str30 str31 str40 str41 str49 str50 str51

Measured value/Average value

Input current = -10 uA

TS-SOI – ResultsPMOS transistors

W/L=50m/10 m

W/L=15m/3 m15m/3 m

50m/10 m

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TS-SOI – Model extraction

Extracted MOS models for first run of TS-SOI: level 1 and level 2. Extraction of level 3 model in progress.

LEVEL=1 LEVEL=2 KP= 2.293E-5 VTO= 0.991 VTO= 0.688 GAMMA= 0.868 GAMMA= 0.633 PHI= 1.241 PHI= 0.969 PB= 0.600 LAMBDA= 0.059 NFS= 1.000E+9 UO= 1.547E+3 UCRIT= 3.242E+4 UEXP= 0.447 LAMBDA= 0.041 VMAX= 1.000E+7 NEFF= 2.048 DELTA= 0.000 0 .0E+0

1.0E-3

2.0E-3

3.0E-3

4.0E-3

5.0E-3

6.0E-3

0 1 2 3 4 5

VDS (V)

I (A)

LEVEL=2

LEVEL=1

Characteristics simulated with level 2 model fit quite well measurements results

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TS-SOI – Results

DC characteristics were measured for digital cells (inverter, double load inverter, double load buffer, NAND and NOR gate) and simple amplifying stages (OS and OS-OG)

Obtained characteristics will be used for device models validation

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TS-SOI – Results

Inverter:VT 2.5 V

Max IVDD=160 A

OS amplifier:Gain -168 V/V @ 3

AGain -102 V/V @ 11

A

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TS-SOI – Next steps

Further works on technological files extraction and device mismatches studies

Measurements of readout matrix (with input pads) in SOI technologies

Production of test structures on high resistive substrates (already in progress) and measurements of complete sensors

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Prototype readout circuits

First prototype of the readout circuit was designed and fabricated in 0.8 AMS technology

Architecture of a readout circuit is being tested before the technological works are finished

Technology properties and the readout circuit operation are investigated separately

Compatibility was obtained by special design techniques:

Re-scaling transistor dimensions to obtain the same gate capacitances and width to length (W/L) ratios like in IET-SOI technology

Using most crucial IET-SOI design rules for the layout – the same drain diffusion areas, the same metal lines widths

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Architecture of prototype chip

Readout pixel

Readout pixel

Readout pixel

Readout pixel

Readout pixel

Readout pixel

Readout pixel

Readout pixel

Readout pixel

Readout pixel

Readout pixel

Readout pixel

Readout pixel

Readout pixel

Readout pixel

Row

_sel

shi

ft re

gist

er

and

res

et lo

gic

Analog Output

Column_sel shift register

Dummy pixel

Control block CLK RST

READ

Cur

ren

t ref

ere

nce

The prototype readout circuit consists of 2 matrices with 256 (16x16) channels. Detecting diode is

replaced by injection capacitance.

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Prototype chip

Row_sel<0>

Column_sel<0>

Column_sel<1>

Column_sel<31>

Reset_rowl<0>

Row_sel<1>

Row_sel<31>

Reset_rowl<1>

Reset_rowl<31>

Sample I-after reset

Sample II-after integration time

Charge integration

Implemented readout technique combines rolling-shutter with CDS

Detector dead time is limited to the reset time of integrating element

Integration time of every channel is adjustable and well defined

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Prototype chip - Results

Transfer characteristic

Output range:1.75 V

Nonlinearity: 5%

0

200

400

600

800

1000

1200

1400

1600

1800

2000

0 500 1000 1500 2000 2500 3000

Vin [mV]

Vo

ut

[m

V]

Measuredcharacteristic

Linear fit

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Prototype chip – Next steps Further validation of

prototype readout circuits Estimation of maximum

readout speed Investigation of possible

parasitic effects, like cross-talk, gradient across the circuit, etc.

Basing on the results of prototype chips measurements the readout circuit in SOI technology will be designed