1 CSE 45432 SUNY New Paltz Chapter 3 Machine Language Instructions

1CSE 45432 SUNY New Paltz

Chapter 3

Machine Language Instructions


Generic Examples of Instruction Format Widths

Variable:

Fixed:

Hybrid:

……

If code size is most important, use variable length instructionsIf code size is most important, use variable length instructions

If performance is most important, use fixed length instructionsIf performance is most important, use fixed length instructions


General Purpose Registers Dominate

1975-1995 all machines use general purpose registersExpect new instruction set architecture to use general purpose register

Advantages of registers• registers are faster than memory• registers are easier for a compiler to use

- e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order vs. stack

• registers can hold variables- memory traffic is reduced, so program is sped up

(since registers are faster than memory)- code density improves (since register named with fewer bits

than memory location)


Addressing Objects: Endianess and Alignment

• Big Endian: address of most significant IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA

• Little Endian: address of least significant Intel 80x86, DEC Vax, DEC Alpha (Windows NT)

msb lsb

3 2 1 0little endian byte 0

0 1 2 3

big endian byte 0

Alignment: require that objects fall on address that is multiple of their size.

0 1 2 3

Aligned

NotAligned


Top 10 80x86 Instructions

Rank Instruction Integer Average Percent total executed

1 load 22%

2 conditional branch 20%

3 compare 16%

4 store 12%

5 add 8%

6 and 6%

7 sub 5%

8 move register-register 4%

9 call 1%

10 return 1%

Total 96%

Simple instructions dominate instruction frequencySimple instructions dominate instruction frequency


Machine Language Instructions:

• More primitive than higher level languages

• Very restrictive

• We’ll be working with the MIPS instruction set architecture

– similar to other architectures developed since the 1980's

– used by NEC, Nintendo, Silicon Graphics, Sony

Design goals: maximize performance and minimize cost, reduce design Design goals: maximize performance and minimize cost, reduce design timetime


MIPS ISA

MIPS assumes 32 CPU registers ($0, …. , $31)• All arithmetic instructions have 3 operands• Operand order is fixed (destination first in assembly instruction)• Operand of arithmetic instructions are in registers• Simple memory addressing mechanism

C code: A = B + C + D;E = F - A;

MIPS code: add $t0, $s1, $s2add $s0, $t0, $s3sub $s4, $s5, $s0

t0, s1, s2, … are symbolic names for registers (translated to the corresponding numbers by the assembler).

Compiler


Register Usage Conventions

Name Register number Usage

$zero 0 the constant value 0$v0-$v1 2-3 values for results and expression evaluation$a0-$a3 4-7 arguments$t0-$t7 8-15 temporaries$s0-$s7 16-23 saved$t8-$t9 24-25 more temporaries$gp 28 global pointer$sp 29 stack pointer$fp 30 frame pointer$ra 31 return address

Registers hold 32 bits of data

Register zero always has the value zero (even if you try to write it)


Memory Organization

• Viewed as a large, single-dimension array, with an address.

• A memory address is an index into the array

• A word in MIPS is 32 bits long (4 bytes)

• "Byte addressing" means that the index points to a byte of memory.

• 232 bytes with byte addresses from 0 to 232-1

• 230 words with byte addresses 0, 4, 8, ... 232-4

• Words are aligned! (the least 2 significant bits of a word address?)

...

0

1

2

3

4

5

6

8 bits of data

8 bits of data

8 bits of data

8 bits of data

8 bits of data

8 bits of data

8 bits of data

0

4

8

12

...

32 bits of data

32 bits of data

32 bits of data

32 bits of data


Load and Store Instructions

• A memory address = content of a register + an immediate constantA memory address = content of a register + an immediate constant

C code: A[8] = h + A[8];

MIPS code: lw $t0, 32($s3) // Load word add $t0, $s2, $t0

sw $t0, 32($s3) // Store word

• The compiler stores the address of the first element of array A in register $s3.• It is assumed that the value of h is stored in register $s2.• Store word has destination last• Remember arithmetic operands are registers, not memory!


Summary so far:

• MIPS— loading words but addressing bytes— arithmetic on registers only

• Instruction Meaning

add $s1, $s2, $s3add $s1, $s2, $s3 $s1 <= $s2 + $s3$s1 <= $s2 + $s3sub $s1, $s2, $s3sub $s1, $s2, $s3 $s1 <= $s2 – $s3$s1 <= $s2 – $s3lw $s1, 100($s2)lw $s1, 100($s2) $s1 <= Memory[$s2+100] $s1 <= Memory[$s2+100] sw $s1, 100($s2)sw $s1, 100($s2) Memory[$s2+100] => $s1Memory[$s2+100] => $s1


Example

swap(int v[], int k);{ int temp;

temp = v[k]v[k] = v[k+1];v[k+1] = temp;

} swap:muli $2, $5, 4add $2, $4, $2lw $15, 0($2)lw $16, 4($2)sw $16, 0($2)sw $15, 4($2)jr $31


• Decision making instructions

– alter the control flow,

– i.e., change the "next" instruction to be executed

• MIPS conditional branch instructions: bne $t0, $t1, Label // branch if $t0 != $t1 beq $t0, $t1, Label // branch if $t0 = $t1

• Example: if (i==j) h = i + j;

bne $s0, $s1, Labeladd $s3, $s0, $s1

Label: ....

Control Instructions


• MIPS unconditional branch instructions:j label

• Example:

if (i!=j) beq $s4, $s5, Lab1 h=i+j; add $s3, $s4, $s5else j Lab2 h=i-j; Lab1: sub $s3, $s4, $s5

Lab2: ...

Control Instructions (Continue)


• We have: beq, bne, what about Branch-if-less-than?

• New instruction:if $s1 < $s2 then

$t0 = 1 slt $t0, $s1, $s2 else

$t0 = 0

• Can use this instruction to build "blt $s1, $s2, Label" — can now build general control structures

• Note that the assembler needs a register to do this,— there are policy of use conventions for registers

Control Instructions (Continue)


• Instructions, like registers and words of data, are also 32 bits long• R-type instruction format:

– Example: add $t0, $s1, $s2– registers have numbers, $t0=8, $s1=17, $s2=18

000000 10001 10010 01000 00000 100000

op rs rt rd shamt funct

• I-type instruction format:

– Example: lw $t0, 32($s2)

35 18 9 32

op rs rt 16 bit number

Machine Language

Source register Destination register Op-code extension


Overview of MIPS

• Simple instructions all 32 bits wide• Very structured, no unnecessary baggage• Only three instruction formats

• In branch instructions, address is relative to PC (next instruction)bne $t4,$t5,Label==> PC = (PC+4) + Label if $t4 = = $t5

• In jump instructions, address is relative to the 4 high order bits of PC– Address boundaries of 256 MB.

• Pseudo Instructions are assembly instructions that are translated by the assembler into one or more MIPS instructions– Example: MOV $t0, $t1 ==> add $t0, $t1, $0

op rs rt rd shamt funct

op rs rt 16 bit address

op 26 bit address

R

I

J


Byte Halfword Word

Registers

Memory

Memory

Word

Memory

Word

Register

Register

1. Immediate addressing

2. Register addressing

3. Base addressing

4. PC-relative addressing

5. Pseudodirect addressing

op rs rt

op rs rt

op rs rt

op

op

rs rt

Address

Address

Address

rd . . . funct

Immediate

PC

PC

+

+

MIPS 5 Addressing Modes


• Immediate instructions (2nd operand is a constant):

addi $29, $29, 4 // Add Immediate slti $8, $18, 10 // Set Less Than Immediate andi $29, $29, 6 // AND Immediate ori $29, $29, 4 // OR Immediate

• To load a 32 bit constant into a register, load each 16 bit separatel lui $t0, 1010101010101010 //First: "load upper immediate"

Then must get the lower order bits right, i.e.,ori $t0, $t0, 1010101010101010 // OR immediate

Constants

1010101010101010 0000000000000000

0000000000000000 1010101010101010

1010101010101010 1010101010101010

1010101010101010 0000000000000000 filled with zeros

OR


To summarize:MIPS operands

Name Example Comments

$s0-$s7, $t0-$t9, $zero, Fast locations for data. In MIPS, data must be in registers to perform 32 registers $a0-$a3, $v0-$v1, $gp, arithmetic. MIPS register $zero always equals 0. Register $at is

$fp, $sp, $ra, $at reserved for the assembler to handle large constants.Memory[0], Accessed only by data transfer instructions. MIPS uses byte addresses, so

230 memory Memory[4], ..., sequential words differ by 4. Memory holds data structures, such as arrays,words Memory[4294967292] and spilled registers, such as those saved on procedure calls.

MIPS assembly languageCategory Instruction Example Meaning Comments

add add $s1, $s2, $s3 $s1 <= $s2 + $s3 Three operands; data in registers

Arithmetic subtract sub $s1, $s2, $s3 $s1 <= $s2 - $s3 Three operands; data in registers

add immediate addi $s1, $s2, 100 $s1 <= $s2 + 100 Used to add constantsload word lw $s1, 100($s2) $s1 <= Memory[$s2 + 100] Word from memory to registerstore word sw $s1, 100($s2) Memory[$s2 + 100] <D1= $s1Word from register to memory

Data transfer load byte lb $s1, 100($s2) $s1 <= Memory[$s2 + 100] Byte from memory to registerstore byte sb $s1, 100($s2) Memory[$s2 + 100] <= $s1 Byte from register to memoryload upper immediate

lui $s1, 100 $s1 <= 100 * 216 Loads constant in upper 16 bits

branch on equal beq $s1, $s2, 25 if ($s1 == $s2) go to PC + 4 + 100

Equal test; PC-relative branch

Conditionalbranch on not equal bne $s1, $s2, 25 if ($s1 != $s2) go to

PC + 4 + 100Not equal test; PC-relative

branch set on less than slt $s1, $s2, $s3 if ($s2 < $s3) $s1 = 1; else $s1 = 0

Compare less than; for beq, bne

set less than immediate

slti $s1, $s2, 100 if ($s2 < 100) $s1 = 1; else $s1 = 0

Compare less than constant

jump j 2500 go to 10000 Jump to target addressUncondi- jump register jr $ra go to $ra For switch, procedure returntional jump jump and link jal 2500 $ra = PC + 4; go to 10000 For procedure call


• We've focused on architectural issues– basics of MIPS assembly language and machine code– we’ll build a processor to execute these instructions.

• Design alternative:

– provide more powerful operations

– goal is to reduce number of instructions executed

– danger is a slower cycle time and/or a higher CPI

• Sometimes referred to as “RISC vs. CISC”

– virtually all new instruction sets since 1982 have been RISC

– VAX: minimize code size, make assembly language easy

instructions from 1 to 54 bytes long!

• We’ll look at PowerPC and 80x86

Alternative Architectures


PowerPC

• Indexed addressing– example: lw $t1,$a0+$s3 // $t1=Memory[$a0+$s3]– What do we have to do in MIPS?

• Update addressing– update a register as part of load (for marching through arrays)– example: lwu $t0,4($s3) // $t0=Memory[$s3+4];$s3=$s3+4– What do we have to do in MIPS?

• Others:– load multiple/store multiple– a special counter register “bc Loop”

decrement counter, if not 0 goto loop


80x86

• 1978: The Intel 8086 is announced (16 bit architecture)

• 1980: The 8087 floating point coprocessor is added

• 1982: The 80286 increases address space to 24 bits, +instructions

• 1985: The 80386 extends to 32 bits, new addressing modes

• 1989-1995: The 80486, Pentium, Pentium Pro add a few instructions(mostly designed for higher performance)

• 1997: MMX is added

“This history illustrates the impact of the “golden handcuffs” of compatibility

“adding new features as someone might add clothing to a packed bag”

“an architecture that is difficult to explain and impossible to love”


A dominant architecture: 80x86

• Complexity:– Instructions from 1 to 17 bytes long– one operand must act as both a source and destination– one operand can come from memory– complex addressing modes

e.g., “base or scaled index with 8 or 32 bit displacement”• Saving grace:

– the most frequently used instructions are not too difficult to build– compilers avoid the portions of the architecture that are slow

“what the 80x86 lacks in style is made up in quantity, making it beautiful from the right perspective”


• Instruction complexity is only one variableInstruction complexity is only one variable

– lower instruction count vs. higher CPI / lower clock ratelower instruction count vs. higher CPI / lower clock rate

• Design Principles:Design Principles:

1 Simplicity favors regularitySimplicity favors regularity

2 Smaller is fasterSmaller is faster

3 Good design demands compromiseGood design demands compromise

4 Make the common case fastMake the common case fast

• Instruction set architectureInstruction set architecture

– a very important abstraction indeed!a very important abstraction indeed!

Fallacy: Fallacy: Most powerful instructions mean higher performanceMost powerful instructions mean higher performance

Repeat Prefix (REP) in 80X86Repeat Prefix (REP) in 80X86

FallacyFallacy: Write in assembly language to obtain the highest performance: Write in assembly language to obtain the highest performance

Summary


0 zero constant 0

1 at reserved for assembler

2 v0 expression evaluation &

3 v1 function results

4 a0 arguments

5 a1

6 a2

7 a3

8 t0 temporary: caller saves

. . . (callee can clobber)

15 t7

MIPS: Software conventions for Registers

16 s0 callee saves

. . . (caller can clobber)

23 s7

24 t8 temporary (cont’d)

25 t9

26 k0 reserved for OS kernel

27 k1

28 gp Pointer to global area

29 sp Stack pointer

30 fp frame pointer

31 ra Return Address (HW)

Plus a 3-deep stack of mode bits.

Documents

1 CSE 45432 SUNY New Paltz Chapter 3 Machine Language Instructions