38
1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

  • View
    216

  • Download
    0

Embed Size (px)

Citation preview

Page 1: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

1

CS 140L Lecture 1

CK Cheng

CSE Dept.

UC San Diego

Page 2: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

2

Outlines

• Administration

• Lab. Overall View

• FPGA Architecture

• Transistors

• Gates

Page 3: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

3

Administration

Web site:

http://www.cse.ucsd.edu/classes/sp09/cse140L/

WebBoard:

http://webboard.ucsd.edu

Page 4: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

4

Administration

Instructor: CK Cheng, CSE2130, [email protected], 858 534-6184

Teaching Assistants:

• Thomas Weng, [email protected]

• Renshen Wang, [email protected]

• Chengmo Yang, [email protected]

• Mingjing Chen, [email protected]

Page 5: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

5

Administration

Schedule

• Lecture: 2:00-2:50PM, W, Center 212.

• Discussion: 3:00-3:50PM, W, Center 212.

• Office hours: 10:30-11:30AM, TTh, CSE 2130.

Page 6: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

6

Administration

Textbook

• Digital Design and Computer Architecture, David Money Harris and Sarah L. Harris, published by Morgan Kaufmann, 2007.

Hardware

• Altera DE1 Education Kit

Page 7: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

Administration

Labs (68%): computer simulations, board demonstration, report write-up. One report per group.

• 1. Combinational Circuit Designs

• 2. The Specification and Usage of Flip-Flops

• 3. Finite State Machines

• 4. System Design using Datapath and Control Subsystems

Final (30%): 3:00-4:30PM F6/127

Page 8: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

8

Behavior description C, System C, Verilog, VHDL

Register Transfer Level Verilog, VHDL

Netlist of Logic

Physical Layout

Logic Synthesis

Placement, Routing

Mask Fabrication FPGAs

1. Data Representation 2. Synthesis: Logic, Physical Layout3. Analysis: Functional, Timing Verification

Overall View of Labs

Page 9: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

9

FPGAs (Field Programmable Gate Arrays)

Switch MatrixWiring Channels

Programmable Logic Block

Switches

-SRAM based (Flash memory)-Antifuse

Disadvantages: Penalty on area, density, speedAdvantages: Flexibility, low startup costs, low risk, revisions without changing the hardware

Page 10: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

10Copyright © 2007 Elsevier

1-<10>

Transistors: Silicon

Silicon Lattice

Si SiSi

Si SiSi

Si SiSi

As SiSi

Si SiSi

Si SiSi

B SiSi

Si SiSi

Si SiSi

-

+

+

-

Free electron Free hole

n-Type p-Type

• Transistors are built out of silicon, a semiconductor

• Pure silicon is a poor conductor (no free charges)

• Doped silicon is a good conductor (free charges)

– n-type (free negative charges, electrons)

– p-type (free positive charges, holes)

Page 11: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

11Copyright © 2007 Elsevier

1-<11>

MOS Transistors

n

p

gatesource drain

substrate

SiO2

nMOS

Polysilicon

n

gate

source drain

• Metal oxide silicon (MOS) transistors:

– Polysilicon (used to be metal) gate

– Oxide (silicon dioxide) insulator

– Doped silicon

Page 12: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

12Copyright © 2007 Elsevier

1-<12>

Transistors: nMOS

n

p

gatesource drain

substrate

n n

p

gatesource drain

substrate

n

GND

GND

VDD

GND

+++++++- - - - - - -

channel

Gate = 0, it is OFF (source and drain are disconnected)

Gate = 1, it is ON (channel between source and drain)

Source= 0 => Drain=0

Source=1 => Drain=0.8 (Poor one)

Page 13: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

1-<13>Copyright © 2007 Elsevier 1-<13>

Transistors: pMOS• pMOS transistor is just the opposite

– ON when Gate = 0• Source =0 => Drain = 0.2 (Poor zero)• Source =1 => Drain = 1

– OFF when Gate = 1

SiO2

n

gatesource drainPolysilicon

p p

gate

source drain

substrate

Page 14: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

14Copyright © 2007 Elsevier

1-<14>

Transistor Function

g

s

d

g = 0

s

d

g = 1

s

d

g

d

s

d

s

d

s

nMOS

pMOS

OFF ON

ON OFF

Page 15: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

15Copyright © 2007 Elsevier

1-<15>

Transistor Function• nMOS transistors pass good 0’s, so connect source

to GND• pMOS transistors pass good 1’s, so connect source

to VDD

pMOSpull-upnetwork

outputinputs

nMOSpull-downnetwork

Page 16: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

1-<16>Copyright © 2007 Elsevier 1-<16>

CMOS Gates: NOT Gate

VDD

A Y

GND

N1

P1

NOT

Y = A

A Y0 11 0

A Y

A P1 N1 Y

0

1

Page 17: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

1-<17>Copyright © 2007 Elsevier 1-<17>

CMOS Gates: NOT Gate

VDD

A Y

GND

N1

P1

NOT

Y = A

A Y0 11 0

A Y

A P1 N1 Y

0 ON OFF 1

1 OFF ON 0

Page 18: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

1-<18>Copyright © 2007 Elsevier 1-<18>

CMOS Gates: NAND Gate

A

B

Y

N2

N1

P2 P1NAND

Y = AB

A B Y0 0 10 1 11 0 11 1 0

AB

Y

A B P1 P2 N1 N2 Y

0 0

0 1

1 0

1 1

Page 19: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

1-<19>Copyright © 2007 Elsevier 1-<19>

CMOS Gates: NAND Gate

A

B

Y

N2

N1

P2 P1NAND

Y = AB

A B Y0 0 10 1 11 0 11 1 0

AB

Y

A B P1 P2 N1 N2 Y

0 0 ON ON OFF OFF 1

0 1 ON OFF OFF ON 1

1 0 OFF ON ON OFF 1

1 1 OFF OFF ON ON 0

Page 20: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

20Copyright © 2007 Elsevier

1-<20>

CMOS Gate Structure

pMOSpull-upnetwork

outputinputs

nMOSpull-downnetwork

Page 21: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

21Copyright © 2007 Elsevier

1-<21>

NOR GateHow do you build a three-input NOR gate?

Page 22: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

22Copyright © 2007 Elsevier

1-<22>

NOR3 GateThree-input NOR gate

B

CY

A

Page 23: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

23Copyright © 2007 Elsevier

1-<23>

Other CMOS GatesHow do you build a two-input AND gate?

Page 24: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

24Copyright © 2007 Elsevier

1-<24>

Other CMOS GatesTwo-input AND gate

AB

Y

Page 25: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

1-<25>Copyright © 2007 Elsevier 1-<25>

Transmission Gates

• nMOS pass 1’s poorly

• pMOS pass 0’s poorly

• Transmission gate is a better switch– passes both 0 and 1 well

• When EN = 1, the switch is ON:– EN = 0 and A is connected to B

• When EN = 0, the switch is OFF:– A is not connected to B

A B

EN

EN

Page 26: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

Copyright © 2007 Elsevier 1-<26>

Noise

• Anything that degrades the signal– E.g., resistance, power supply noise, coupling

to neighboring wires, etc.

• Example: a gate (driver) could output a 5 volt signal but, because of resistance in a long wire, the signal could arrive at the receiver with a degraded value, for example, 4.5 volts

Driver ReceiverNoise

5 V 4.5 V

Page 27: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

Copyright © 2007 Elsevier 1-<27>

The Static Discipline

• Given logically valid inputs, every circuit element must produce logically valid outputs

• Discipline ourselves to use limited ranges of voltages to represent discrete values

Page 28: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

Copyright © 2007 Elsevier

1-<28>

Logic Levels

Driver Receiver

ForbiddenZone

NML

NMH

Input CharacteristicsOutput Characteristics

VO H

VDD

VO L

GND

VIH

VIL

Logic HighInput Range

Logic LowInput Range

Logic HighOutput Range

Logic LowOutput Range

Page 29: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

Copyright © 2007 Elsevier

1-<29>

Noise MarginsDriver Receiver

ForbiddenZone

NML

NMH

Input CharacteristicsOutput Characteristics

VO H

VDD

VO L

GND

VIH

VIL

Logic HighInput Range

Logic LowInput Range

Logic HighOutput Range

Logic LowOutput Range

NMH = VOH – VIH

NML = VIL – VOL

Page 30: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

Copyright © 2007 Elsevier

1-<30>

DC Transfer Characteristics

VDD

V(A)

V(Y)

VOH VDD

VOL

VIL, VIH

0

A Y

VDD

V(A)

V(Y)

VOH

VDD

VOL

VIL VIH

Unity GainPoints

Slope = 1

0VDD / 2

Ideal Buffer: Real Buffer:

NMH = NML = VDD/2 NMH , NML < VDD/2

Page 31: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

Copyright © 2007 Elsevier 1-<31>

DC Transfer Characteristics

ForbiddenZone

NML

NMH

Input CharacteristicsOutput CharacteristicsVDD

VO L

GND

VIHVIL

VO H

A Y

VDD

V(A)

V(Y)

VOH

VDD

VOL

VIL VIH

Unity GainPoints

Slope = 1

0

Page 32: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

Copyright © 2007 Elsevier 1-<32>

VDD Scaling

• Chips in the 1970’s and 1980’s were designed using VDD = 5 V

• As technology improved, VDD dropped– Avoid frying tiny transistors– Save power

• 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 1.0 V, …• Be careful connecting chips with different

supply voltages

Page 33: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

Copyright © 2007 Elsevier 1-<33>

Logic Family Examples

Logic Family VDD VIL VIH VOL VOH

TTL 5 (4.75 - 5.25) 0.8 2.0 0.4 2.4

CMOS 5 (4.5 - 6) 1.35 3.15 0.33 3.84

LVTTL 3.3 (3 - 3.6) 0.8 2.0 0.4 2.4

LVCMOS 3.3 (3 - 3.6) 0.9 1.8 0.36 2.7

Page 34: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

Copyright © 2007 Elsevier

1-<34>

Power Consumption

• Power = Energy consumed per unit time

• Two types of power consumption:– Dynamic power consumption– Static power consumption

Page 35: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

Copyright © 2007 Elsevier

1-<35>

Dynamic Power Consumption

• Power to charge transistor gate capacitances

• The energy required to charge a capacitance, C, to VDD is CVDD

2

• If the circuit is running at frequency f, and all transistors switch (from 1 to 0 or vice versa) at that frequency, the capacitor is charged f/2 times per second (discharging from 1 to 0 is free).

Pdynamic = ½CVDD2f

Page 36: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

Copyright © 2007 Elsevier

1-<36>

Static Power Consumption• Power consumed when no gates are

switching

• It is caused by the quiescent supply current, IDD, also called the leakage current

• Thus, the total static power consumption is:

Pstatic = IDDVDD

Page 37: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

Copyright © 2007 Elsevier

1-<37>

Power Consumption Example

• Estimate the power consumption of a wireless handheld computer– VDD = 1.2 V

– C = 20 nF– f = 1 GHz

– IDD = 20 mA

Page 38: 1 CS 140L Lecture 1 CK Cheng CSE Dept. UC San Diego

Copyright © 2007 Elsevier

1-<38>

Power Consumption Example

• Estimate the power consumption of a wireless handheld computer– VDD = 1.2 V

– C = 20 nF– f = 1 GHz

– IDD = 20 mA

P = ½CVDD2f + IDDVDD

= ½(20 nF)(1.2 V)2(1 GHz) + (20 mA)(1.2 V)

= 14.4 W