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    Quality of Serice Control in High-Speed NetworksH. Jonathan Chao, Xiaolei Guo

    Copyright 2002 John Wiley & Sons, Inc. . .ISBNs 0-471-00397-2 Hardback ; 0-471-22439-1 Electronic

    QUALITY OF SERVICE CONTROLIN HIGH-SPEED NETWORKS

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    QUALITY OF SERVICE CONTROLIN HIGH-SPEED NETWORKS

    H. JONATHAN CHAO

    XIAOLEI GUO

    A Wiley-Interscience Publication

    JOHN WILEY & SONS, INC.

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    CONTENTS

    PREFACE xiii

    1 INTRODUCTION 1

    1.1 Nature of Traffic r 2

    1.2 Network Technologies r 2

    1.2.1 ATM r 2

    .1.2.2 Internet Integrated Services Intserv r 4

    .1.2.3 Internet Differentiated Services Diffserv r 5

    .1.2.4 Multiprotocol Label Switching MPLS r 6

    1.3 QoS Parameters r 7

    1.4 QoS Control Methods r 91.4.1 Admission Control r 9

    1.4.2 Traffic Access Control r 10

    1.4.3 Packet Scheduling r 10

    1.4.4 Packet Fair Queuing Implementation r 11

    1.4.5 Buffer Management r 11

    1.4.6 Flow and Congestion Control r 11

    1.4.7 QoS Routing r 11

    1.5 Summary r 12

    References r 13

    v

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    CONTENTSvi

    2 ADMISSION CONTROL 17

    2.1 Deterministic Bound r 18

    2.2 Probabilistic Bound: Equivalent Bandwidth r 19

    2.2.1 Bernoulli Trials and Binomial Distribution r 20

    2.2.2 Fluid-Flow Approximation r 20

    2.2.3 Gaussian Distribution r 21

    2.2.4 Large-Deviation Approximation r 21

    2.2.5 Poisson Distribution r 22

    2.2.6 Measurement-Based Methods r 22

    2.3 CAC for ATM VBR Services r 23

    2.3.1 Worst-Case Traffic Model and CAC r 23

    2.3.2 Effective Bandwidth r 24

    2.3.3 Lucents CAC r 25

    2.3.4 NECs CAC r 27

    2.3.5 Tagged-Probability-Based CAC r 30

    2.4 CAC for Integrated Services Internet r 43

    2.4.1 Guaranteed Quality of Service r 45

    2.4.2 Controlled-Load Service r 49

    References r 54

    3 TRAFFIC ACCESS CONTROL 61

    3.1 ATM Traffic Contract and Control Algorithms r 62

    3.1.1 Traffic Contract r 62

    3.1.2 PCR Conformance, SCR, and BT r 63

    3.1.3 Cell Delay Variation Tolerance r 63

    3.1.4 Generic Cell Rate Algorithm r 64

    3.2 An ATM Shaping Multiplexer r 66

    3.2.1 Regularity Condition

    Dual Leaky Bucket r 673.2.2 ATM Shaping Multiplexer Algorithm r 70

    3.2.3 Implementation Architecture r 77

    3.2.4 Finite Bits Overflow Problem r 79

    3.2.5 Simulation Study r 86

    3.2.6 Summary r 89

    3.3 An Integrated Packet Shaper r 90

    3.3.1 Basics of a Packet Traffic Shaper r 90

    3.3.2 Integrating Traffic Shaping and WFIScheduling r 95

    3.3.3 A Logical Structure of the WFI Packet Shaper r 96

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    CONTENTS vii

    3.3.4 Implementation of the WFI Packet Shaper r 97

    3.4 Appendix: Bucket Size Determination r 103

    References r 107

    4 PACKET SCHEDULING 109

    4.1 Overview r 109

    4.2 First In, First Out r 111

    4.3 Round-Robin r 147 r 112

    4.4 Stop-and-Go r 113

    4.5 Hierarchical Round-Robin r 115

    4.6 Earliest Due Date r 116

    4.7 Rate-Controlled Static Priority r 117

    4.8 Generalized Processor Sharing r 119

    4.9 Weighted Fair Queuing r 123

    4.10 Virtual Clock r 127

    4.11 Self-Clocked Fair Queuing r 130

    4.12 Worst-case Fair Weighted Fair Queuing r 1324.13 WF 2 Qq r 136

    4.14 Multiple-Node Case r 137

    4.15 Comparison r 139

    4.16 A Core-Stateless Scheduling Algorithm r 140

    4.16.1 Shaped Virtual Clock Algorithm r 141

    4.16.2 Core-Stateless Shaped Virtual ClockAlgorithm r 142

    4.16.3 Encoding Process r 147

    4.16.4 Complexity r 150

    References r 150

    5 PACKET FAIR QUEUING IMPLEMENTATIONS 153

    5.1 Conceptual Framework and Design Issues r 154

    5.2 Sequencer r 156

    5.2.1 Store Cells in Logical Queues r 157

    5.2.2 Sort Priorities Using a Sequencer r 7158

    5.3 Priority Content-Addressable Memory r 163

    5.3.1 Searching by the PCAM Chip r 163

    5.3.2 Block Diagram r 165

    5.3.3 Connecting Multiple PCAM Chips r 168

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    CONTENTSviii

    5.4 RAM-Based Searching Engine r 168

    5.4.1 Hierarchical Searching r 169

    5.4.2 Timestamp Overflow r 172

    5.4.3 Design of the RSE r 173

    5.4.4 RSE Operations r 173

    5.4.5 Write-in Operation r 175

    5.4.6 Reset Operation r 176

    5.4.7 Search Operation r 177

    5.5 General ShaperScheduler r 179

    5.5.1 Slotted Updates of System Virtual Time r 180

    5.5.2 Implementation Architecture r 182

    5.6 Timestamp Aging Problem r 188

    5.7 Summary r 192

    References r 193

    6 BUFFER MANAGEMENT 197

    6.1 A Look at ATM Networks r 1976.1.1 Overview r 198

    6.1.2 Self-Calibrating Pushout r 201

    6.1.3 TCPrIP over ATMUBR r 209

    6.1.4 Dynamic Threshold with Single Loss Priority r 212

    6.2 A Look at the Internet r 213

    6.2.1 Tail Drop r 214

    6.2.2 Drop on Full r 214

    6.2.3 Random Early Detection r 215

    6.2.4 Differential Dropping: RIO r 220

    .6.2.5 Fair Random Early Detection FRED r 223

    .6.2.6 Stabilized Random Early Detection SRED r 224

    .6.2.7 Longest Queue Drop LQD r 226

    6.3 Summary r 231

    References r 232

    7 FLOW AND CONGESTION CONTROL 235

    7.1 Overview r 235

    7.1.1 Window-Based Flow Control r 236

    7.1.2 Rate-Based Flow Control r 238

    7.1.3 Predictive Control Mechanism r 239

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    CONTENTS ix

    7.2 ATM Networks r 240

    7.2.1 ATM Service Categories r 240

    7.2.2 Backlog Balancing Flow Control r 242

    7.2.3 ABR Flow Control r 267

    7.3 TCPrIP Networks r 276

    7.3.1 TCP Overview r 277

    7.3.2 TCP Congestion Control r 2817.3.3 Other TCP Variants r 286

    7.3.4 TCP with Explicit Congestion Notification r 289

    7.4 EASYAnother Rate-Based Flow Control Scheme r 291

    References r 292

    8 QoS ROUTING 299

    8.1 ATM Signaling and Routing r 300

    .8.1.1 User-to-Network UNI Signaling r 301

    8.1.2 PNNI Signaling r 306

    8.2 QoS Routing for Integrated Services Networks r 316

    8.2.1 Selection of Metrics r 316

    8.2.2 Weighted Graph Model r 318

    8.2.3 Path Selection Algorithms r 319

    8.2.4 Computational Complexity r 325

    8.2.5 Further Reading r 326

    References r 326

    9 DIFFERENTIATED SERVICES 329

    9.1 Service Level Agreement and Traffic ConditioningAgreement r 330

    9.1.1 Service Level Agreement r 330

    9.1.2 Traffic Conditioning Agreement r 3319.2 Basic Architecture of Differentiated Services r 332

    9.3 Network Boundary Traffic Classification andConditioning r 334

    9.4 Per-Hop Behaviors and Some ImplementationExamples r 335

    9.4.1 Default Behavior r 336

    9.4.2 Class Selector r 336

    9.4.3 Assured Forwarding r 337

    9.4.4 Expedited Forwarding r 338

    9.4.5 PHB Implementation with Packet Schedulers r 338

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    CONTENTSx

    9.5 Conceptual Model r 340

    9.5.1 Configuration and Management Interface r 341

    9.5.2 Optional QoS Agent Module r 341

    9.5.3 Diffserv Functions at Ingress and EgressInterfaces r 341

    9.5.4 Shaping and Policing r 341

    9.5.5 Traffic Classification r 3429.5.6 Meters r 342

    9.5.7 Action Elements r 342

    9.5.8 Queuing Elements r 343

    9.5.9 Traffic Conditioning Blocks r 344

    References r 344

    10 MULTIPROTOCOL LABEL SWITCHING 347

    10.1 Basic Architecture r 349

    10.1.1 Label and Label Binding r 349

    10.1.2 Label Stack r 25010.1.3 Route Selection r 352

    10.1.4 Penultimate Hop Popping r 352

    10.1.5 LSP Tunnels r 353

    10.1.6 An Example: Hierarchy of LSP Tunnels r 354

    10.1.7 Next-Hop Label Forwarding Entry r 355

    10.2 Label Distribution r 356