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- 1. SWITCHING THEORY AND LOGIC DESIGN Minimizing Boolean Logic BELCY D MATHEWSElectronics and communication Engineering

2. Review Combinational logic Truth Tables vs Boolean Expressions vs Gates Minimal Operators And / Or / Not, NAND, NORNew Friends XOR, EQ, Full AdderBoolean Algebra +, *, ~, assoc, comm, distr., .Manipulating Expressions and Circuits Proofs: Term rewriting & Exhaustive Enumeration Simplifications De Morgans Law DualityCanonical and minimal forms Sum of products Product of sums 3. Review: Relationship Among Representations * Theorem: Any Boolean function that can be expressed as a truth table can be written as an expression in Boolean Algebra using AND, OR, NOT.u n iq u e ?not u n iq u e B o o le a n E x p r e s s io n [c o n v e n ie n t fo r m a n ip u la tio n ]T r u th T a b le? g a te r e p r e s e n ta tio n (s c h e m a tic )not u n iq u e[c lo s e to im p le m e n ta to n ]How do we convert from one to the other? Optimizations? 4. Review: Canonical FormsStandard form for a Boolean expression - unique algebraic expression directly from a true table (TT) description. Two Types: * Sum of Products (SOP) * Product of Sums (POS) Sum of Products (disjunctive normal form, minterm expansion). Example: minterms abc abc abc abc abc abc abc abcabc 000 001 010 011 100 101 110 111f f 01 01 01 10 10 10 10 10One product (and) term for each 1 in f: f = abc + abc + abc +abc +abc f = abc + abc + abc 5. Review: Sum of Products (cont.) Canonical Forms are usually not minimal: Our Example: f = abc + abc + abc + abc +abc (xy + xy = x) = abc + ab + ab = abc + a (xy + x = y + x) = a + bc f = abc + abc + abc = ab + abc = a ( b + bc ) = a ( b + c ) = ab + ac 6. Review: Canonical Forms Product of Sums (conjunctive normal form, maxterm expansion). Example: maxterms a+b+c a+b+c a+b+c a+b+c a+b+c a+b+c a+b+c a+b+cabc 000 001 010 011 100 101 110 111f f 01 01 01 10 10 10 10 10One sum (or) term for each 0 in f: f = (a+b+c)(a+b+c)(a+b+c) f = (a+b+c)(a+b+c)(a+b+c) (a+b+c)(a+b+c)Mapping from SOP to POS (or POS to SOP): Derive truth table then proceed. 7. Incompletely specified functions Example: binary coded decimal increment by 1 A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BCD digits encode decimal digits 0 9 in bit patterns B C D W X 0000 1001 Y Z 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 10 1 1 0 0 1 1 0 0 1 1 0 0 1 11 0 1 0 1 0 1 0 1 0 1 0 1 0 10 0 0 0 0 0 1 1 0 X X X X X X0 0 1 1 1 1 0 0 0 X X X X X X1 1 0 0 1 1 0 0 0 X X X X X X0 1 0 1 0 1 0 1 0 X X X X X Xoff-set of Won-set of W don't care (DC) set of Wthese inputs patterns should never be encountered in practice "don't care" about associated output values, can be exploited in minimization 8. Outline Review De Morgans to transform SofP into simple 2-level forms Uniting Law to reduce SofP N-cube perspective Announcements Karnaugh Maps Examples Reduction Algorithm 9. Putting DeMorgans to work ====DeMorgans Law: (a + b) = a b a + b = (a b)(a b) = a + b (a b) = (a + b)push bubbles or introduce in pairs or remove pairs. 10. Transformation to Simple GatesSum of Products= De MorgansInvolution: x = (x) 11. Implementations of Two-level Logic Sum-of-products AND gates to form product terms (minterms) OR gate to form sum Product-of-sums OR gates to form sum terms (maxterms) AND gates to form product 12. Two-level Logic using NAND Gates Replace minterm AND gates with NAND gates Place compensating inversion at inputs of OR gate 13. Two-level Logic using NAND Gates (contd) OR gate with inverted inputs is a NAND gate de Morgan's: A' + B' = (A B)' Two-level NAND-NAND network Inverted inputs are not counted In a typical circuit, inversion is done once and signal distributed 14. Two-level Logic using NOR Gates Replace maxterm OR gates with NOR gates Place compensating inversion at inputs of AND gate 15. Two-level Logic using NOR Gates (contd) AND gate with inverted inputs is a NOR gate de Morgan's: A' B' = (A + B)' Two-level NOR-NOR network Inverted inputs are not counted In a typical circuit, inversion is done once and signal distributed 16. The Uniting Theorem Key tool to simplification: A (B' + B) = A Essence of simplification of two-level logic Find two element subsets of the ON-set where only one variable changes its value this single F = A'B'+AB' = varying variable can (A'+A)B' = B' be eliminated and a single A B F product term used the same value in both on-set rows to represent both elements B has 001010101110B remainsA has a different value in the two rows A is eliminated 17. Boolean cubes Visual technique for identifying when the uniting theorem can be applied n input variables = n-dimensional "cube 11 01 0 1 1-cube Y Neighbors address differs by one bit flip 2-cube X00X1113-cubeY Z 00010110011111114-cube YX 0000ZW X1000 18. Mapping truth tables onto Boolean cubes Uniting theorem combines two "faces" of a cube into a larger "face" two faces of size 0 (nodes) F Example: A B F combine into a face of size 1(line) 0010101011101101B 00A10A varies within face, B does not this face represents the literal B' ON-set = solid nodes OFF-set = empty nodes DC-set = 'd nodes 19. Three variable example Binary full-adder carry-out logic A 0 0 0 0 1 1 1 1B 0 0 1 1 0 0 1 1Cin 0 1 0 1 0 1 0 1Cout 0 0 0 1 0 1 1 1(A'+A)BCin 111B C 000AB(Cin'+Cin)101 AA(B+B')Cinthe on-set is completely covered by the combination (OR) of the subcubes of lower dimensionality - note that 111 is covered three times Cout = BCin+AB+ACin 20. Higher dimensional cubes Sub-cubes of higher dimension than 2 F(A,B,C) = m(4,5,6,7) 011111 110010 B C 000001 A101 100on-set forms a square i.e., a cube of dimension 2 represents an expression in one variable i.e., 3 dimensions 2 dimensions A is asserted (true) and unchanged B and C vary This subcube represents the literal A 21. m-dimensional cubes in a ndimensional Boolean space In a 3-cube (three variables): 0-cube, i.e., a single node, yields a term in 3 literals 1-cube, i.e., a line of two nodes, yields a term in 2 literals 2-cube, i.e., a plane of four nodes, yields a term in 1 literal 3-cube, i.e., a cube of eight nodes, yields a constant term "1" In general, m-subcube within an n-cube (m < n) yields a term with n m literals 22. Karnaugh maps Flat map of Boolean cube Wraparound at edges Hard to draw and visualize for more than 4 dimensions Virtually impossible for more than 6 dimensions Alternative to truth-tables to help visualize adjacencies Guide to applying the unitingAtheorem B F A 0 1 B On-set elements with only one variable changing value 0 0 1 0 1 1 0 0 are adjacent0unlike the situation1 in a linear truth-table 2 11030101110 23. Karnaugh maps (contd) Numbering scheme based on Graycode e.g., 00, 01, 11, 10 2n values of n bits where each differs from next by A AB 00 bit flip C one 01 11 10 A 0C 106 4 2 Hamiltonian circuit through n-cube 12 8 0 45 1 3 Only a 7single bit changes in code9 forDadjacent map 13 1 5 B cells 15 11 3 7A0C2641375BC2614B1013 = 1101= ABCD 24. Adjacencies in Karnaugh maps Wrap from first to last column Wrap top row to bottom row 011A 000 010 110100C 001 011 111101B111 110010 B C 000001 A101 100 25. Karnaugh map examples F=A 1B100B Cout = f(A,B,C) = m(0,4,6,7)A 0010Cin 0111BA 1C0010011BAB + ACin + BCinAC + BC + ABobtain the complement of the function by covering 0s with subcubes 26. More Karnaugh map examples A 0C0110011G(A,B,C) = AB A 1C0010011F(A,B,C) =m(0,4,5,7) = AC + BCB A 0C1101100BF' simply replace 1's with 0's and vice versa F'(A,B,C) = m(1,2,3,6) = BC + AC 27. K-map: 4-variable interactive quiz F(A,B,C,D) = m(0,2,3,5,6,7,8,10,11,14,15) F= A1010C0 10001111 111111 1DC 0000DA B11111000Bfind the smallest number of the largest possible subcubes to cover the ON-set (fewer terms with fewer inputs per term) 28. Karnaugh map: 4-variable example F(A,B,C,D) = m(0,2,3,5,6,7,8,10,11,14,15) C + ABD + BD F= A1010C0 10001111 111111 1DC 0000DA B11111000Bfind the smallest number of the largest possible subcubes to cover the ON-set (fewer terms with fewer inputs per term) 29. Karnaugh maps: dont cares f(A,B,C,D) = m(1,3,5,7,9) + d(6,12,13) without don't cares AD + BCD f= A 0X01C0 1X111000X00BD 30. Karnaugh maps: dont cares (contd) f(A,B,C,D) = m(1,3,5,7,9) + d(6,12,13) f = A'D + C'D A'D + B'C'D cares f= A 0X01C0 1X111000X00BDwithout don't with don't caresby using don't care as a "1" a 2-cube can be formed rather than a 1-cube to cover this node don't cares can be treated as 1s or 0s depending on which is more advantageous 31. Design example: two-bit comparator A B 0 0 N1 N2A B C DLT EQ GTABCD11block diagram and truth table0011C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1LT 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0EQ 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1GT 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0we'll need a 4-variable Karnaugh map for each of the 3 output functions 32. Design example: two-bit comparator (contd) AA0001C0 00011011100A1C000D0 100001000001C110D101100000010BBBK-map for LTK-map for EQDK-map for GTLT = A' B' D + A' C + B' C D EQ = A'B'C'D' + A'BC'D + ABCD + AB'CD= (A xnor C) (B xnor D)GT = B C' D' + A C' + A B D' Canonical PofS vs minimal?LT and GT are similar (flip A/C and B/D) 33. Design example: two-bit comparator (contd) AB CD two alternative implementations of EQ with and without XOR EQEQXNOR is implemented with at least 3 simple gates 34. Design example: 2x2-bit multiplierA1 A2 B1 B2P1 P2 P4 P8block diagram and truth tableA2 A1 B2 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 0 1 1 1 1 0 0 1 1B1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1P8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1P4 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0P2 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 04-variable K-map for each of the 4 output functionsP1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 35. Design example: 2x2-bit multiplier (contd) A20000B20 00000100000K-map for P8 B1K-map for P4 P4 = A2B2B1' + A2A1'B2P8 = A2A1B2B1B2A20000000000010011A1A1 A200000B201101010110A1B1K-map for P2K-map for P1 P1= A1B1B1P2 = A2'A