Avionics Digital 2016

AE2406 – Avionics Lab Manual

60

BASIC DIGITAL ICS

LOGIC GATES:

a. AND gate:

An AND gate is the physical realization of logical multiplication operation. It is an electronic

circuit which generates an output signal of ‘1’ only if all the input signals are ‘1’.

b. OR gate:

An OR gate is the physical realization of the logical addition operation. It is an electronic circuit

which generates an output signal of ‘1’ if any of the input signal is ‘1’.

c. NOT gate:

A NOT gate is the physical realization of the complementation operation. It is an electronic

circuit which generates an output signal which is the reverse of the input signal. A NOT gate is

also known as an inverter because it inverts the input.

d. NAND gate:

A NAND gate is a complemented AND gate. The output of the NAND gate will be ‘0’ if all the

input signals are ‘1’ and will be ‘1’ if any one of the input signal is ‘0’.

e. NOR gate:

A NOR gate is a complemented OR gate. The output of the OR gate will be ‘1’ if all the inputs

are ‘0’ and will be ‘0’ if any one of the input signal is ‘1’.

f. EX-OR gate:

An Ex-OR gate performs the following Boolean function,

A B = ( A . B’ ) + ( A’ . B )

It is similar to OR gate but excludes the combination of both A and B being equal to one. The

exclusive OR is a function that give an output signal ‘0’ when the two input signals are equal

either ‘0’ or ‘1’.


61

A. AND GATE

LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7408:

CIRCUIT DIAGRAM:

TRUTH TABLE:

S.No INPUT OUTPUT

A B Y = A . B

1. 0 0 0

2. 0 1 0

3. 1 0 0

4. 1 1 1


62

OR GATE

LOGIC DIAGRAM:


CIRCUIT DIAGRAM:

TRUTH TABLE:

S.No INPUT OUTPUT

A B Y = A + B

1. 0 0 0

2. 0 1 1

3. 1 0 1

4. 1 1 1


63

NOT GATE

LOGIC DIAGRAM:


CIRCUIT DIAGRAM:

TRUTH TABLE:

S.No INPUT OUTPUT

A Y = A’

1. 0 1

2. 1 0


64

NAND GATE

LOGIC DIAGRAM:


CIRCUIT DIARAM:

TRUTH TABLE:

S.No INPUT OUTPUT

A B Y = (A. B)’

1. 0 0 1

2. 0 1 1

3. 1 0 1

4. 1 1 0


65

NOR GATE

LOGIC DIAGRAM:


CIRCUIT DIAGRAM:

TRUTH TABLE:

S.No INPUT OUTPUT

A B Y = (A + B)’

1. 0 0 1

2. 0 1 0

3. 1 0 0

4. 1 1 0


66

EX-OR GATE

LOGIC DIAGRAM


CIRCUIT DIAGRAM:

TRUTH TABLE:

S.No INPUT OUTPUT

A B Y = A B

1. 0 0 0

2. 0 1 1

3. 1 0 1

4. 1 1 0


67

Ex. No. 8(A) IMPLEMENTATION OF HALF ADDER & FULL ADDER

OBJECTIVE:

To design and verify the truth table of the Half Adder & Full Adder circuits.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408

3. OR gate IC 7432

4. NOT gate IC 7404

5. EX-OR gate IC 7486

6. Connecting wires As required

THEORY:

The most basic arithmetic operation is the addition of two binary digits. There are four possible

elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 102

The first three operations produce a sum of whose length is one digit, but when the last operation is

performed the sum is two digits. The higher significant bit of this result is called a carry and lower

significant bit is called the sum.

HALF ADDER:

A combinational circuit which performs the addition of two bits is called half adder. The input variables

designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

FULL ADDER:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The

three input bits include two significant bits and a previous carry bit. A full adder circuit can be

implemented with two half adders and one OR gate.


68

HALF ADDER

TRUTH TABLE:

S.No INPUT OUTPUT

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 0 1

DESIGN:

From the truth table the expression for sum and carry bits of the output can be obtained as,

Sum, S = A B

Carry, C = A . B

CIRCUIT DIAGRAM:

FULL ADDER

TRUTH TABLE:

S.No INPUT OUTPUT

A B C SUM CARRY

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1


69

DESIGN:

From the truth table the expression for sum and carry bits of the output can be obtained as,

SUM = A’B’C + A’BC’ + AB’C’ + ABC

CARRY = A’BC + AB’C + ABC’ +ABC

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

SUM

SUM = A’B’C + A’BC’ + AB’C’ + ABC = A B C

CARRY

CARRY = AB + AC + BC


70

CIRCUIT DIAGRAM:

PROCEDURE:

1. Connections are given as per the circuit diagrams.

2. For all the ICs 7th

pin is grounded and 14th

pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Viva-Voce Questions:

1. What is combinational circuit?

2. Name some universal Gates.

3. What is the truth table of NAND gate?

4. Differentiate combinational circuit and sequential circuit.

5. What is Logic gate.

6. Explain the application of experiment.

RESULT:

The design of the half adder and full adder circuits was done and their truth tables were verified.


71

Ex. No.8 (B) IMPLEMENTATION OF HALF SUBTRACTOR &FULL SUBTRACTOR

AIM:

To design and verify the truth table of the Half Subtractor & Full Subtractor circuits.

APPARATUS REQUIRED:



2. AND gate IC 7408

3. OR gate IC 7432

4. NOT gate IC 7404

5. EX-OR gate IC 7486


THEORY:

The arithmetic operation, subtraction of two binary digits has four possible elementary operations,

namely,

0 - 0 = 0

0 - 1 = 1 with 1 borrow

1 - 0 = 1

1 - 1 = 0

In all operations, each subtrahend bit is subtracted from the minuend bit. In case of the second operation

the minuend bit is smaller than the subtrahend bit, hence 1 is borrowed.

HALF SUBTRACTOR:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input

variables designate the minuend and the subtrahend bit, whereas the output variables produce the

difference and borrow bits.

FULL SUBTRACTOR:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The

three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be

implemented with two half subtractors and one OR gate.


72

HALF SUBTRACTOR

TRUTH TABLE:

S.No INPUT OUTPUT

A B DIFF BORR

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

DESIGN:

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A’ . B

CIRCUIT DIAGRAM:


73

FULL SUBTRACTOR

TRUTH TABLE:

S.No INPUT OUTPUT

A B C DIFF BORR

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

DESIGN:

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF= A’B’C + A’BC’ + AB’C’ + ABC

Borrow, BORR = A’BC + AB’C + ABC’ +ABC

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

DIFFERENCE

DIFF = A’B’C + A’BC’ + AB’C’ + ABC = A B C

BORROW


74

BORR = A’B + A’C + BC

CIRCUIT DIAGRAM:

PROCEDURE:





3. Apply the inputs and verify the truth table for the half subtractor and full subtractor circuits.


1. What is the use of Karnaugh Map?

2. Name some basic Gates.

3. What is the logic of XOR gate?

4. What is Flip flop?

5. What is Boolean algebra


RESULT:

The design of the half subtractor and full subtractor circuits was done and their truth tables were verified.


75

Ex. No. 9. DESIGN AND IMPLEMENTATION OF MULTIPLEXER & DEMULTIPLEXER

OBJECTIVE:

To design and verify the truth table of a 4X1 Multiplexer & 1X4 Demultiplexer.

APPARATUS REQUIRED:



2. OR gate IC 7432

3. NOT gate IC 7404

4. AND gate ( three input ) IC 7411


THEORY:

Multiplexer is a digital switch which allows digital information from several sources to be routed onto a

single output line. The basic multiplexer has several data input lines and a single output line. The

selection of a particular input line is controlled by a set of selection lines. Normally, there are 2n input

lines and n selector lines whose bit combinations determine which input is selected. Therefore,

multiplexer is ‘many into one’ and it provides the digital equivalent of an analog selector switch.

A Demultiplexer is a circuit that receives information on a single line and transmits this information on

one of 2n possible output lines. The selection of specific output line is controlled by the values of n

selection lines.


76

4 X 1 MULTIPLEXER

LOGIC SYMBOL:

TRUTH TABLE:

S.No

SELECTION

INPUT OUTPUT

S1 S2 Y

1. 0 0 I0

2. 0 1 I1

3. 1 0 I2

4. 1 1 I3



77

CIRCUIT DIAGRAM:


78

1X4 DEMULTIPLEXER

LOGIC SYMBOL:

TRUTH TABLE:

S.No INPUT OUTPUT

S1 S2 Din Y0 Y1 Y2 Y3

1. 0 0 0 0 0 0 0

2. 0 0 1 1 0 0 0

3. 0 1 0 0 0 0 0

4. 0 1 1 0 1 0 0

5. 1 0 0 0 0 0 0

6. 1 0 1 0 0 1 0

7. 1 1 0 0 0 0 0

8. 1 1 1 0 0 0 1


79

CIRCUIT DIAGRAM:

PROCEDURE:





3. Apply the inputs and verify the truth table for the multiplexer & demultiplexer.


80


1. What is Multiplexer?

2. What is multiplexer?

3. What is the principle of behind MUX?

4. Which circuit called serial to parallel convertor?

5. What is Parallel to serial convertor.


7. Where MUX used in aircraft applications?

RESULT:

The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth tables were

verified.


81

EX.NO. 3. DESIGN AND IMPLEMENTATION OF ENCODERAND DECODER

OBJECTIVE:

To construct and verify the 8 X 3 Encoder and 3x8 Decoder using logic gates.

REQUIREMENTS:

S. No Components / Equipments Specification Quantity

1. Digital IC trainer kit - 1

2. OR Gate IC7432 3

3. Connecting Wires - Sufficient Numbers

Theory:

(i) Encoder: Encoder takes all the data inputs one at a time and converts them to a single

encoded output, it is a multi-input data line, combinational logic circuit that converts the logic level 1

data at its input to an equivalent binary code at its output. Encoder has 2n

input lines with common

types that include 4 to 2,8 to 3 & 16 to 4 line configuration. Encoders are available to encode

either a decimal or hexadecimal input pattern to typically binary or BCD output code.

Decoder: A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into

coded outputs, where the input and output codes are different; e.g. n-to-2n, BCD decoders. Decoding is

necessary in applications such as data multiplexing, 7 segment display and memory address decoding.

Any n-variable logic function, in canonical sum-of- minterms form can be implemented using a single

n-to-2n

decoder to generate the minterms, and an OR gate to form the sum. The output lines of the

decoder corresponding to the minterms of the function are used as inputs to the or gate. Any

combinational circuit with n inputs and m outputs can be implemented with an n-to-2n

decoder with m

OR gates. Suitable when a circuit has many outputs, and each output function is expressed with few

minterms.


82

Truth Table

Circuit diagram:


83

Outputs:

Y0 = D4 + D5 + D6 + D7

Y1 = D2 + D3 + D6 + D7

Y2 = D1 + D3 + D5 + D7

3-8 decoder logic circuit:


84

Truth Table for 3-8 Decoder:

PROCEDURE:

1. Construct the circuit as per the diagram

2. Switch on the power supply.

3. Apply the necessary input and observe the outputs to verify the truth table.

4. The truth table and a design of 8 to 3 Encoder, 3 to 8 decoder are given.

5. Realize this circuit on your board by using logic circuit.

6. Connect three inputs x,y,z to the switches & eight outputs vice-versa.

7. Connect the functions outputs to LEDs.

8. Verify input/output relation (Truth table) of this converter.


85


1. What is Encoder?

2. What is Decoder?

3. What is the principle behind Decoder?

4. Which circuit is used in memory location finding?

5. What Logic behind encoder?


7. Where Decoder used in aircraft applications?

8. Arrive at the Boolean expression for Decoder using karnaugh map.

RESULT

Thus an 8 x 3 encoder and 3x8 Decoder is constructed and verified by using logic gates in digital

IC trainer.


86

Ex. No. 11(A) IMPLEMENTATION OF SHIFT REGISTERS

OBJECTIVE:

To implement and verify the truth table of a serial in serial out shift register.

APPARATUS REQUIRED:



2. D Flip Flop IC 7474 2


THEORY:

A register capable of shifting its binary information either to the left or to the right is called a shift

register. The logical configuration of a shift register consists of a chain of flip flops connected in

cascade with the output of one flip flop connected to the input of the next flip flop. All the flip flops

receive a common clock pulse which causes the shift from one stage to the next.

The Q output of a D flip flop is connected to the D input of the flip flop to the left. Each clock pulse

shifts the contents of the register one bit position to the right. The serial input determines, what goes into

the right most flip flop during the shift. The serial output is taken from the output of the left most flip

flop prior to the application of a pulse. Although this register shifts its contents to its left, if we turn the

page upside down we find that the register shifts its contents to the right. Thus a unidirectional shift

register can function either as a shift right or a shift left register.



87

CIRCUIT DIAGRAM:

TRUTH TABLE:

For a serial data input of 1101,

S.NO CLOCK

PULSE

INPUTS OUTPUTS

D1 D2 D3 D4 Q1 Q2 Q3 Q4

1 1 1 X X X 1 X X X

2 2 1 1 X X 1 1 X X

3 3 0 1 1 X 0 1 1 X

4 4 1 0 1 1 1 0 1 1

5 5 X 1 0 1 X 1 0 1

6 6 X X 1 0 1 X 1 0

7 7 X X X 1 0 X X 1

8 8 X X X X X X X X

PROCEDURE:


2. Apply the input and verify the truth table of the counter.


88


1. What is register?

2. What is sequential circuit?

3. What is the principle of behind shift register?

4. What is Flip flop?

5. What is race around condition?

6. Explain the function of d flip flop.

7. Where shift register used in practical applications?

8. How the memory is organized?

RESULT:

The truth table of a serial in serial out left shift register was hence verified.


89

Ex. No.11 (B) TIMER IC (ASTABLE MULTIVIBRATOR)

Design an Astable multivibrator with 65% duty cycle at 4 KHz frequency, assume C= 0.01 µF.

[Design can be changed by changing the Duty cycle and frequency]

OBJECTIVE:

To design an Astable multivibrator circuit for the given specifications using 555 Timer IC.

APPARATUS REQUIRED:

S. No Name of the Apparatus Range Quantity

1. Function Generator 3 MHz 1

2. CRO 30 MHz 1

3. Dual RPS 0 – 30 V 1

4. Timer IC IC 555 1

5. Bread Board 1

6. Resistors

7. Capacitors

8. Connecting wires and probes As required

THEORY:

An astable multivibrator, often called a free-running multivibrator, is a rectangular-wave-generating

circuit. This circuit do not require an external trigger to change the state of the output. The time during

which the output is either high or low is determined by two resistors and a capacitor, which are

connected externally to the 555 timer. The time during which the capacitor charges from 1/3 Vcc to 2/3

Vcc is equal to the time the output is high and is given by,

tc = 0.69 (R1 + R2) C

Similarly the time during which the capacitor discharges from 2/3 Vcc to 1/3 Vcc is equal to the time the

output is low and is given by,

td = 0.69 (R2) C

Thus the total time period of the output waveform is,

T = tc + td = 0.69 (R1 + 2 R2) C

The term duty cycle is often used in conjunction with the astable multivibrator. The duty cycle is the

ratio of the time tc during which the output is high to the total time period T. It is generally expressed in

percentage. In equation form,

% duty cycle = [(R1 + R2) / (R1 + 2 R2)] x 100


90

PIN DIAGRAM:

CIRCUIT DIAGRAM OF ASTABLE MULTIVIBRATOR


91

DESIGN:

Given f= 4 KHz,

Therefore, Total time period, T = 1/f = ____________

We know, duty cycle = tc / T

Therefore, tc = ------------------------

and td = ____________

We also know for an astable multivibrator

td = 0.69 (R2) C

Therefore, R2 = _____________

tc = 0.69 (R1 + R2) C

Therefore, R1 = _____________

PROCEDURE:

1. Connections are given as per the circuit diagram.

2. + 5V supply is given to the + Vcc terminal of the timer IC.

3. At pin 3 the output waveform is observed with the help of a CRO

4. At pin 6 the capacitor voltage is obtained in the CRO and the V0 and Vc voltage waveforms are

plotted in a graph sheet.

OBSERVATIONS:

S.No Waveforms

Amplitude

( No. of div x

Volts per div )

Time period

( No. of div x

Time per div )

tc td

1.

Output Voltage , Vo

2.

Capacitor voltage , Vc


92


1. What is Integrated circuit?

2. What is 555 timer?

3. What is the principle of behind IC 555?

4. Which circuit called astable multivibrator?

5. What is CRO?


7. Where Timer used in aircraft applications?

RESULT:

Thus the design of the Astable multivibrator circuit was done and the output voltage and capacitor

voltage waveforms were obtained.


93

EX.NO.12. STUDY ABOUT THE CONFIGURATION OF MIL STD 1553B

DATA BUS

OBJECTIVE:

To study architecture, transfer modes and coupling methods of MIL STD 1553B data bus.

THEORY:

In recent years, the use of digital techniques in aircraft equipment has greatly increased, as

have the number of avionics subsystems and the volume of data processed by them.

Because analog point-to-point wire bundles are inefficient and cumbersome means of

interconnecting the sensors, computers, actuators, indicators, and other equipment onboard the

modern military vehicle, a serial digital multiplex data bus was developed. MIL-STD-1553 defines


94

all aspects of the bus, therefore, many groups working with the military tri-services have chosen to

adopt it.

The 1553 multiplex data bus provides integrated, centralized system control and a standard

interface for all equipment connected to the bus. The bus concept provides a means by which all bus

traffic is available to be accessed with a single connection for testing and interfacing with the system.

The standard defines operation of a serial data bus that interconnects multiple devices via a twisted,

shielded pair of wires. The system implements a command-response format.

MIL-STD-1553, "Aircraft Internal Time-Division Command/Response Multiplex Data Bus,"

has been in use since 1973 and is widely applied. MIL-STD-1553 is referred to as "1553" with the

appropriate revision letter (A or B) as a suffix. The basic difference between the 1553A and the

1553B is that in the 1553B, the options are defined rather than being left for the user to define as

required. It was found that when the standard did not define an item, there was no coordination in its

use. Hardware and software had to be redesigned for each new application. The primary goal of the

1553B was to provide flexibility without creating new designs for each new user. This was

accomplished by specifying the electrical interfaces explicitly so that compatibility between designs

by different manufacturers could be electrically interchangeable.

Components of MIL-STD-1553 data bus:

Bus Controller - The bus controller (BC) is the terminal that initiates information transfers on the data

bus. It sends commands to the remote terminals which reply with a response. The bus will support

multiple controllers, but only one may be active at a time. Other requirements, according to 1553, are:

(1) it is "the key part of the data bus system," and (2) "the sole control of information transmission on

the bus shall reside with the bus controller."

Bus Monitor - 1553 defines the bus monitor as "the terminal assigned the task of receiving bus traffic

and extracting selected information to be used at a later time." Bus monitors are frequently used for

instrumentation.

Remote Terminal - Any terminal not operating in either the bus controller or bus monitor mode is

operating in the remote terminal (RT) mode. Remote terminals are the largest group of bus

components.


95

MODULATION:

WORD FORMATS

Bus traffic or communications travels along the bus in words. A word in MIL-STD-1553 is a

sequence of 20 bit times consisting of a 3 bit-time sync wave form, 16 bits of data, and 1 parity

check bit. This is the word as it is transmitted on the bus; 1553 terminals add the sync and parity

before transmission and remove them during reception. Therefore, the nominal word size is 16 bits,

with the most significant bit (MSB) first.

There are three types of words: command, status, and data. A packet is defined to have no intermessage

gaps. The time between the last word of a controller message and the return of the terminal status byte is

4-12 microseconds. The time between status byte and the next controller message is undefined. Figure

3 illustrates these three formats.The signal is transferred over the data bus using serial digital pulse code

modulation.

COMMAND WORD

Command words are transmitted only by the bus controller and always consist of:

1. 3 bit-time sync pattern

2. 5 bit RT address field

3. 1 Transmit/Receive (T/R) field

4. 5 bit subaddress/mode field

5. 5 bit word count/mode code field

6. 1 parity check bit.


96

DATA WORD

Data words are transmitted either by the BC or by the RT in response to a BC request. The

standard allows a maximum of 32 data words to be sent in a packet with a command word before a

status response must be returned.

Data words always consist of:

i. 3 bit-time sync pattern (opposite in polarity from command and status words)

ii. 16 bit data field

iii. 1 parity check bit.

STATUS WORD

Status words are transmitted by the RT in response to command messages from the BC and

consist of:

i. 3 bit-time sync pattern (same as for a command word)

ii. 5 bit address of the responding RT

iii. 11 bit status field

iv. 1 parity check bit.


97

INFORMATION TRANSFERS

Three basic types of information transfers are defined by 1553:

a. Bus Controller to Remote Terminal transfers

b. Remote Terminal to Bus Controller transfers

c. Remote Terminal to Remote Terminal transfers.


98


1. Explain MIL-STD 1553B components?

2. Explain the status word of MIL-STD 1553B.

3. Explain the bus controller and Remote terminal of MIL-STD 1553B

4. What is the bus speed of MIL STD 1553B?

5. How many RT can be connected to MIL STD 1553B?

6. What is data bus?

7. What is Manchester encoding?

8. What are the information transfers in MIL-STD-1553 data bus?

RESULT:

Thus the configuration lay out, Word formats and Information transfer of MIL-STD-1553B data

bus is studied.

Documents

Avionics Digital 2016